Index of /Programmierbare Logik/APL/Test

[ICO]NameLast modifiedSizeDescription
[PARENTDIR]Parent Directory  -  
[ ]Test.pof2022-12-24 03:16 2.0M 
[ ]Test.sof2022-12-24 03:16 821K 
[IMG]Test.fit.rpt2022-12-24 03:16 275K 
[ ]Test.sim.rpt2022-12-24 03:16 153K 
[ ]altfp_mult0.vhd2022-12-24 03:15 133K 
[ ]Test.pin2022-12-24 03:16 77K 
[ ]test_assignment_defaults.qdf2022-12-24 03:16 51K 
[IMG]lpm_mult2_wave0.jpg2022-12-24 03:16 33K 
[ ]test.sta.rpt2022-12-24 03:16 31K 
[IMG]lpm_mult1_wave0.jpg2022-12-24 03:16 30K 
[ ]Waveform1.vwf2022-12-24 03:16 27K 
[ ]DE2_Default.qsf2022-12-24 03:15 24K 
[ ]Test.qsf2022-12-24 03:16 24K 
[ ]altmult_add0.vhd2022-12-24 03:15 21K 
[ ]audio_unit.bdf2022-12-24 03:15 21K 
[ ]test.bdf2022-12-24 03:16 21K 
[ ]Test.vwf2022-12-24 03:16 20K 
[ ]Equalizer.bdf2022-12-24 03:15 18K 
[ ]test.map.rpt2022-12-24 03:16 17K 
[ ]altmult_add0.bsf2022-12-24 03:15 16K 
[ ]audio_pll_2.vhd2022-12-24 03:15 15K 
[ ]audio_pll_1.vhd2022-12-24 03:15 15K 
[ ]clock_generator.bdf2022-12-24 03:15 12K 
[ ]Test.tan.rpt2022-12-24 03:16 12K 
[ ]test.flow.rpt2022-12-24 03:16 9.7K 
[ ]filter_unit.bdf2022-12-24 03:15 7.8K 
[ ]Test.asm.rpt2022-12-24 03:16 7.5K 
[ ]audio_clock_generator.bdf2022-12-24 03:15 7.4K 
[ ]dec_24bit_to_7seg.vhd2022-12-24 03:15 5.2K 
[ ]lpm_mult0.vhd2022-12-24 03:16 4.9K 
[ ]lpm_mult2.vhd2022-12-24 03:16 4.8K 
[ ]lpm_mult1.vhd2022-12-24 03:16 4.8K 
[ ]iir_sub_1.vhd2022-12-24 03:16 4.7K 
[ ]iir_add_1.vhd2022-12-24 03:16 4.7K 
[ ]iir_add_2.vhd2022-12-24 03:16 4.7K 
[ ]iir_mul_1.vhd2022-12-24 03:16 4.7K 
[ ]lpm_mult3.vhd2022-12-24 03:16 4.7K 
[ ]audio_unit.bsf2022-12-24 03:15 4.4K 
[ ]UNUSED.hex2022-12-24 03:16 4.3K 
[ ]altfp_mult0.bsf2022-12-24 03:15 3.9K 
[ ]filter_unit.bsf2022-12-24 03:15 3.1K 
[ ]register_test.bsf2022-12-24 03:16 3.0K 
[ ]audio_pll_2.bsf2022-12-24 03:15 2.9K 
[ ]audio_pll_1.bsf2022-12-24 03:15 2.9K 
[ ]i2c_transmitter.vhd2022-12-24 03:16 2.9K 
[ ]filter_arithmetic_unit.bsf2022-12-24 03:15 2.9K 
[ ]audio_input_register.vhd2022-12-24 03:15 2.6K 
[ ]Test.vhd2022-12-24 03:16 2.6K 
[ ]dec_24bit_to_7seg.bsf2022-12-24 03:15 2.6K 
[ ]audio_input_register.bsf2022-12-24 03:15 2.5K 
[ ]audio_test.bsf2022-12-24 03:15 2.5K 
[ ]audio_output_register.bsf2022-12-24 03:15 2.5K 
[ ]test_a.bsf2022-12-24 03:16 2.5K 
[ ]iir_mul_1.bsf2022-12-24 03:16 2.4K 
[ ]lpm_mult3.bsf2022-12-24 03:16 2.4K 
[ ]audio_data_to_LEDs.bsf2022-12-24 03:15 2.3K 
[ ]i2c_transmitter.bsf2022-12-24 03:15 2.3K 
[ ]clock_generator.bsf2022-12-24 03:15 2.3K 
[ ]iir_sub_1.bsf2022-12-24 03:16 2.2K 
[ ]iir_add_1.bsf2022-12-24 03:16 2.2K 
[ ]iir_add_2.bsf2022-12-24 03:16 2.2K 
[ ]lpm_mult2.bsf2022-12-24 03:16 2.1K 
[ ]lpm_mult1.bsf2022-12-24 03:16 2.1K 
[ ]filter_arithmetic_unit.vhd.bak2022-12-24 03:15 2.1K 
[ ]Test.qsf.bak2022-12-24 03:16 2.1K 
[ ]lpm_mult0.bsf2022-12-24 03:16 2.0K 
[ ]filter_arithmetic_unit.vhd2022-12-24 03:15 2.0K 
[ ]test_a.vhd2022-12-24 03:16 2.0K 
[ ]i2c_data_register.vhd2022-12-24 03:15 1.9K 
[ ]i2c_data_register.bsf2022-12-24 03:15 1.9K 
[ ]audio_output_register.vhd2022-12-24 03:15 1.9K 
[ ]audio_clock_generator.bsf2022-12-24 03:15 1.9K 
[ ]test_constant.bsf2022-12-24 03:16 1.8K 
[ ]test1.bsf2022-12-24 03:16 1.7K 
[ ]audio_clock_generator.vhd2022-12-24 03:15 1.7K 
[ ]test_a.vhd.bak2022-12-24 03:16 1.6K 
[ ]dec_4bit_to_7seg.bsf2022-12-24 03:15 1.6K 
[ ]audio_clock_divider.bsf2022-12-24 03:15 1.6K 
[ ]iir_add_sub.cnx2022-12-24 03:16 1.3K 
[ ]mul1.cnx2022-12-24 03:16 1.3K 
[ ]Test.qpf2022-12-24 03:16 1.2K 
[ ]test_vhdl.bsf2022-12-24 03:16 1.2K 
[ ]dec_4bit_to_7seg.vhd.bak2022-12-24 03:15 1.1K 
[ ]dec_4bit_to_7seg.vhd2022-12-24 03:15 1.1K 
[ ]iir_sub_1.cmp2022-12-24 03:16 1.0K 
[ ]iir_add_1.cmp2022-12-24 03:16 1.0K 
[ ]iir_mul_1.cmp2022-12-24 03:16 1.0K 
[ ]lpm_mult3.cmp2022-12-24 03:16 1.0K 
[ ]lpm_mult2.cmp2022-12-24 03:16 1.0K 
[ ]lpm_mult1.cmp2022-12-24 03:16 1.0K 
[ ]iir_add_2.cmp2022-12-24 03:16 1.0K 
[ ]test.vhdl2022-12-24 03:16 948  
[ ]audio_data_to_LEDs.vhd2022-12-24 03:15 903  
[ ]iir_sub_1.inc2022-12-24 03:16 888  
[ ]iir_add_1.inc2022-12-24 03:16 888  
[ ]iir_mul_1.inc2022-12-24 03:16 887  
[ ]lpm_mult3.inc2022-12-24 03:16 886  
[ ]iir_add_2.inc2022-12-24 03:16 885  
[ ]audio_test.vhd2022-12-24 03:15 808  
[ ]audio_clock_divider.vhd2022-12-24 03:15 715  
[ ]Test.tan.summary2022-12-24 03:16 715  
[ ]Test.map.summary2022-12-24 03:16 665  
[ ]register_test.vhd.bak2022-12-24 03:16 646  
[ ]register_test.vhd2022-12-24 03:16 646  
[ ]test_constant.vhd2022-12-24 03:16 598  
[IMG]Test.fit.summary2022-12-24 03:16 594  
[TXT]lpm_mult2_waveforms.html2022-12-24 03:16 572  
[TXT]lpm_mult1_waveforms.html2022-12-24 03:16 572  
[ ]iir_sub_1.qip2022-12-24 03:16 553  
[ ]iir_add_2.qip2022-12-24 03:16 553  
[ ]iir_add_1.qip2022-12-24 03:16 553  
[ ]lpm_mult3.qip2022-12-24 03:16 550  
[ ]iir_mul_1.qip2022-12-24 03:16 550  
[ ]test_vhdl.vhd2022-12-24 03:16 539  
[ ]test_vhdl.vhd.bak2022-12-24 03:16 533  
[ ]dec_24bit_to_7-seg.vhd2022-12-24 03:15 440  
[ ]test1.vhd2022-12-24 03:16 416  
[ ]test1.vhd.bak2022-12-24 03:16 415  
[ ]test_constant.vhd.bak2022-12-24 03:16 410  
[ ]test.jdi2022-12-24 03:16 315  
[ ]Test.dpf2022-12-24 03:16 239  
[ ]test.sta.summary2022-12-24 03:16 223  
[ ]mul1.cnxerr2022-12-24 03:16 203  
[ ]iir_add_sub.cnxerr2022-12-24 03:16 203  
[ ]lpm_mult3_inst.vhd2022-12-24 03:16 117  
[ ]iir_sub_1_inst.vhd2022-12-24 03:16 117  
[ ]iir_mul_1_inst.vhd2022-12-24 03:16 117  
[ ]iir_add_2_inst.vhd2022-12-24 03:16 117  
[ ]iir_add_1_inst.vhd2022-12-24 03:16 117  
[ ]audio_pll_2_inst.vhd2022-12-24 03:15 91  
[ ]audio_pll_1_inst.vhd2022-12-24 03:15 91  
[ ]Test.qws2022-12-24 03:16 90  
[ ]Test.done2022-12-24 03:16 26  
[ ]testdat.in2022-12-24 03:16 7  
[ ]testdat.in.bak2022-12-24 03:16 5  
[ ]mul1.qip2022-12-24 03:16 0  
[ ]iir_add_sub.qip2022-12-24 03:16 0  
[DIR]incremental_db/2024-10-20 18:38 -  
[DIR]greybox_tmp/2024-10-20 17:26 -  
[DIR]db/2024-10-20 17:26 -  
Apache/2.4.57 (Debian) Server at studium.doeffinger.net Port 80