Analysis & Synthesis report for test
Mon Jun 11 21:14:36 2012
Quartus II 64-Bit Version 11.1 Build 173 11/01/2011 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2011 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                   ;
+------------------------------------+-------------------------------------------+
; Analysis & Synthesis Status        ; Failed - Mon Jun 11 21:14:36 2012         ;
; Quartus II 64-Bit Version          ; 11.1 Build 173 11/01/2011 SJ Full Version ;
; Revision Name                      ; test                                      ;
; Top-level Entity Name              ; test                                      ;
; Family                             ; Cyclone II                                ;
; Total logic elements               ; N/A until Partition Merge                 ;
;     Total combinational functions  ; N/A until Partition Merge                 ;
;     Dedicated logic registers      ; N/A until Partition Merge                 ;
; Total registers                    ; N/A until Partition Merge                 ;
; Total pins                         ; N/A until Partition Merge                 ;
; Total virtual pins                 ; N/A until Partition Merge                 ;
; Total memory bits                  ; N/A until Partition Merge                 ;
; Embedded Multiplier 9-bit elements ; N/A until Partition Merge                 ;
; Total PLLs                         ; N/A until Partition Merge                 ;
+------------------------------------+-------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                        ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                     ; Setting            ; Default Value      ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                     ; EP2C35F672C6       ;                    ;
; Top-level entity name                                                      ; test               ; test               ;
; Family name                                                                ; Cyclone II         ; Cyclone IV GX      ;
; Use smart compilation                                                      ; Off                ; Off                ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
; Enable compact report table                                                ; Off                ; Off                ;
; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
; Preserve fewer node names                                                  ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
; State Machine Processing                                                   ; Auto               ; Auto               ;
; Safe State Machine                                                         ; Off                ; Off                ;
; Extract Verilog State Machines                                             ; On                 ; On                 ;
; Extract VHDL State Machines                                                ; On                 ; On                 ;
; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
; Parallel Synthesis                                                         ; Off                ; Off                ;
; DSP Block Balancing                                                        ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                         ; On                 ; On                 ;
; Power-Up Don't Care                                                        ; On                 ; On                 ;
; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
; Remove Duplicate Registers                                                 ; On                 ; On                 ;
; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
; Optimization Technique                                                     ; Balanced           ; Balanced           ;
; Carry Chain Length                                                         ; 70                 ; 70                 ;
; Auto Carry Chains                                                          ; On                 ; On                 ;
; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
; Auto ROM Replacement                                                       ; On                 ; On                 ;
; Auto RAM Replacement                                                       ; On                 ; On                 ;
; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
; Strict RAM Replacement                                                     ; Off                ; Off                ;
; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
; Auto Resource Sharing                                                      ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
; Timing-Driven Synthesis                                                    ; Off                ; Off                ;
; Report Parameter Settings                                                  ; On                 ; On                 ;
; Report Source Assignments                                                  ; On                 ; On                 ;
; Report Connectivity Checks                                                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
; HDL message level                                                          ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
; Clock MUX Protection                                                       ; On                 ; On                 ;
; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
; Block Design Naming                                                        ; Auto               ; Auto               ;
; SDC constraint protection                                                  ; Off                ; Off                ;
; Synthesis Effort                                                           ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
; Synthesis Seed                                                             ; 1                  ; 1                  ;
+----------------------------------------------------------------------------+--------------------+--------------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 2      ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
    Info: Version 11.1 Build 173 11/01/2011 SJ Full Version
    Info: Processing started: Mon Jun 11 21:14:35 2012
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Test -c test
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (12021): Found 2 design units, including 1 entities, in source file lpm_mult3.vhd
    Info (12022): Found design unit 1: lpm_mult3-SYN
    Info (12023): Found entity 1: lpm_mult3
Info (12021): Found 1 design units, including 1 entities, in source file test.bdf
    Info (12023): Found entity 1: test
Info (12021): Found 2 design units, including 1 entities, in source file test_constant.vhd
    Info (12022): Found design unit 1: test_constant-behavior
    Info (12023): Found entity 1: test_constant
Info (12021): Found 2 design units, including 1 entities, in source file iir_mul_1.vhd
    Info (12022): Found design unit 1: iir_mul_1-SYN
    Info (12023): Found entity 1: iir_mul_1
Info (12021): Found 2 design units, including 1 entities, in source file iir_add_1.vhd
    Info (12022): Found design unit 1: iir_add_1-SYN
    Info (12023): Found entity 1: iir_add_1
Info (12021): Found 2 design units, including 1 entities, in source file iir_sub_1.vhd
    Info (12022): Found design unit 1: iir_sub_1-SYN
    Info (12023): Found entity 1: iir_sub_1
Info (12021): Found 2 design units, including 1 entities, in source file iir_add_2.vhd
    Info (12022): Found design unit 1: iir_add_2-SYN
    Info (12023): Found entity 1: iir_add_2
Info (12127): Elaborating entity "test" for the top level hierarchy
Error (275023): Width mismatch in y -- source is ""result[23..0]" (ID iir_add_1:inst9)"
Error (275023): Width mismatch in w0 -- source is ""result[15..0]" (ID iir_sub_1:inst7)"
Error (275024): Width mismatch in port "dataa[15..0]" of instance "inst2" and type iir_mul_1 -- source is ""a2""
Error (275024): Width mismatch in port "datab[7..0]" of instance "inst2" and type iir_mul_1 -- source is ""w2""
Error (275024): Width mismatch in port "dataa[15..0]" of instance "inst4" and type iir_mul_1 -- source is ""w1""
Error (275024): Width mismatch in port "datab[7..0]" of instance "inst4" and type iir_mul_1 -- source is ""b1""
Error (275024): Width mismatch in port "dataa[15..0]" of instance "inst5" and type iir_mul_1 -- source is ""w2""
Error (275024): Width mismatch in port "datab[7..0]" of instance "inst5" and type iir_mul_1 -- source is ""b2""
Error (275024): Width mismatch in port "dataa[15..0]" of instance "inst" and type iir_mul_1 -- source is ""x""
Error (275024): Width mismatch in port "datab[7..0]" of instance "inst" and type iir_mul_1 -- source is ""s1""
Error (275024): Width mismatch in port "dataa[15..0]" of instance "inst1" and type iir_mul_1 -- source is ""a1""
Error (275024): Width mismatch in port "datab[7..0]" of instance "inst1" and type iir_mul_1 -- source is ""w1""
Error (275024): Width mismatch in port "dataa[15..0]" of instance "inst7" and type iir_sub_1 -- source is ""result[23..0]" (ID iir_mul_1:inst)"
Error (275024): Width mismatch in port "datab[15..0]" of instance "inst7" and type iir_sub_1 -- source is ""result[23..0]" (ID iir_add_1:inst6)"
Error (275024): Width mismatch in port "datab[7..0]" of instance "inst3" and type iir_mul_1 -- source is ""b0""
Error (12153): Can't elaborate top-level user hierarchy
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 16 errors, 1 warning
    Error: Peak virtual memory: 416 megabytes
    Error: Processing ended: Mon Jun 11 21:14:36 2012
    Error: Elapsed time: 00:00:01
    Error: Total CPU time (on all processors): 00:00:01


