Analysis & Synthesis report for uhr
Thu May 17 09:18:43 2012
Quartus II Version 7.2 Build 151 09/26/2007 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Registers Removed During Synthesis
  8. General Register Statistics
  9. Multiplexer Restructuring Statistics (Restructuring Performed)
 10. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                 ;
+------------------------------------+-----------------------------------------+
; Analysis & Synthesis Status        ; Successful - Thu May 17 09:18:43 2012   ;
; Quartus II Version                 ; 7.2 Build 151 09/26/2007 SJ Web Edition ;
; Revision Name                      ; uhr                                     ;
; Top-level Entity Name              ; uhr                                     ;
; Family                             ; Cyclone II                              ;
; Total logic elements               ; 172                                     ;
;     Total combinational functions  ; 172                                     ;
;     Dedicated logic registers      ; 54                                      ;
; Total registers                    ; 54                                      ;
; Total pins                         ; 61                                      ;
; Total virtual pins                 ; 0                                       ;
; Total memory bits                  ; 0                                       ;
; Embedded Multiplier 9-bit elements ; 0                                       ;
; Total PLLs                         ; 0                                       ;
+------------------------------------+-----------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                            ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                         ; Setting            ; Default Value      ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                         ; EP2C35F672C6       ;                    ;
; Top-level entity name                                                          ; uhr                ; uhr                ;
; Family name                                                                    ; Cyclone II         ; Stratix II         ;
; Use Generated Physical Constraints File                                        ; Off                ;                    ;
; Use smart compilation                                                          ; Off                ; Off                ;
; Maximum processors allowed for parallel compilation                            ; 1                  ; 1                  ;
; Restructure Multiplexers                                                       ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                            ; Off                ; Off                ;
; Preserve fewer node names                                                      ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                      ; Off                ; Off                ;
; Verilog Version                                                                ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                                   ; VHDL93             ; VHDL93             ;
; State Machine Processing                                                       ; Auto               ; Auto               ;
; Safe State Machine                                                             ; Off                ; Off                ;
; Extract Verilog State Machines                                                 ; On                 ; On                 ;
; Extract VHDL State Machines                                                    ; On                 ; On                 ;
; Ignore Verilog initial constructs                                              ; Off                ; Off                ;
; Add Pass-Through Logic to Inferred RAMs                                        ; On                 ; On                 ;
; Parallel Synthesis                                                             ; Off                ; Off                ;
; DSP Block Balancing                                                            ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                             ; On                 ; On                 ;
; Power-Up Don't Care                                                            ; On                 ; On                 ;
; Remove Redundant Logic Cells                                                   ; Off                ; Off                ;
; Remove Duplicate Registers                                                     ; On                 ; On                 ;
; Ignore CARRY Buffers                                                           ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                         ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                          ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore LCELL Buffers                                                           ; Off                ; Off                ;
; Ignore SOFT Buffers                                                            ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                                 ; Off                ; Off                ;
; Optimization Technique -- Cyclone II/Cyclone III                               ; Balanced           ; Balanced           ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II/Cyclone III ; 70                 ; 70                 ;
; Auto Carry Chains                                                              ; On                 ; On                 ;
; Auto Open-Drain Pins                                                           ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                          ; Off                ; Off                ;
; Perform gate-level register retiming                                           ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax                         ; On                 ; On                 ;
; Auto ROM Replacement                                                           ; On                 ; On                 ;
; Auto RAM Replacement                                                           ; On                 ; On                 ;
; Auto Shift Register Replacement                                                ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                                  ; On                 ; On                 ;
; Allow Synchronous Control Signals                                              ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                         ; Off                ; Off                ;
; Auto RAM to Logic Cell Conversion                                              ; Off                ; Off                ;
; Auto Resource Sharing                                                          ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                             ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                             ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                                  ; Off                ; Off                ;
; Ignore translate_off and synthesis_off directives                              ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                             ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                             ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                               ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                                   ; Normal compilation ; Normal compilation ;
; HDL message level                                                              ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                                ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                       ; 100                ; 100                ;
; Clock MUX Protection                                                           ; On                 ; On                 ;
; Block Design Naming                                                            ; Auto               ; Auto               ;
+--------------------------------------------------------------------------------+--------------------+--------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                    ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                    ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------+
; uhr.bdf                          ; yes             ; User Block Diagram/Schematic File  ; D:/juergen/Projekte/VHDL/uhr/uhr.bdf                            ;
; uhr_controller.vhd               ; yes             ; User VHDL File                     ; D:/juergen/Projekte/VHDL/uhr/uhr_controller.vhd                 ;
; bus_to_4bit.vhd                  ; yes             ; User VHDL File                     ; D:/juergen/Projekte/VHDL/uhr/bus_to_4bit.vhd                    ;
; not_7seg.vhd                     ; yes             ; User VHDL File                     ; D:/juergen/Projekte/VHDL/uhr/not_7seg.vhd                       ;
; 7449.bdf                         ; yes             ; Megafunction                       ; d:/juergen/altera/72/quartus/libraries/others/maxplus2/7449.bdf ;
+----------------------------------+-----------------+------------------------------------+-----------------------------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 172   ;
;                                             ;       ;
; Total combinational functions               ; 172   ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 63    ;
;     -- 3 input functions                    ; 53    ;
;     -- <=2 input functions                  ; 56    ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 134   ;
;     -- arithmetic mode                      ; 38    ;
;                                             ;       ;
; Total registers                             ; 54    ;
;     -- Dedicated logic registers            ; 54    ;
;     -- I/O registers                        ; 0     ;
;                                             ;       ;
; I/O pins                                    ; 61    ;
; Maximum fan-out node                        ; inst1 ;
; Maximum fan-out                             ; 50    ;
; Total fan-out                               ; 678   ;
; Average fan-out                             ; 2.36  ;
+---------------------------------------------+-------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                              ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name      ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------+--------------+
; |uhr                       ; 172 (1)           ; 54 (1)       ; 0           ; 0            ; 0       ; 0         ; 61   ; 0            ; |uhr                     ; work         ;
;    |7449:inst18|           ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |uhr|7449:inst18         ; work         ;
;    |7449:inst20|           ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |uhr|7449:inst20         ; work         ;
;    |7449:inst22|           ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |uhr|7449:inst22         ; work         ;
;    |7449:inst24|           ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |uhr|7449:inst24         ; work         ;
;    |7449:inst26|           ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |uhr|7449:inst26         ; work         ;
;    |7449:inst28|           ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |uhr|7449:inst28         ; work         ;
;    |7449:inst30|           ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |uhr|7449:inst30         ; work         ;
;    |7449:inst32|           ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |uhr|7449:inst32         ; work         ;
;    |uhr_controller:inst|   ; 115 (115)         ; 53 (53)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |uhr|uhr_controller:inst ; work         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+----------------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                                     ;
+--------------------------------------------+-------------------------------------------+
; Register name                              ; Reason for Removal                        ;
+--------------------------------------------+-------------------------------------------+
; uhr_controller:inst|\clock:icsec[0]        ; Merged with uhr_controller:inst|csec[0]   ;
; uhr_controller:inst|\clock:icsec[1]        ; Merged with uhr_controller:inst|csec[1]   ;
; uhr_controller:inst|\clock:icsec[2]        ; Merged with uhr_controller:inst|csec[2]   ;
; uhr_controller:inst|\clock:icsec[3]        ; Merged with uhr_controller:inst|csec[3]   ;
; uhr_controller:inst|\clock:idsec[0]        ; Merged with uhr_controller:inst|dsec[0]   ;
; uhr_controller:inst|\clock:idsec[1]        ; Merged with uhr_controller:inst|dsec[1]   ;
; uhr_controller:inst|\clock:idsec[2]        ; Merged with uhr_controller:inst|dsec[2]   ;
; uhr_controller:inst|\clock:idsec[3]        ; Merged with uhr_controller:inst|dsec[3]   ;
; uhr_controller:inst|\clock:isec[0]         ; Merged with uhr_controller:inst|sec[0]    ;
; uhr_controller:inst|\clock:isec[1]         ; Merged with uhr_controller:inst|sec[1]    ;
; uhr_controller:inst|\clock:isec[2]         ; Merged with uhr_controller:inst|sec[2]    ;
; uhr_controller:inst|\clock:isec[3]         ; Merged with uhr_controller:inst|sec[3]    ;
; uhr_controller:inst|\clock:isec10[0]       ; Merged with uhr_controller:inst|sec10[0]  ;
; uhr_controller:inst|\clock:isec10[1]       ; Merged with uhr_controller:inst|sec10[1]  ;
; uhr_controller:inst|\clock:isec10[2]       ; Merged with uhr_controller:inst|sec10[2]  ;
; uhr_controller:inst|\clock:isec10[3]       ; Merged with uhr_controller:inst|sec10[3]  ;
; uhr_controller:inst|\clock:imin[0]         ; Merged with uhr_controller:inst|min[0]    ;
; uhr_controller:inst|\clock:imin[1]         ; Merged with uhr_controller:inst|min[1]    ;
; uhr_controller:inst|\clock:imin[2]         ; Merged with uhr_controller:inst|min[2]    ;
; uhr_controller:inst|\clock:imin[3]         ; Merged with uhr_controller:inst|min[3]    ;
; uhr_controller:inst|\clock:imin10[0]       ; Merged with uhr_controller:inst|min10[0]  ;
; uhr_controller:inst|\clock:imin10[1]       ; Merged with uhr_controller:inst|min10[1]  ;
; uhr_controller:inst|\clock:imin10[2]       ; Merged with uhr_controller:inst|min10[2]  ;
; uhr_controller:inst|\clock:imin10[3]       ; Merged with uhr_controller:inst|min10[3]  ;
; uhr_controller:inst|\clock:ihour[0]        ; Merged with uhr_controller:inst|hour[0]   ;
; uhr_controller:inst|\clock:ihour[1]        ; Merged with uhr_controller:inst|hour[1]   ;
; uhr_controller:inst|\clock:ihour[2]        ; Merged with uhr_controller:inst|hour[2]   ;
; uhr_controller:inst|\clock:ihour[3]        ; Merged with uhr_controller:inst|hour[3]   ;
; uhr_controller:inst|\clock:ihour10[0]      ; Merged with uhr_controller:inst|hour10[0] ;
; uhr_controller:inst|\clock:ihour10[1]      ; Merged with uhr_controller:inst|hour10[1] ;
; uhr_controller:inst|\clock:ihour10[2]      ; Merged with uhr_controller:inst|hour10[2] ;
; uhr_controller:inst|\clock:ihour10[3]      ; Merged with uhr_controller:inst|hour10[3] ;
; uhr_controller:inst|sec10[3]               ; Stuck at GND due to stuck port data_in    ;
; uhr_controller:inst|min10[3]               ; Stuck at GND due to stuck port data_in    ;
; uhr_controller:inst|\clock:counter[18..19] ; Stuck at GND due to stuck port data_in    ;
; Total Number of Removed Registers = 36     ;                                           ;
+--------------------------------------------+-------------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 54    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 4     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                  ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output        ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------+
; 3:1                ; 6 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; Yes        ; |uhr|uhr_controller:inst|hour[2]  ;
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |uhr|uhr_controller:inst|min[2]   ;
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |uhr|uhr_controller:inst|min10[3] ;
; 4:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |uhr|uhr_controller:inst|csec[3]  ;
; 4:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |uhr|uhr_controller:inst|dsec[2]  ;
; 4:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |uhr|uhr_controller:inst|sec[3]   ;
; 4:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |uhr|uhr_controller:inst|sec10[3] ;
; 4:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |uhr|uhr_controller:inst|hour[1]  ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Web Edition
    Info: Processing started: Thu May 17 09:18:41 2012
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off uhr -c uhr
Info: Found 1 design units, including 1 entities, in source file uhr.bdf
    Info: Found entity 1: uhr
Info: Found 2 design units, including 1 entities, in source file uhr_controller.vhd
    Info: Found design unit 1: uhr_controller-behavior_uhr_controller
    Info: Found entity 1: uhr_controller
Info: Found 2 design units, including 1 entities, in source file bus_to_4bit.vhd
    Info: Found design unit 1: bus_to_4bit-behavior_bus_to_4bit
    Info: Found entity 1: bus_to_4bit
Info: Found 2 design units, including 1 entities, in source file not_7seg.vhd
    Info: Found design unit 1: not_7seg-behavior_not_7seg
    Info: Found entity 1: not_7seg
Info: Elaborating entity "uhr" for the top level hierarchy
Info: Elaborating entity "not_7seg" for hierarchy "not_7seg:inst19"
Info: Found 1 design units, including 1 entities, in source file ../../../altera/72/quartus/libraries/others/maxplus2/7449.bdf
    Info: Found entity 1: 7449
Info: Elaborating entity "7449" for hierarchy "7449:inst18"
Warning: Processing legacy GDF or BDF entity "7449" with Max+Plus II bus and instance naming rules
Warning: The design contains mutiple Block Design Files, and some design file(s) are using a naming scheme which is different from other design file(s).
Info: Elaborated megafunction instantiation "7449:inst18"
Info: Elaborating entity "bus_to_4bit" for hierarchy "bus_to_4bit:inst10"
Info: Elaborating entity "uhr_controller" for hierarchy "uhr_controller:inst"
Warning (10492): VHDL Process Statement warning at uhr_controller.vhd(150): signal "executed" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at uhr_controller.vhd(151): signal "executed" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at uhr_controller.vhd(152): signal "executed" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at uhr_controller.vhd(153): signal "executed" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at uhr_controller.vhd(155): signal "executed" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Info: Duplicate registers merged to single register
    Info: Duplicate register "uhr_controller:inst|\clock:icsec[0]" merged to single register "uhr_controller:inst|csec[0]"
    Info: Duplicate register "uhr_controller:inst|\clock:icsec[1]" merged to single register "uhr_controller:inst|csec[1]"
    Info: Duplicate register "uhr_controller:inst|\clock:icsec[2]" merged to single register "uhr_controller:inst|csec[2]"
    Info: Duplicate register "uhr_controller:inst|\clock:icsec[3]" merged to single register "uhr_controller:inst|csec[3]"
    Info: Duplicate register "uhr_controller:inst|\clock:idsec[0]" merged to single register "uhr_controller:inst|dsec[0]"
    Info: Duplicate register "uhr_controller:inst|\clock:idsec[1]" merged to single register "uhr_controller:inst|dsec[1]"
    Info: Duplicate register "uhr_controller:inst|\clock:idsec[2]" merged to single register "uhr_controller:inst|dsec[2]"
    Info: Duplicate register "uhr_controller:inst|\clock:idsec[3]" merged to single register "uhr_controller:inst|dsec[3]"
    Info: Duplicate register "uhr_controller:inst|\clock:isec[0]" merged to single register "uhr_controller:inst|sec[0]"
    Info: Duplicate register "uhr_controller:inst|\clock:isec[1]" merged to single register "uhr_controller:inst|sec[1]"
    Info: Duplicate register "uhr_controller:inst|\clock:isec[2]" merged to single register "uhr_controller:inst|sec[2]"
    Info: Duplicate register "uhr_controller:inst|\clock:isec[3]" merged to single register "uhr_controller:inst|sec[3]"
    Info: Duplicate register "uhr_controller:inst|\clock:isec10[0]" merged to single register "uhr_controller:inst|sec10[0]"
    Info: Duplicate register "uhr_controller:inst|\clock:isec10[1]" merged to single register "uhr_controller:inst|sec10[1]"
    Info: Duplicate register "uhr_controller:inst|\clock:isec10[2]" merged to single register "uhr_controller:inst|sec10[2]"
    Info: Duplicate register "uhr_controller:inst|\clock:isec10[3]" merged to single register "uhr_controller:inst|sec10[3]"
    Info: Duplicate register "uhr_controller:inst|\clock:imin[0]" merged to single register "uhr_controller:inst|min[0]"
    Info: Duplicate register "uhr_controller:inst|\clock:imin[1]" merged to single register "uhr_controller:inst|min[1]"
    Info: Duplicate register "uhr_controller:inst|\clock:imin[2]" merged to single register "uhr_controller:inst|min[2]"
    Info: Duplicate register "uhr_controller:inst|\clock:imin[3]" merged to single register "uhr_controller:inst|min[3]"
    Info: Duplicate register "uhr_controller:inst|\clock:imin10[0]" merged to single register "uhr_controller:inst|min10[0]"
    Info: Duplicate register "uhr_controller:inst|\clock:imin10[1]" merged to single register "uhr_controller:inst|min10[1]"
    Info: Duplicate register "uhr_controller:inst|\clock:imin10[2]" merged to single register "uhr_controller:inst|min10[2]"
    Info: Duplicate register "uhr_controller:inst|\clock:imin10[3]" merged to single register "uhr_controller:inst|min10[3]"
    Info: Duplicate register "uhr_controller:inst|\clock:ihour[0]" merged to single register "uhr_controller:inst|hour[0]"
    Info: Duplicate register "uhr_controller:inst|\clock:ihour[1]" merged to single register "uhr_controller:inst|hour[1]"
    Info: Duplicate register "uhr_controller:inst|\clock:ihour[2]" merged to single register "uhr_controller:inst|hour[2]"
    Info: Duplicate register "uhr_controller:inst|\clock:ihour[3]" merged to single register "uhr_controller:inst|hour[3]"
    Info: Duplicate register "uhr_controller:inst|\clock:ihour10[0]" merged to single register "uhr_controller:inst|hour10[0]"
    Info: Duplicate register "uhr_controller:inst|\clock:ihour10[1]" merged to single register "uhr_controller:inst|hour10[1]"
    Info: Duplicate register "uhr_controller:inst|\clock:ihour10[2]" merged to single register "uhr_controller:inst|hour10[2]"
    Info: Duplicate register "uhr_controller:inst|\clock:ihour10[3]" merged to single register "uhr_controller:inst|hour10[3]"
Warning (14130): Reduced register "uhr_controller:inst|sec10[3]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "uhr_controller:inst|min10[3]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "uhr_controller:inst|\clock:counter[19]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "uhr_controller:inst|\clock:counter[18]" with stuck data_in port to stuck value GND
Info: Implemented 237 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 56 output pins
    Info: Implemented 176 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 11 warnings
    Info: Allocated 211 megabytes of memory during processing
    Info: Processing ended: Thu May 17 09:18:43 2012
    Info: Elapsed time: 00:00:02


