Analysis & Synthesis report for test3
Sun Jun 10 19:34:18 2012
Quartus II Version 7.2 Build 151 09/26/2007 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis DSP Block Usage Summary
  8. General Register Statistics
  9. Parameter Settings for User Entity Instance: mul:mul_1|lpm_mult:lpm_mult_component
 10. Parameter Settings for User Entity Instance: div:div_1|lpm_divide:lpm_divide_component
 11. lpm_mult Parameter Settings by Entity Instance
 12. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                 ;
+------------------------------------+-----------------------------------------+
; Analysis & Synthesis Status        ; Successful - Sun Jun 10 19:34:18 2012   ;
; Quartus II Version                 ; 7.2 Build 151 09/26/2007 SJ Web Edition ;
; Revision Name                      ; test3                                   ;
; Top-level Entity Name              ; test3                                   ;
; Family                             ; Cyclone II                              ;
; Total logic elements               ; 3,469                                   ;
;     Total combinational functions  ; 3,469                                   ;
;     Dedicated logic registers      ; 0                                       ;
; Total registers                    ; 0                                       ;
; Total pins                         ; 44                                      ;
; Total virtual pins                 ; 0                                       ;
; Total memory bits                  ; 0                                       ;
; Embedded Multiplier 9-bit elements ; 16                                      ;
; Total PLLs                         ; 0                                       ;
+------------------------------------+-----------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                            ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                         ; Setting            ; Default Value      ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                         ; EP2C35F672C6       ;                    ;
; Top-level entity name                                                          ; test3              ; test3              ;
; Family name                                                                    ; Cyclone II         ; Stratix II         ;
; Use Generated Physical Constraints File                                        ; Off                ;                    ;
; Use smart compilation                                                          ; Off                ; Off                ;
; Maximum processors allowed for parallel compilation                            ; 1                  ; 1                  ;
; Restructure Multiplexers                                                       ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                            ; Off                ; Off                ;
; Preserve fewer node names                                                      ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                      ; Off                ; Off                ;
; Verilog Version                                                                ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                                   ; VHDL93             ; VHDL93             ;
; State Machine Processing                                                       ; Auto               ; Auto               ;
; Safe State Machine                                                             ; Off                ; Off                ;
; Extract Verilog State Machines                                                 ; On                 ; On                 ;
; Extract VHDL State Machines                                                    ; On                 ; On                 ;
; Ignore Verilog initial constructs                                              ; Off                ; Off                ;
; Add Pass-Through Logic to Inferred RAMs                                        ; On                 ; On                 ;
; Parallel Synthesis                                                             ; Off                ; Off                ;
; DSP Block Balancing                                                            ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                             ; On                 ; On                 ;
; Power-Up Don't Care                                                            ; On                 ; On                 ;
; Remove Redundant Logic Cells                                                   ; Off                ; Off                ;
; Remove Duplicate Registers                                                     ; On                 ; On                 ;
; Ignore CARRY Buffers                                                           ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                         ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                          ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore LCELL Buffers                                                           ; Off                ; Off                ;
; Ignore SOFT Buffers                                                            ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                                 ; Off                ; Off                ;
; Optimization Technique -- Cyclone II/Cyclone III                               ; Balanced           ; Balanced           ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II/Cyclone III ; 70                 ; 70                 ;
; Auto Carry Chains                                                              ; On                 ; On                 ;
; Auto Open-Drain Pins                                                           ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                          ; Off                ; Off                ;
; Perform gate-level register retiming                                           ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax                         ; On                 ; On                 ;
; Auto ROM Replacement                                                           ; On                 ; On                 ;
; Auto RAM Replacement                                                           ; On                 ; On                 ;
; Auto Shift Register Replacement                                                ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                                  ; On                 ; On                 ;
; Allow Synchronous Control Signals                                              ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                         ; Off                ; Off                ;
; Auto RAM to Logic Cell Conversion                                              ; Off                ; Off                ;
; Auto Resource Sharing                                                          ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                             ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                             ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                                  ; Off                ; Off                ;
; Ignore translate_off and synthesis_off directives                              ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                             ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                             ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                               ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                                   ; Normal compilation ; Normal compilation ;
; HDL message level                                                              ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                                ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                       ; 100                ; 100                ;
; Clock MUX Protection                                                           ; On                 ; On                 ;
; Block Design Naming                                                            ; Auto               ; Auto               ;
+--------------------------------------------------------------------------------+--------------------+--------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                               ;
+----------------------------------+-----------------+------------------------------+----------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                                     ;
+----------------------------------+-----------------+------------------------------+----------------------------------------------------------------------------------+
; div.vhd                          ; yes             ; User VHDL File               ; D:/Studium/6.Semester/Programmierbare Logik/APL/test3/div.vhd                    ;
; mul.vhd                          ; yes             ; User VHDL File               ; D:/Studium/6.Semester/Programmierbare Logik/APL/test3/mul.vhd                    ;
; test3.vhd                        ; yes             ; User VHDL File               ; D:/Studium/6.Semester/Programmierbare Logik/APL/test3/test3.vhd                  ;
; lpm_mult.tdf                     ; yes             ; Megafunction                 ; d:/altera/72/quartus/libraries/megafunctions/lpm_mult.tdf                        ;
; aglobal72.inc                    ; yes             ; Megafunction                 ; d:/altera/72/quartus/libraries/megafunctions/aglobal72.inc                       ;
; lpm_add_sub.inc                  ; yes             ; Megafunction                 ; d:/altera/72/quartus/libraries/megafunctions/lpm_add_sub.inc                     ;
; multcore.inc                     ; yes             ; Megafunction                 ; d:/altera/72/quartus/libraries/megafunctions/multcore.inc                        ;
; bypassff.inc                     ; yes             ; Megafunction                 ; d:/altera/72/quartus/libraries/megafunctions/bypassff.inc                        ;
; altshift.inc                     ; yes             ; Megafunction                 ; d:/altera/72/quartus/libraries/megafunctions/altshift.inc                        ;
; db/mult_snq.tdf                  ; yes             ; Auto-Generated Megafunction  ; D:/Studium/6.Semester/Programmierbare Logik/APL/test3/db/mult_snq.tdf            ;
; lpm_divide.tdf                   ; yes             ; Megafunction                 ; d:/altera/72/quartus/libraries/megafunctions/lpm_divide.tdf                      ;
; abs_divider.inc                  ; yes             ; Megafunction                 ; d:/altera/72/quartus/libraries/megafunctions/abs_divider.inc                     ;
; sign_div_unsign.inc              ; yes             ; Megafunction                 ; d:/altera/72/quartus/libraries/megafunctions/sign_div_unsign.inc                 ;
; db/lpm_divide_v3r.tdf            ; yes             ; Auto-Generated Megafunction  ; D:/Studium/6.Semester/Programmierbare Logik/APL/test3/db/lpm_divide_v3r.tdf      ;
; db/sign_div_unsign_k9h.tdf       ; yes             ; Auto-Generated Megafunction  ; D:/Studium/6.Semester/Programmierbare Logik/APL/test3/db/sign_div_unsign_k9h.tdf ;
; db/alt_u_div_l6f.tdf             ; yes             ; Auto-Generated Megafunction  ; D:/Studium/6.Semester/Programmierbare Logik/APL/test3/db/alt_u_div_l6f.tdf       ;
; db/add_sub_lkc.tdf               ; yes             ; Auto-Generated Megafunction  ; D:/Studium/6.Semester/Programmierbare Logik/APL/test3/db/add_sub_lkc.tdf         ;
; db/add_sub_mkc.tdf               ; yes             ; Auto-Generated Megafunction  ; D:/Studium/6.Semester/Programmierbare Logik/APL/test3/db/add_sub_mkc.tdf         ;
+----------------------------------+-----------------+------------------------------+----------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                                                                          ;
+---------------------------------------------+------------------------------------------------------------------------+
; Resource                                    ; Usage                                                                  ;
+---------------------------------------------+------------------------------------------------------------------------+
; Estimated Total logic elements              ; 3,469                                                                  ;
;                                             ;                                                                        ;
; Total combinational functions               ; 3469                                                                   ;
; Logic element usage by number of LUT inputs ;                                                                        ;
;     -- 4 input functions                    ; 71                                                                     ;
;     -- 3 input functions                    ; 1697                                                                   ;
;     -- <=2 input functions                  ; 1701                                                                   ;
;                                             ;                                                                        ;
; Logic elements by mode                      ;                                                                        ;
;     -- normal mode                          ; 1644                                                                   ;
;     -- arithmetic mode                      ; 1825                                                                   ;
;                                             ;                                                                        ;
; Total registers                             ; 0                                                                      ;
;     -- Dedicated logic registers            ; 0                                                                      ;
;     -- I/O registers                        ; 0                                                                      ;
;                                             ;                                                                        ;
; I/O pins                                    ; 44                                                                     ;
; Embedded Multiplier 9-bit elements          ; 16                                                                     ;
; Maximum fan-out node                        ; mul:mul_1|lpm_mult:lpm_mult_component|mult_snq:auto_generated|op_7~258 ;
; Maximum fan-out                             ; 167                                                                    ;
; Total fan-out                               ; 8744                                                                   ;
; Average fan-out                             ; 2.48                                                                   ;
+---------------------------------------------+------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                     ;
+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node                ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                              ; Library Name ;
+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------+--------------+
; |test3                                    ; 3469 (1)          ; 0 (0)        ; 0           ; 16           ; 0       ; 8         ; 44   ; 0            ; |test3                                                                                                                           ; work         ;
;    |div:div_1|                            ; 3247 (0)          ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test3|div:div_1                                                                                                                 ; work         ;
;       |lpm_divide:lpm_divide_component|   ; 3247 (0)          ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test3|div:div_1|lpm_divide:lpm_divide_component                                                                                 ; work         ;
;          |lpm_divide_v3r:auto_generated|  ; 3247 (0)          ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test3|div:div_1|lpm_divide:lpm_divide_component|lpm_divide_v3r:auto_generated                                                   ; work         ;
;             |sign_div_unsign_k9h:divider| ; 3247 (63)         ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test3|div:div_1|lpm_divide:lpm_divide_component|lpm_divide_v3r:auto_generated|sign_div_unsign_k9h:divider                       ; work         ;
;                |alt_u_div_l6f:divider|    ; 3184 (3184)       ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test3|div:div_1|lpm_divide:lpm_divide_component|lpm_divide_v3r:auto_generated|sign_div_unsign_k9h:divider|alt_u_div_l6f:divider ; work         ;
;    |mul:mul_1|                            ; 221 (0)           ; 0 (0)        ; 0           ; 16           ; 0       ; 8         ; 0    ; 0            ; |test3|mul:mul_1                                                                                                                 ; work         ;
;       |lpm_mult:lpm_mult_component|       ; 221 (0)           ; 0 (0)        ; 0           ; 16           ; 0       ; 8         ; 0    ; 0            ; |test3|mul:mul_1|lpm_mult:lpm_mult_component                                                                                     ; work         ;
;          |mult_snq:auto_generated|        ; 221 (221)         ; 0 (0)        ; 0           ; 16           ; 0       ; 8         ; 0    ; 0            ; |test3|mul:mul_1|lpm_mult:lpm_mult_component|mult_snq:auto_generated                                                             ; work         ;
+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+-----------------------------------------------------+
; Analysis & Synthesis DSP Block Usage Summary        ;
+---------------------------------------+-------------+
; Statistic                             ; Number Used ;
+---------------------------------------+-------------+
; Simple Multipliers (9-bit)            ; 0           ;
; Simple Multipliers (18-bit)           ; 8           ;
; Embedded Multiplier Blocks            ; --          ;
; Embedded Multiplier 9-bit elements    ; 16          ;
; Signed Embedded Multipliers           ; 1           ;
; Unsigned Embedded Multipliers         ; 3           ;
; Mixed Sign Embedded Multipliers       ; 4           ;
; Variable Sign Embedded Multipliers    ; 0           ;
; Dedicated Input Shift Register Chains ; 0           ;
+---------------------------------------+-------------+
Note: number of Embedded Multiplier Blocks used is only available after a successful fit.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: mul:mul_1|lpm_mult:lpm_mult_component ;
+------------------------------------------------+------------+----------------------+
; Parameter Name                                 ; Value      ; Type                 ;
+------------------------------------------------+------------+----------------------+
; AUTO_CARRY_CHAINS                              ; ON         ; AUTO_CARRY           ;
; IGNORE_CARRY_BUFFERS                           ; OFF        ; IGNORE_CARRY         ;
; AUTO_CASCADE_CHAINS                            ; ON         ; AUTO_CASCADE         ;
; IGNORE_CASCADE_BUFFERS                         ; OFF        ; IGNORE_CASCADE       ;
; LPM_WIDTHA                                     ; 64         ; Signed Integer       ;
; LPM_WIDTHB                                     ; 24         ; Signed Integer       ;
; LPM_WIDTHP                                     ; 88         ; Signed Integer       ;
; LPM_WIDTHR                                     ; 0          ; Untyped              ;
; LPM_WIDTHS                                     ; 1          ; Untyped              ;
; LPM_REPRESENTATION                             ; SIGNED     ; Untyped              ;
; LPM_PIPELINE                                   ; 0          ; Untyped              ;
; LATENCY                                        ; 0          ; Untyped              ;
; INPUT_A_IS_CONSTANT                            ; NO         ; Untyped              ;
; INPUT_B_IS_CONSTANT                            ; NO         ; Untyped              ;
; USE_EAB                                        ; OFF        ; Untyped              ;
; MAXIMIZE_SPEED                                 ; 5          ; Untyped              ;
; DEVICE_FAMILY                                  ; Cyclone II ; Untyped              ;
; CARRY_CHAIN                                    ; MANUAL     ; Untyped              ;
; APEX20K_TECHNOLOGY_MAPPER                      ; LUT        ; TECH_MAPPER_APEX20K  ;
; DEDICATED_MULTIPLIER_CIRCUITRY                 ; YES        ; Untyped              ;
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0          ; Untyped              ;
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0          ; Untyped              ;
; CBXI_PARAMETER                                 ; mult_snq   ; Untyped              ;
; INPUT_A_FIXED_VALUE                            ; Bx         ; Untyped              ;
; INPUT_B_FIXED_VALUE                            ; Bx         ; Untyped              ;
; USE_AHDL_IMPLEMENTATION                        ; OFF        ; Untyped              ;
+------------------------------------------------+------------+----------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: div:div_1|lpm_divide:lpm_divide_component ;
+------------------------+----------------+----------------------------------------------+
; Parameter Name         ; Value          ; Type                                         ;
+------------------------+----------------+----------------------------------------------+
; LPM_WIDTHN             ; 88             ; Signed Integer                               ;
; LPM_WIDTHD             ; 64             ; Signed Integer                               ;
; LPM_NREPRESENTATION    ; SIGNED         ; Untyped                                      ;
; LPM_DREPRESENTATION    ; SIGNED         ; Untyped                                      ;
; LPM_PIPELINE           ; 0              ; Untyped                                      ;
; LPM_REMAINDERPOSITIVE  ; TRUE           ; Untyped                                      ;
; MAXIMIZE_SPEED         ; 6              ; Untyped                                      ;
; CBXI_PARAMETER         ; lpm_divide_v3r ; Untyped                                      ;
; CARRY_CHAIN            ; MANUAL         ; Untyped                                      ;
; OPTIMIZE_FOR_SPEED     ; 5              ; Untyped                                      ;
; AUTO_CARRY_CHAINS      ; ON             ; AUTO_CARRY                                   ;
; IGNORE_CARRY_BUFFERS   ; OFF            ; IGNORE_CARRY                                 ;
; AUTO_CASCADE_CHAINS    ; ON             ; AUTO_CASCADE                                 ;
; IGNORE_CASCADE_BUFFERS ; OFF            ; IGNORE_CASCADE                               ;
+------------------------+----------------+----------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------+
; lpm_mult Parameter Settings by Entity Instance                                ;
+---------------------------------------+---------------------------------------+
; Name                                  ; Value                                 ;
+---------------------------------------+---------------------------------------+
; Number of entity instances            ; 1                                     ;
; Entity Instance                       ; mul:mul_1|lpm_mult:lpm_mult_component ;
;     -- LPM_WIDTHA                     ; 64                                    ;
;     -- LPM_WIDTHB                     ; 24                                    ;
;     -- LPM_WIDTHP                     ; 88                                    ;
;     -- LPM_REPRESENTATION             ; SIGNED                                ;
;     -- INPUT_A_IS_CONSTANT            ; NO                                    ;
;     -- INPUT_B_IS_CONSTANT            ; NO                                    ;
;     -- USE_EAB                        ; OFF                                   ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; YES                                   ;
;     -- INPUT_A_FIXED_VALUE            ; Bx                                    ;
;     -- INPUT_B_FIXED_VALUE            ; Bx                                    ;
+---------------------------------------+---------------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Web Edition
    Info: Processing started: Sun Jun 10 19:34:01 2012
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off test3 -c test3
Info: Found 2 design units, including 1 entities, in source file div.vhd
    Info: Found design unit 1: div-SYN
    Info: Found entity 1: div
Info: Found 2 design units, including 1 entities, in source file mul.vhd
    Info: Found design unit 1: mul-SYN
    Info: Found entity 1: mul
Info: Found 2 design units, including 1 entities, in source file test3.vhd
    Info: Found design unit 1: test3-behavior
    Info: Found entity 1: test3
Info: Elaborating entity "test3" for the top level hierarchy
Warning (10540): VHDL Signal Declaration warning at test3.vhd(23): used explicit default value for signal "a" because signal was never assigned a value
Warning (10540): VHDL Signal Declaration warning at test3.vhd(24): used explicit default value for signal "b" because signal was never assigned a value
Warning (10540): VHDL Signal Declaration warning at test3.vhd(25): used explicit default value for signal "d" because signal was never assigned a value
Warning (10036): Verilog HDL or VHDL warning at test3.vhd(27): object "s" assigned a value but never read
Info: Elaborating entity "mul" for hierarchy "mul:mul_1"
Info: Found 1 design units, including 1 entities, in source file ../../../../../altera/72/quartus/libraries/megafunctions/lpm_mult.tdf
    Info: Found entity 1: lpm_mult
Info: Elaborating entity "lpm_mult" for hierarchy "mul:mul_1|lpm_mult:lpm_mult_component"
Info: Elaborated megafunction instantiation "mul:mul_1|lpm_mult:lpm_mult_component"
Info: Found 1 design units, including 1 entities, in source file db/mult_snq.tdf
    Info: Found entity 1: mult_snq
Info: Elaborating entity "mult_snq" for hierarchy "mul:mul_1|lpm_mult:lpm_mult_component|mult_snq:auto_generated"
Info: Elaborating entity "div" for hierarchy "div:div_1"
Info: Found 1 design units, including 1 entities, in source file ../../../../../altera/72/quartus/libraries/megafunctions/lpm_divide.tdf
    Info: Found entity 1: lpm_divide
Info: Elaborating entity "lpm_divide" for hierarchy "div:div_1|lpm_divide:lpm_divide_component"
Info: Elaborated megafunction instantiation "div:div_1|lpm_divide:lpm_divide_component"
Warning: Assertion warning: MGL_INTERNAL_WARNING: (Simulating lpm_divide|sign_div_unsign inst divider|alt_u_div inst divider with the provided stimulus caused the simulator to reach the maximum iteration limit.) The RTL netlist and the provided stimulus create an endless loop in internal simulation. It cannot be used to initialize the generators based on the stimulus.  Avoid using loops in the RTL netlist or choose an appropriate stimulus.
Warning: Assertion warning: MGL_INTERNAL_WARNING: (Simulating lpm_divide|sign_div_unsign inst divider|alt_u_div inst divider with the provided stimulus caused the simulator to reach the maximum iteration limit.) The RTL netlist and the provided stimulus create an endless loop in internal simulation. It cannot be used to initialize the generators based on the stimulus.  Avoid using loops in the RTL netlist or choose an appropriate stimulus.
Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_v3r.tdf
    Info: Found entity 1: lpm_divide_v3r
Info: Elaborating entity "lpm_divide_v3r" for hierarchy "div:div_1|lpm_divide:lpm_divide_component|lpm_divide_v3r:auto_generated"
Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_k9h.tdf
    Info: Found entity 1: sign_div_unsign_k9h
Info: Elaborating entity "sign_div_unsign_k9h" for hierarchy "div:div_1|lpm_divide:lpm_divide_component|lpm_divide_v3r:auto_generated|sign_div_unsign_k9h:divider"
Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_l6f.tdf
    Info: Found entity 1: alt_u_div_l6f
Info: Elaborating entity "alt_u_div_l6f" for hierarchy "div:div_1|lpm_divide:lpm_divide_component|lpm_divide_v3r:auto_generated|sign_div_unsign_k9h:divider|alt_u_div_l6f:divider"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_lkc.tdf
    Info: Found entity 1: add_sub_lkc
Info: Elaborating entity "add_sub_lkc" for hierarchy "div:div_1|lpm_divide:lpm_divide_component|lpm_divide_v3r:auto_generated|sign_div_unsign_k9h:divider|alt_u_div_l6f:divider|add_sub_lkc:add_sub_0"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_mkc.tdf
    Info: Found entity 1: add_sub_mkc
Info: Elaborating entity "add_sub_mkc" for hierarchy "div:div_1|lpm_divide:lpm_divide_component|lpm_divide_v3r:auto_generated|sign_div_unsign_k9h:divider|alt_u_div_l6f:divider|add_sub_mkc:add_sub_1"
Warning: Design contains 18 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "SW[0]"
    Warning (15610): No output dependent on input pin "SW[1]"
    Warning (15610): No output dependent on input pin "SW[2]"
    Warning (15610): No output dependent on input pin "SW[3]"
    Warning (15610): No output dependent on input pin "SW[4]"
    Warning (15610): No output dependent on input pin "SW[5]"
    Warning (15610): No output dependent on input pin "SW[6]"
    Warning (15610): No output dependent on input pin "SW[7]"
    Warning (15610): No output dependent on input pin "SW[8]"
    Warning (15610): No output dependent on input pin "SW[9]"
    Warning (15610): No output dependent on input pin "SW[10]"
    Warning (15610): No output dependent on input pin "SW[11]"
    Warning (15610): No output dependent on input pin "SW[12]"
    Warning (15610): No output dependent on input pin "SW[13]"
    Warning (15610): No output dependent on input pin "SW[14]"
    Warning (15610): No output dependent on input pin "SW[15]"
    Warning (15610): No output dependent on input pin "SW[16]"
    Warning (15610): No output dependent on input pin "SW[17]"
Info: Implemented 3529 device resources after synthesis - the final resource count might be different
    Info: Implemented 18 input pins
    Info: Implemented 26 output pins
    Info: Implemented 3469 logic cells
    Info: Implemented 16 DSP elements
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 25 warnings
    Info: Allocated 335 megabytes of memory during processing
    Info: Processing ended: Sun Jun 10 19:34:18 2012
    Info: Elapsed time: 00:00:17


