Classic Timing Analyzer report for test2
Sat Jun 09 14:17:13 2012
Quartus II Version 7.2 Build 151 09/26/2007 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. tpd
  5. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                     ;
+------------------------------+-------+---------------+-------------+-------+---------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From  ; To      ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+-------+---------+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 10.437 ns   ; SW[0] ; LEDR[6] ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;       ;         ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+-------+---------+------------+----------+--------------+


+---------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                      ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                         ; Setting            ; From ; To ; Entity Name ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                    ; EP2C35F672C6       ;      ;    ;             ;
; Timing Models                                                  ; Final              ;      ;    ;             ;
; Default hold multicycle                                        ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                      ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                         ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                 ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                               ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                          ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                        ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                               ; Off                ;      ;    ;             ;
; Enable Clock Latency                                           ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node          ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                          ; 10                 ;      ;    ;             ;
; Number of paths to report                                      ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                   ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                         ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                     ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                   ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis ; Off                ;      ;    ;             ;
+----------------------------------------------------------------+--------------------+------+----+-------------+


+----------------------------------------------------------------+
; tpd                                                            ;
+-------+-------------------+-----------------+-------+----------+
; Slack ; Required P2P Time ; Actual P2P Time ; From  ; To       ;
+-------+-------------------+-----------------+-------+----------+
; N/A   ; None              ; 10.437 ns       ; SW[0] ; LEDR[6]  ;
; N/A   ; None              ; 10.434 ns       ; SW[0] ; LEDR[7]  ;
; N/A   ; None              ; 10.370 ns       ; SW[1] ; LEDR[7]  ;
; N/A   ; None              ; 9.900 ns        ; SW[7] ; LEDR[14] ;
; N/A   ; None              ; 9.893 ns        ; SW[7] ; LEDR[15] ;
; N/A   ; None              ; 9.649 ns        ; SW[0] ; LEDR[14] ;
; N/A   ; None              ; 9.642 ns        ; SW[0] ; LEDR[15] ;
; N/A   ; None              ; 9.585 ns        ; SW[1] ; LEDR[14] ;
; N/A   ; None              ; 9.578 ns        ; SW[1] ; LEDR[15] ;
; N/A   ; None              ; 9.551 ns        ; SW[7] ; LEDR[13] ;
; N/A   ; None              ; 9.342 ns        ; SW[0] ; LEDR[10] ;
; N/A   ; None              ; 9.327 ns        ; SW[2] ; LEDR[14] ;
; N/A   ; None              ; 9.320 ns        ; SW[2] ; LEDR[15] ;
; N/A   ; None              ; 9.300 ns        ; SW[0] ; LEDR[13] ;
; N/A   ; None              ; 9.289 ns        ; SW[0] ; LEDR[12] ;
; N/A   ; None              ; 9.284 ns        ; SW[0] ; LEDR[9]  ;
; N/A   ; None              ; 9.278 ns        ; SW[1] ; LEDR[10] ;
; N/A   ; None              ; 9.278 ns        ; SW[0] ; LEDR[11] ;
; N/A   ; None              ; 9.274 ns        ; SW[0] ; LEDR[8]  ;
; N/A   ; None              ; 9.236 ns        ; SW[1] ; LEDR[13] ;
; N/A   ; None              ; 9.225 ns        ; SW[1] ; LEDR[12] ;
; N/A   ; None              ; 9.220 ns        ; SW[1] ; LEDR[9]  ;
; N/A   ; None              ; 9.214 ns        ; SW[1] ; LEDR[11] ;
; N/A   ; None              ; 9.210 ns        ; SW[1] ; LEDR[8]  ;
; N/A   ; None              ; 9.020 ns        ; SW[2] ; LEDR[10] ;
; N/A   ; None              ; 8.978 ns        ; SW[2] ; LEDR[13] ;
; N/A   ; None              ; 8.967 ns        ; SW[2] ; LEDR[12] ;
; N/A   ; None              ; 8.962 ns        ; SW[2] ; LEDR[9]  ;
; N/A   ; None              ; 8.956 ns        ; SW[2] ; LEDR[11] ;
; N/A   ; None              ; 8.952 ns        ; SW[2] ; LEDR[8]  ;
; N/A   ; None              ; 8.499 ns        ; SW[3] ; LEDR[14] ;
; N/A   ; None              ; 8.492 ns        ; SW[3] ; LEDR[15] ;
; N/A   ; None              ; 8.453 ns        ; SW[4] ; LEDR[14] ;
; N/A   ; None              ; 8.446 ns        ; SW[4] ; LEDR[15] ;
; N/A   ; None              ; 8.441 ns        ; SW[6] ; LEDR[14] ;
; N/A   ; None              ; 8.435 ns        ; SW[5] ; LEDR[14] ;
; N/A   ; None              ; 8.434 ns        ; SW[6] ; LEDR[15] ;
; N/A   ; None              ; 8.428 ns        ; SW[5] ; LEDR[15] ;
; N/A   ; None              ; 8.192 ns        ; SW[3] ; LEDR[10] ;
; N/A   ; None              ; 8.150 ns        ; SW[3] ; LEDR[13] ;
; N/A   ; None              ; 8.146 ns        ; SW[4] ; LEDR[10] ;
; N/A   ; None              ; 8.139 ns        ; SW[3] ; LEDR[12] ;
; N/A   ; None              ; 8.134 ns        ; SW[3] ; LEDR[9]  ;
; N/A   ; None              ; 8.128 ns        ; SW[3] ; LEDR[11] ;
; N/A   ; None              ; 8.104 ns        ; SW[4] ; LEDR[13] ;
; N/A   ; None              ; 8.093 ns        ; SW[4] ; LEDR[12] ;
; N/A   ; None              ; 8.092 ns        ; SW[6] ; LEDR[13] ;
; N/A   ; None              ; 8.086 ns        ; SW[5] ; LEDR[13] ;
; N/A   ; None              ; 8.082 ns        ; SW[4] ; LEDR[11] ;
; N/A   ; None              ; 8.081 ns        ; SW[6] ; LEDR[12] ;
; N/A   ; None              ; 8.075 ns        ; SW[5] ; LEDR[12] ;
; N/A   ; None              ; 8.064 ns        ; SW[5] ; LEDR[11] ;
+-------+-------------------+-----------------+-------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Web Edition
    Info: Processing started: Sat Jun 09 14:17:13 2012
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off test2 -c test2 --timing_analysis_only
Info: Longest tpd from source pin "SW[0]" to destination pin "LEDR[6]" is 10.437 ns
    Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N25; Fanout = 10; PIN Node = 'SW[0]'
    Info: 2: + IC(2.276 ns) + CELL(2.246 ns) = 5.521 ns; Loc. = DSPMULT_X39_Y1_N0; Fanout = 1; COMB Node = 'lpm_mult0:inst|lpm_mult:lpm_mult_component|mult_jkq:auto_generated|mac_mult1~DATAOUT6'
    Info: 3: + IC(0.000 ns) + CELL(0.224 ns) = 5.745 ns; Loc. = DSPOUT_X39_Y1_N2; Fanout = 1; COMB Node = 'lpm_mult0:inst|lpm_mult:lpm_mult_component|mult_jkq:auto_generated|result[6]'
    Info: 4: + IC(1.894 ns) + CELL(2.798 ns) = 10.437 ns; Loc. = PIN_AD21; Fanout = 0; PIN Node = 'LEDR[6]'
    Info: Total cell delay = 6.267 ns ( 60.05 % )
    Info: Total interconnect delay = 4.170 ns ( 39.95 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Allocated 167 megabytes of memory during processing
    Info: Processing ended: Sat Jun 09 14:17:14 2012
    Info: Elapsed time: 00:00:01


