<html><head><meta name="color-scheme" content="light dark"></head><body><pre style="word-wrap: break-word; white-space: pre-wrap;">Analysis &amp; Synthesis report for test2
Sat Jun 09 14:16:58 2012
Quartus II Version 7.2 Build 151 09/26/2007 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis &amp; Synthesis Summary
  3. Analysis &amp; Synthesis Settings
  4. Analysis &amp; Synthesis Source Files Read
  5. Analysis &amp; Synthesis Resource Usage Summary
  6. Analysis &amp; Synthesis Resource Utilization by Entity
  7. Analysis &amp; Synthesis DSP Block Usage Summary
  8. Registers Removed During Synthesis
  9. General Register Statistics
 10. Parameter Settings for User Entity Instance: test_constant:inst1
 11. Parameter Settings for User Entity Instance: lpm_mult0:inst|lpm_mult:lpm_mult_component
 12. lpm_mult Parameter Settings by Entity Instance
 13. Analysis &amp; Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------+
; Analysis &amp; Synthesis Summary                                                 ;
+------------------------------------+-----------------------------------------+
; Analysis &amp; Synthesis Status        ; Successful - Sat Jun 09 14:16:58 2012   ;
; Quartus II Version                 ; 7.2 Build 151 09/26/2007 SJ Web Edition ;
; Revision Name                      ; test2                                   ;
; Top-level Entity Name              ; test2                                   ;
; Family                             ; Cyclone II                              ;
; Total logic elements               ; 0                                       ;
;     Total combinational functions  ; 0                                       ;
;     Dedicated logic registers      ; 0                                       ;
; Total registers                    ; 0                                       ;
; Total pins                         ; 33                                      ;
; Total virtual pins                 ; 0                                       ;
; Total memory bits                  ; 0                                       ;
; Embedded Multiplier 9-bit elements ; 1                                       ;
; Total PLLs                         ; 0                                       ;
+------------------------------------+-----------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------+
; Analysis &amp; Synthesis Settings                                                                                            ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                         ; Setting            ; Default Value      ;
+--------------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                         ; EP2C35F672C6       ;                    ;
; Top-level entity name                                                          ; test2              ; test2              ;
; Family name                                                                    ; Cyclone II         ; Stratix II         ;
; Use Generated Physical Constraints File                                        ; Off                ;                    ;
; Use smart compilation                                                          ; Off                ; Off                ;
; Maximum processors allowed for parallel compilation                            ; 1                  ; 1                  ;
; Restructure Multiplexers                                                       ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                            ; Off                ; Off                ;
; Preserve fewer node names                                                      ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                      ; Off                ; Off                ;
; Verilog Version                                                                ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                                   ; VHDL93             ; VHDL93             ;
; State Machine Processing                                                       ; Auto               ; Auto               ;
; Safe State Machine                                                             ; Off                ; Off                ;
; Extract Verilog State Machines                                                 ; On                 ; On                 ;
; Extract VHDL State Machines                                                    ; On                 ; On                 ;
; Ignore Verilog initial constructs                                              ; Off                ; Off                ;
; Add Pass-Through Logic to Inferred RAMs                                        ; On                 ; On                 ;
; Parallel Synthesis                                                             ; Off                ; Off                ;
; DSP Block Balancing                                                            ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                             ; On                 ; On                 ;
; Power-Up Don't Care                                                            ; On                 ; On                 ;
; Remove Redundant Logic Cells                                                   ; Off                ; Off                ;
; Remove Duplicate Registers                                                     ; On                 ; On                 ;
; Ignore CARRY Buffers                                                           ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                         ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                          ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore LCELL Buffers                                                           ; Off                ; Off                ;
; Ignore SOFT Buffers                                                            ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                                 ; Off                ; Off                ;
; Optimization Technique -- Cyclone II/Cyclone III                               ; Balanced           ; Balanced           ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II/Cyclone III ; 70                 ; 70                 ;
; Auto Carry Chains                                                              ; On                 ; On                 ;
; Auto Open-Drain Pins                                                           ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                          ; Off                ; Off                ;
; Perform gate-level register retiming                                           ; Off                ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax                         ; On                 ; On                 ;
; Auto ROM Replacement                                                           ; On                 ; On                 ;
; Auto RAM Replacement                                                           ; On                 ; On                 ;
; Auto Shift Register Replacement                                                ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                                  ; On                 ; On                 ;
; Allow Synchronous Control Signals                                              ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                         ; Off                ; Off                ;
; Auto RAM to Logic Cell Conversion                                              ; Off                ; Off                ;
; Auto Resource Sharing                                                          ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                             ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                             ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                                  ; Off                ; Off                ;
; Ignore translate_off and synthesis_off directives                              ; Off                ; Off                ;
; Show Parameter Settings Tables in Synthesis Report                             ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                             ; Off                ; Off                ;
; Retiming Meta-Stability Register Sequence Length                               ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                                   ; Normal compilation ; Normal compilation ;
; HDL message level                                                              ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                                ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                       ; 100                ; 100                ;
; Clock MUX Protection                                                           ; On                 ; On                 ;
; Block Design Naming                                                            ; Auto               ; Auto               ;
+--------------------------------------------------------------------------------+--------------------+--------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis &amp; Synthesis Source Files Read                                                                                                                         ;
+----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                         ;
+----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------------+
; test2.bdf                        ; yes             ; User Block Diagram/Schematic File  ; D:/juergen/Projekte/VHDL/test2/test2.bdf                             ;
; test_constant.vhd                ; yes             ; User VHDL File                     ; D:/juergen/Projekte/VHDL/test2/test_constant.vhd                     ;
; lpm_mult0.vhd                    ; yes             ; Other                              ; D:/juergen/Projekte/VHDL/test2/lpm_mult0.vhd                         ;
; lpm_mult.tdf                     ; yes             ; Megafunction                       ; d:/juergen/altera/72/quartus/libraries/megafunctions/lpm_mult.tdf    ;
; aglobal72.inc                    ; yes             ; Megafunction                       ; d:/juergen/altera/72/quartus/libraries/megafunctions/aglobal72.inc   ;
; lpm_add_sub.inc                  ; yes             ; Megafunction                       ; d:/juergen/altera/72/quartus/libraries/megafunctions/lpm_add_sub.inc ;
; multcore.inc                     ; yes             ; Megafunction                       ; d:/juergen/altera/72/quartus/libraries/megafunctions/multcore.inc    ;
; bypassff.inc                     ; yes             ; Megafunction                       ; d:/juergen/altera/72/quartus/libraries/megafunctions/bypassff.inc    ;
; altshift.inc                     ; yes             ; Megafunction                       ; d:/juergen/altera/72/quartus/libraries/megafunctions/altshift.inc    ;
; db/mult_jkq.tdf                  ; yes             ; Auto-Generated Megafunction        ; D:/juergen/Projekte/VHDL/test2/db/mult_jkq.tdf                       ;
+----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Analysis &amp; Synthesis Resource Usage Summary                                                                                ;
+---------------------------------------------+------------------------------------------------------------------------------+
; Resource                                    ; Usage                                                                        ;
+---------------------------------------------+------------------------------------------------------------------------------+
;                                             ;                                                                              ;
; Total combinational functions               ; 0                                                                            ;
; Logic element usage by number of LUT inputs ;                                                                              ;
;     -- 4 input functions                    ; 0                                                                            ;
;     -- 3 input functions                    ; 0                                                                            ;
;     -- &lt;=2 input functions                  ; 0                                                                            ;
;                                             ;                                                                              ;
; Logic elements by mode                      ;                                                                              ;
;     -- normal mode                          ; 0                                                                            ;
;     -- arithmetic mode                      ; 0                                                                            ;
;                                             ;                                                                              ;
; Total registers                             ; 0                                                                            ;
;     -- Dedicated logic registers            ; 0                                                                            ;
;     -- I/O registers                        ; 0                                                                            ;
;                                             ;                                                                              ;
; I/O pins                                    ; 33                                                                           ;
; Embedded Multiplier 9-bit elements          ; 1                                                                            ;
; Maximum fan-out node                        ; lpm_mult0:inst|lpm_mult:lpm_mult_component|mult_jkq:auto_generated|result[0] ;
; Maximum fan-out                             ; 16                                                                           ;
; Total fan-out                               ; 25                                                                           ;
; Average fan-out                             ; 0.71                                                                         ;
+---------------------------------------------+------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis &amp; Synthesis Resource Utilization by Entity                                                                                                                                                                                        ;
+-------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node          ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                       ; Library Name ;
+-------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------------+--------------+
; |test2                              ; 0 (0)             ; 0 (0)        ; 0           ; 1            ; 1       ; 0         ; 33   ; 0            ; |test2                                                                    ; work         ;
;    |lpm_mult0:inst|                 ; 0 (0)             ; 0 (0)        ; 0           ; 1            ; 1       ; 0         ; 0    ; 0            ; |test2|lpm_mult0:inst                                                     ; work         ;
;       |lpm_mult:lpm_mult_component| ; 0 (0)             ; 0 (0)        ; 0           ; 1            ; 1       ; 0         ; 0    ; 0            ; |test2|lpm_mult0:inst|lpm_mult:lpm_mult_component                         ; work         ;
;          |mult_jkq:auto_generated|  ; 0 (0)             ; 0 (0)        ; 0           ; 1            ; 1       ; 0         ; 0    ; 0            ; |test2|lpm_mult0:inst|lpm_mult:lpm_mult_component|mult_jkq:auto_generated ; work         ;
+-------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+-----------------------------------------------------+
; Analysis &amp; Synthesis DSP Block Usage Summary        ;
+---------------------------------------+-------------+
; Statistic                             ; Number Used ;
+---------------------------------------+-------------+
; Simple Multipliers (9-bit)            ; 1           ;
; Simple Multipliers (18-bit)           ; 0           ;
; Embedded Multiplier Blocks            ; --          ;
; Embedded Multiplier 9-bit elements    ; 1           ;
; Signed Embedded Multipliers           ; 1           ;
; Unsigned Embedded Multipliers         ; 0           ;
; Mixed Sign Embedded Multipliers       ; 0           ;
; Variable Sign Embedded Multipliers    ; 0           ;
; Dedicated Input Shift Register Chains ; 0           ;
+---------------------------------------+-------------+
Note: number of Embedded Multiplier Blocks used is only available after a successful fit.


+---------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                              ;
+----------------------------------------+----------------------------------------+
; Register name                          ; Reason for Removal                     ;
+----------------------------------------+----------------------------------------+
; test_constant:inst1|const2[0..5]       ; Stuck at GND due to stuck port data_in ;
; test_constant:inst1|const2[6]          ; Stuck at VCC due to stuck port data_in ;
; test_constant:inst1|const2[7]          ; Stuck at GND due to stuck port data_in ;
; test_constant:inst1|const1[0..5]       ; Stuck at GND due to stuck port data_in ;
; test_constant:inst1|const1[6]          ; Stuck at VCC due to stuck port data_in ;
; test_constant:inst1|const1[7]          ; Stuck at GND due to stuck port data_in ;
; Total Number of Removed Registers = 16 ;                                        ;
+----------------------------------------+----------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: test_constant:inst1 ;
+----------------+-------+-----------------------------------------+
; Parameter Name ; Value ; Type                                    ;
+----------------+-------+-----------------------------------------+
; n              ; 8     ; Untyped                                 ;
; x              ; 1.0   ; Signed Float                            ;
+----------------+-------+-----------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -&gt; More Settings" to "Off".


+-----------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: lpm_mult0:inst|lpm_mult:lpm_mult_component ;
+------------------------------------------------+------------+---------------------------+
; Parameter Name                                 ; Value      ; Type                      ;
+------------------------------------------------+------------+---------------------------+
; AUTO_CARRY_CHAINS                              ; ON         ; AUTO_CARRY                ;
; IGNORE_CARRY_BUFFERS                           ; OFF        ; IGNORE_CARRY              ;
; AUTO_CASCADE_CHAINS                            ; ON         ; AUTO_CASCADE              ;
; IGNORE_CASCADE_BUFFERS                         ; OFF        ; IGNORE_CASCADE            ;
; LPM_WIDTHA                                     ; 8          ; Signed Integer            ;
; LPM_WIDTHB                                     ; 8          ; Signed Integer            ;
; LPM_WIDTHP                                     ; 16         ; Signed Integer            ;
; LPM_WIDTHR                                     ; 0          ; Untyped                   ;
; LPM_WIDTHS                                     ; 1          ; Untyped                   ;
; LPM_REPRESENTATION                             ; SIGNED     ; Untyped                   ;
; LPM_PIPELINE                                   ; 0          ; Untyped                   ;
; LATENCY                                        ; 0          ; Untyped                   ;
; INPUT_A_IS_CONSTANT                            ; NO         ; Untyped                   ;
; INPUT_B_IS_CONSTANT                            ; NO         ; Untyped                   ;
; USE_EAB                                        ; OFF        ; Untyped                   ;
; MAXIMIZE_SPEED                                 ; 5          ; Untyped                   ;
; DEVICE_FAMILY                                  ; Cyclone II ; Untyped                   ;
; CARRY_CHAIN                                    ; MANUAL     ; Untyped                   ;
; APEX20K_TECHNOLOGY_MAPPER                      ; LUT        ; TECH_MAPPER_APEX20K       ;
; DEDICATED_MULTIPLIER_CIRCUITRY                 ; YES        ; Untyped                   ;
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0          ; Untyped                   ;
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0          ; Untyped                   ;
; CBXI_PARAMETER                                 ; mult_jkq   ; Untyped                   ;
; INPUT_A_FIXED_VALUE                            ; Bx         ; Untyped                   ;
; INPUT_B_FIXED_VALUE                            ; Bx         ; Untyped                   ;
; USE_AHDL_IMPLEMENTATION                        ; OFF        ; Untyped                   ;
+------------------------------------------------+------------+---------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -&gt; More Settings" to "Off".


+------------------------------------------------------------------------------------+
; lpm_mult Parameter Settings by Entity Instance                                     ;
+---------------------------------------+--------------------------------------------+
; Name                                  ; Value                                      ;
+---------------------------------------+--------------------------------------------+
; Number of entity instances            ; 1                                          ;
; Entity Instance                       ; lpm_mult0:inst|lpm_mult:lpm_mult_component ;
;     -- LPM_WIDTHA                     ; 8                                          ;
;     -- LPM_WIDTHB                     ; 8                                          ;
;     -- LPM_WIDTHP                     ; 16                                         ;
;     -- LPM_REPRESENTATION             ; SIGNED                                     ;
;     -- INPUT_A_IS_CONSTANT            ; NO                                         ;
;     -- INPUT_B_IS_CONSTANT            ; NO                                         ;
;     -- USE_EAB                        ; OFF                                        ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; YES                                        ;
;     -- INPUT_A_FIXED_VALUE            ; Bx                                         ;
;     -- INPUT_B_FIXED_VALUE            ; Bx                                         ;
+---------------------------------------+--------------------------------------------+


+-------------------------------+
; Analysis &amp; Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis &amp; Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Web Edition
    Info: Processing started: Sat Jun 09 14:16:57 2012
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off test2 -c test2
Info: Found 1 design units, including 1 entities, in source file test2.bdf
    Info: Found entity 1: test2
Info: Found 2 design units, including 1 entities, in source file test_constant.vhd
    Info: Found design unit 1: test_constant-behavior
    Info: Found entity 1: test_constant
Info: Elaborating entity "test2" for the top level hierarchy
Warning: Can't find a definition for parameter x -- assuming SF"1.0" was intended to be a quoted string
Info: Elaborating entity "test_constant" for hierarchy "test_constant:inst1"
Warning: Using design file lpm_mult0.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: lpm_mult0-SYN
    Info: Found entity 1: lpm_mult0
Info: Elaborating entity "lpm_mult0" for hierarchy "lpm_mult0:inst"
Info: Found 1 design units, including 1 entities, in source file ../../../altera/72/quartus/libraries/megafunctions/lpm_mult.tdf
    Info: Found entity 1: lpm_mult
Info: Elaborating entity "lpm_mult" for hierarchy "lpm_mult0:inst|lpm_mult:lpm_mult_component"
Info: Elaborated megafunction instantiation "lpm_mult0:inst|lpm_mult:lpm_mult_component"
Info: Found 1 design units, including 1 entities, in source file db/mult_jkq.tdf
    Info: Found entity 1: mult_jkq
Info: Elaborating entity "mult_jkq" for hierarchy "lpm_mult0:inst|lpm_mult:lpm_mult_component|mult_jkq:auto_generated"
Warning (14130): Reduced register "test_constant:inst1|const2[0]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "test_constant:inst1|const2[1]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "test_constant:inst1|const2[2]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "test_constant:inst1|const2[3]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "test_constant:inst1|const2[4]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "test_constant:inst1|const2[5]" with stuck data_in port to stuck value GND
Info: Power-up level of register "test_constant:inst1|const2[6]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "test_constant:inst1|const2[6]" with stuck data_in port to stuck value VCC
Warning (14130): Reduced register "test_constant:inst1|const2[7]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "test_constant:inst1|const1[0]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "test_constant:inst1|const1[1]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "test_constant:inst1|const1[2]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "test_constant:inst1|const1[3]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "test_constant:inst1|const1[4]" with stuck data_in port to stuck value GND
Warning (14130): Reduced register "test_constant:inst1|const1[5]" with stuck data_in port to stuck value GND
Info: Power-up level of register "test_constant:inst1|const1[6]" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "test_constant:inst1|const1[6]" with stuck data_in port to stuck value VCC
Warning (14130): Reduced register "test_constant:inst1|const1[7]" with stuck data_in port to stuck value GND
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "LEDG[7]" stuck at GND
    Warning (13410): Pin "LEDG[6]" stuck at VCC
    Warning (13410): Pin "LEDG[5]" stuck at GND
    Warning (13410): Pin "LEDG[4]" stuck at GND
    Warning (13410): Pin "LEDG[3]" stuck at GND
    Warning (13410): Pin "LEDG[2]" stuck at GND
    Warning (13410): Pin "LEDG[1]" stuck at GND
    Warning (13410): Pin "LEDG[0]" stuck at GND
Warning: Design contains 1 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "CLOCK_50"
Info: Implemented 34 device resources after synthesis - the final resource count might be different
    Info: Implemented 9 input pins
    Info: Implemented 24 output pins
    Info: Implemented 1 DSP elements
Info: Quartus II Analysis &amp; Synthesis was successful. 0 errors, 29 warnings
    Info: Allocated 210 megabytes of memory during processing
    Info: Processing ended: Sat Jun 09 14:16:58 2012
    Info: Elapsed time: 00:00:01


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