|equalizer
CLOCK_50 => lcd_controller:inst1.clk
CLOCK_50 => taktgenerator:inst7.clk_in
CLOCK_50 => equalizer_controller:inst2.clk
SW[0] => zaehler20:inst15.reset
SW[0] => zaehler14:inst4.reset
SW[1] => lcd_controller:inst1.rst
SW[1] => equalizer_controller:inst2.mutein
SW[2] => ~NO_FANOUT~
SW[3] => zaehler14:inst4.load
SW[4] => zaehler20:inst15.input_c[0]
SW[4] => equalizer_controller:inst2.input_c[0]
SW[5] => zaehler20:inst15.input_c[1]
SW[5] => equalizer_controller:inst2.input_c[1]
SW[6] => zaehler20:inst15.input_c[2]
SW[6] => equalizer_controller:inst2.input_c[2]
SW[7] => zaehler20:inst15.input_c[3]
SW[7] => equalizer_controller:inst2.input_c[3]
SW[8] => zaehler20:inst15.input_c[4]
SW[8] => equalizer_controller:inst2.input_c[4]
SW[9] => zaehler20:inst15.input_c[5]
SW[9] => equalizer_controller:inst2.input_c[5]
SW[10] => zaehler20:inst15.input_c[6]
SW[10] => equalizer_controller:inst2.input_c[6]
SW[11] => zaehler20:inst15.input_c[7]
SW[11] => equalizer_controller:inst2.input_c[7]
SW[12] => zaehler20:inst15.input_c[8]
SW[12] => equalizer_controller:inst2.input_c[8]
SW[13] => zaehler20:inst15.input_c[9]
SW[13] => equalizer_controller:inst2.input_c[9]
SW[14] => zaehler20:inst15.input_c[10]
SW[14] => equalizer_controller:inst2.input_c[10]
SW[15] => zaehler20:inst15.input_c[11]
SW[15] => equalizer_controller:inst2.input_c[11]
SW[16] => zaehler20:inst15.input_c[12]
SW[16] => equalizer_controller:inst2.input_c[12]
SW[17] => zaehler20:inst15.input_c[13]
SW[17] => equalizer_controller:inst2.input_c[13]
KEY[0] => inst8.IN0
KEY[1] => inst9.IN0
KEY[2] => inst18.IN0
KEY[3] => inst17.IN0
LCD_DATA[0] <> lcd_controller:inst1.lcd_data[0]
LCD_DATA[1] <> lcd_controller:inst1.lcd_data[1]
LCD_DATA[2] <> lcd_controller:inst1.lcd_data[2]
LCD_DATA[3] <> lcd_controller:inst1.lcd_data[3]
LCD_DATA[4] <> lcd_controller:inst1.lcd_data[4]
LCD_DATA[5] <> lcd_controller:inst1.lcd_data[5]
LCD_DATA[6] <> lcd_controller:inst1.lcd_data[6]
LCD_DATA[7] <> lcd_controller:inst1.lcd_data[7]


|equalizer|lcd_controller:inst1
clk => lcd_en~reg0.CLK
clk => stop.CLK
clk => start.CLK
clk => index[0].CLK
clk => index[1].CLK
clk => index[2].CLK
clk => delay[0].CLK
clk => delay[1].CLK
clk => delay[2].CLK
clk => delay[3].CLK
clk => delay[4].CLK
clk => delay[5].CLK
clk => delay[6].CLK
clk => delay[7].CLK
clk => delay[8].CLK
clk => delay[9].CLK
clk => delay[10].CLK
clk => delay[11].CLK
clk => delay[12].CLK
clk => delay[13].CLK
clk => delay[14].CLK
clk => delay[15].CLK
clk => delay[16].CLK
clk => delay[17].CLK
clk => delay[18].CLK
clk => delay[19].CLK
clk => counter[0].CLK
clk => counter[1].CLK
clk => counter[2].CLK
clk => counter[3].CLK
clk => counter[4].CLK
clk => counter[5].CLK
clk => counter[6].CLK
clk => counter[7].CLK
clk => output[0].CLK
clk => output[1].CLK
clk => output[2].CLK
clk => output[3].CLK
clk => output[4].CLK
clk => output[5].CLK
clk => output[6].CLK
clk => output[7].CLK
clk => output[8].CLK
rst => output.OUTPUTSELECT
rst => output.OUTPUTSELECT
rst => output.OUTPUTSELECT
rst => output.OUTPUTSELECT
rst => output.OUTPUTSELECT
rst => output.OUTPUTSELECT
rst => output.OUTPUTSELECT
rst => output.OUTPUTSELECT
rst => output.OUTPUTSELECT
rst => counter.OUTPUTSELECT
rst => counter.OUTPUTSELECT
rst => counter.OUTPUTSELECT
rst => counter.OUTPUTSELECT
rst => counter.OUTPUTSELECT
rst => counter.OUTPUTSELECT
rst => counter.OUTPUTSELECT
rst => counter.OUTPUTSELECT
rst => delay.OUTPUTSELECT
rst => delay.OUTPUTSELECT
rst => delay.OUTPUTSELECT
rst => delay.OUTPUTSELECT
rst => delay.OUTPUTSELECT
rst => delay.OUTPUTSELECT
rst => delay.OUTPUTSELECT
rst => delay.OUTPUTSELECT
rst => delay.OUTPUTSELECT
rst => delay.OUTPUTSELECT
rst => delay.OUTPUTSELECT
rst => delay.OUTPUTSELECT
rst => delay.OUTPUTSELECT
rst => delay.OUTPUTSELECT
rst => delay.OUTPUTSELECT
rst => delay.OUTPUTSELECT
rst => delay.OUTPUTSELECT
rst => delay.OUTPUTSELECT
rst => delay.OUTPUTSELECT
rst => delay.OUTPUTSELECT
rst => index.OUTPUTSELECT
rst => index.OUTPUTSELECT
rst => index.OUTPUTSELECT
rst => start.OUTPUTSELECT
rst => stop.OUTPUTSELECT
rst => lcd_en~reg0.ENA


|equalizer|db_out:inst19


|equalizer|bcd_2_seg8Bit:inst
bcd[0] => Equal0.IN9
bcd[0] => Equal1.IN9
bcd[0] => Equal2.IN9
bcd[0] => Equal3.IN9
bcd[0] => Equal4.IN9
bcd[0] => Equal5.IN9
bcd[0] => Equal6.IN9
bcd[0] => Equal7.IN9
bcd[0] => Equal8.IN9
bcd[0] => Equal9.IN9
bcd[0] => Equal10.IN9
bcd[0] => Equal11.IN9
bcd[0] => Equal12.IN9
bcd[0] => Equal13.IN9
bcd[0] => Equal14.IN9
bcd[0] => Equal15.IN9
bcd[0] => Equal16.IN9
bcd[0] => Equal17.IN9
bcd[0] => Equal18.IN9
bcd[0] => Equal19.IN9
bcd[0] => Equal20.IN9
bcd[1] => Equal0.IN8
bcd[1] => Equal1.IN8
bcd[1] => Equal2.IN8
bcd[1] => Equal3.IN8
bcd[1] => Equal4.IN8
bcd[1] => Equal5.IN8
bcd[1] => Equal6.IN8
bcd[1] => Equal7.IN8
bcd[1] => Equal8.IN8
bcd[1] => Equal9.IN8
bcd[1] => Equal10.IN8
bcd[1] => Equal11.IN8
bcd[1] => Equal12.IN8
bcd[1] => Equal13.IN8
bcd[1] => Equal14.IN8
bcd[1] => Equal15.IN8
bcd[1] => Equal16.IN8
bcd[1] => Equal17.IN8
bcd[1] => Equal18.IN8
bcd[1] => Equal19.IN8
bcd[1] => Equal20.IN8
bcd[2] => Equal0.IN7
bcd[2] => Equal1.IN7
bcd[2] => Equal2.IN7
bcd[2] => Equal3.IN7
bcd[2] => Equal4.IN7
bcd[2] => Equal5.IN7
bcd[2] => Equal6.IN7
bcd[2] => Equal7.IN7
bcd[2] => Equal8.IN7
bcd[2] => Equal9.IN7
bcd[2] => Equal10.IN7
bcd[2] => Equal11.IN7
bcd[2] => Equal12.IN7
bcd[2] => Equal13.IN7
bcd[2] => Equal14.IN7
bcd[2] => Equal15.IN7
bcd[2] => Equal16.IN7
bcd[2] => Equal17.IN7
bcd[2] => Equal18.IN7
bcd[2] => Equal19.IN7
bcd[2] => Equal20.IN7
bcd[3] => Equal0.IN6
bcd[3] => Equal1.IN6
bcd[3] => Equal2.IN6
bcd[3] => Equal3.IN6
bcd[3] => Equal4.IN6
bcd[3] => Equal5.IN6
bcd[3] => Equal6.IN6
bcd[3] => Equal7.IN6
bcd[3] => Equal8.IN6
bcd[3] => Equal9.IN6
bcd[3] => Equal10.IN6
bcd[3] => Equal11.IN6
bcd[3] => Equal12.IN6
bcd[3] => Equal13.IN6
bcd[3] => Equal14.IN6
bcd[3] => Equal15.IN6
bcd[3] => Equal16.IN6
bcd[3] => Equal17.IN6
bcd[3] => Equal18.IN6
bcd[3] => Equal19.IN6
bcd[3] => Equal20.IN6
bcd[4] => Equal0.IN5
bcd[4] => Equal1.IN5
bcd[4] => Equal2.IN5
bcd[4] => Equal3.IN5
bcd[4] => Equal4.IN5
bcd[4] => Equal5.IN5
bcd[4] => Equal6.IN5
bcd[4] => Equal7.IN5
bcd[4] => Equal8.IN5
bcd[4] => Equal9.IN5
bcd[4] => Equal10.IN5
bcd[4] => Equal11.IN5
bcd[4] => Equal12.IN5
bcd[4] => Equal13.IN5
bcd[4] => Equal14.IN5
bcd[4] => Equal15.IN5
bcd[4] => Equal16.IN5
bcd[4] => Equal17.IN5
bcd[4] => Equal18.IN5
bcd[4] => Equal19.IN5
bcd[4] => Equal20.IN5


|equalizer|zaehler20:inst15
clk => save13[0].CLK
clk => save13[1].CLK
clk => save13[2].CLK
clk => save13[3].CLK
clk => save13[4].CLK
clk => save12[0].CLK
clk => save12[1].CLK
clk => save12[2].CLK
clk => save12[3].CLK
clk => save12[4].CLK
clk => save11[0].CLK
clk => save11[1].CLK
clk => save11[2].CLK
clk => save11[3].CLK
clk => save11[4].CLK
clk => save10[0].CLK
clk => save10[1].CLK
clk => save10[2].CLK
clk => save10[3].CLK
clk => save10[4].CLK
clk => save9[0].CLK
clk => save9[1].CLK
clk => save9[2].CLK
clk => save9[3].CLK
clk => save9[4].CLK
clk => save8[0].CLK
clk => save8[1].CLK
clk => save8[2].CLK
clk => save8[3].CLK
clk => save8[4].CLK
clk => save7[0].CLK
clk => save7[1].CLK
clk => save7[2].CLK
clk => save7[3].CLK
clk => save7[4].CLK
clk => save6[0].CLK
clk => save6[1].CLK
clk => save6[2].CLK
clk => save6[3].CLK
clk => save6[4].CLK
clk => save5[0].CLK
clk => save5[1].CLK
clk => save5[2].CLK
clk => save5[3].CLK
clk => save5[4].CLK
clk => save4[0].CLK
clk => save4[1].CLK
clk => save4[2].CLK
clk => save4[3].CLK
clk => save4[4].CLK
clk => save3[0].CLK
clk => save3[1].CLK
clk => save3[2].CLK
clk => save3[3].CLK
clk => save3[4].CLK
clk => save2[0].CLK
clk => save2[1].CLK
clk => save2[2].CLK
clk => save2[3].CLK
clk => save2[4].CLK
clk => save1[0].CLK
clk => save1[1].CLK
clk => save1[2].CLK
clk => save1[3].CLK
clk => save1[4].CLK
clk => save0[0].CLK
clk => save0[1].CLK
clk => save0[2].CLK
clk => save0[3].CLK
clk => save0[4].CLK
clk => counter[0].CLK
clk => counter[1].CLK
clk => counter[2].CLK
clk => counter[3].CLK
clk => counter[4].CLK
inc => process_0.IN0
inc => process_0.IN0
dec => process_0.IN1
dec => process_0.IN1
load => save13[0].OUTPUTSELECT
load => save13[1].OUTPUTSELECT
load => save13[2].OUTPUTSELECT
load => save13[3].OUTPUTSELECT
load => save13[4].OUTPUTSELECT
load => save12[0].OUTPUTSELECT
load => save12[1].OUTPUTSELECT
load => save12[2].OUTPUTSELECT
load => save12[3].OUTPUTSELECT
load => save12[4].OUTPUTSELECT
load => save11[0].OUTPUTSELECT
load => save11[1].OUTPUTSELECT
load => save11[2].OUTPUTSELECT
load => save11[3].OUTPUTSELECT
load => save11[4].OUTPUTSELECT
load => save10[0].OUTPUTSELECT
load => save10[1].OUTPUTSELECT
load => save10[2].OUTPUTSELECT
load => save10[3].OUTPUTSELECT
load => save10[4].OUTPUTSELECT
load => save9[0].OUTPUTSELECT
load => save9[1].OUTPUTSELECT
load => save9[2].OUTPUTSELECT
load => save9[3].OUTPUTSELECT
load => save9[4].OUTPUTSELECT
load => save8[0].OUTPUTSELECT
load => save8[1].OUTPUTSELECT
load => save8[2].OUTPUTSELECT
load => save8[3].OUTPUTSELECT
load => save8[4].OUTPUTSELECT
load => save7[0].OUTPUTSELECT
load => save7[1].OUTPUTSELECT
load => save7[2].OUTPUTSELECT
load => save7[3].OUTPUTSELECT
load => save7[4].OUTPUTSELECT
load => save6[0].OUTPUTSELECT
load => save6[1].OUTPUTSELECT
load => save6[2].OUTPUTSELECT
load => save6[3].OUTPUTSELECT
load => save6[4].OUTPUTSELECT
load => save5[0].OUTPUTSELECT
load => save5[1].OUTPUTSELECT
load => save5[2].OUTPUTSELECT
load => save5[3].OUTPUTSELECT
load => save5[4].OUTPUTSELECT
load => save4[0].OUTPUTSELECT
load => save4[1].OUTPUTSELECT
load => save4[2].OUTPUTSELECT
load => save4[3].OUTPUTSELECT
load => save4[4].OUTPUTSELECT
load => save3[0].OUTPUTSELECT
load => save3[1].OUTPUTSELECT
load => save3[2].OUTPUTSELECT
load => save3[3].OUTPUTSELECT
load => save3[4].OUTPUTSELECT
load => save2[0].OUTPUTSELECT
load => save2[1].OUTPUTSELECT
load => save2[2].OUTPUTSELECT
load => save2[3].OUTPUTSELECT
load => save2[4].OUTPUTSELECT
load => save1[0].OUTPUTSELECT
load => save1[1].OUTPUTSELECT
load => save1[2].OUTPUTSELECT
load => save1[3].OUTPUTSELECT
load => save1[4].OUTPUTSELECT
load => save0[0].OUTPUTSELECT
load => save0[1].OUTPUTSELECT
load => save0[2].OUTPUTSELECT
load => save0[3].OUTPUTSELECT
load => save0[4].OUTPUTSELECT
load => counter[4].IN0
input[0] => Equal0.IN9
input[0] => Equal1.IN9
input[0] => Equal2.IN9
input[0] => Equal3.IN9
input[0] => Equal4.IN9
input[0] => Equal5.IN9
input[0] => Equal6.IN9
input[0] => Equal7.IN9
input[0] => Equal8.IN9
input[0] => Equal9.IN9
input[0] => Equal10.IN9
input[0] => Equal11.IN9
input[0] => Equal12.IN9
input[0] => Equal13.IN9
input[1] => Equal0.IN8
input[1] => Equal1.IN8
input[1] => Equal2.IN8
input[1] => Equal3.IN8
input[1] => Equal4.IN8
input[1] => Equal5.IN8
input[1] => Equal6.IN8
input[1] => Equal7.IN8
input[1] => Equal8.IN8
input[1] => Equal9.IN8
input[1] => Equal10.IN8
input[1] => Equal11.IN8
input[1] => Equal12.IN8
input[1] => Equal13.IN8
input[2] => Equal0.IN7
input[2] => Equal1.IN7
input[2] => Equal2.IN7
input[2] => Equal3.IN7
input[2] => Equal4.IN7
input[2] => Equal5.IN7
input[2] => Equal6.IN7
input[2] => Equal7.IN7
input[2] => Equal8.IN7
input[2] => Equal9.IN7
input[2] => Equal10.IN7
input[2] => Equal11.IN7
input[2] => Equal12.IN7
input[2] => Equal13.IN7
input[3] => Equal0.IN6
input[3] => Equal1.IN6
input[3] => Equal2.IN6
input[3] => Equal3.IN6
input[3] => Equal4.IN6
input[3] => Equal5.IN6
input[3] => Equal6.IN6
input[3] => Equal7.IN6
input[3] => Equal8.IN6
input[3] => Equal9.IN6
input[3] => Equal10.IN6
input[3] => Equal11.IN6
input[3] => Equal12.IN6
input[3] => Equal13.IN6
input[4] => Equal0.IN5
input[4] => Equal1.IN5
input[4] => Equal2.IN5
input[4] => Equal3.IN5
input[4] => Equal4.IN5
input[4] => Equal5.IN5
input[4] => Equal6.IN5
input[4] => Equal7.IN5
input[4] => Equal8.IN5
input[4] => Equal9.IN5
input[4] => Equal10.IN5
input[4] => Equal11.IN5
input[4] => Equal12.IN5
input[4] => Equal13.IN5
input_c[0] => process_0.IN1
input_c[1] => process_0.IN1
input_c[2] => process_0.IN1
input_c[3] => process_0.IN1
input_c[4] => process_0.IN1
input_c[5] => process_0.IN1
input_c[6] => process_0.IN1
input_c[7] => process_0.IN1
input_c[8] => process_0.IN1
input_c[9] => process_0.IN1
input_c[10] => process_0.IN1
input_c[11] => process_0.IN1
input_c[12] => process_0.IN1
input_c[13] => process_0.IN1
reset => counter[0].ACLR
reset => counter[1].ACLR
reset => counter[2].ACLR
reset => counter[3].ACLR
reset => counter[4].ACLR
reset => counter[4].IN1
reset => save13[0].ENA
reset => save0[4].ENA
reset => save0[3].ENA
reset => save0[2].ENA
reset => save0[1].ENA
reset => save0[0].ENA
reset => save1[4].ENA
reset => save1[3].ENA
reset => save1[2].ENA
reset => save1[1].ENA
reset => save1[0].ENA
reset => save2[4].ENA
reset => save2[3].ENA
reset => save2[2].ENA
reset => save2[1].ENA
reset => save2[0].ENA
reset => save3[4].ENA
reset => save3[3].ENA
reset => save3[2].ENA
reset => save3[1].ENA
reset => save3[0].ENA
reset => save4[4].ENA
reset => save4[3].ENA
reset => save4[2].ENA
reset => save4[1].ENA
reset => save4[0].ENA
reset => save5[4].ENA
reset => save5[3].ENA
reset => save5[2].ENA
reset => save5[1].ENA
reset => save5[0].ENA
reset => save6[4].ENA
reset => save6[3].ENA
reset => save6[2].ENA
reset => save6[1].ENA
reset => save6[0].ENA
reset => save7[4].ENA
reset => save7[3].ENA
reset => save7[2].ENA
reset => save7[1].ENA
reset => save7[0].ENA
reset => save8[4].ENA
reset => save8[3].ENA
reset => save8[2].ENA
reset => save8[1].ENA
reset => save8[0].ENA
reset => save9[4].ENA
reset => save9[3].ENA
reset => save9[2].ENA
reset => save9[1].ENA
reset => save9[0].ENA
reset => save10[4].ENA
reset => save10[3].ENA
reset => save10[2].ENA
reset => save10[1].ENA
reset => save10[0].ENA
reset => save11[4].ENA
reset => save11[3].ENA
reset => save11[2].ENA
reset => save11[1].ENA
reset => save11[0].ENA
reset => save12[4].ENA
reset => save12[3].ENA
reset => save12[2].ENA
reset => save12[1].ENA
reset => save12[0].ENA
reset => save13[4].ENA
reset => save13[3].ENA
reset => save13[2].ENA
reset => save13[1].ENA


|equalizer|taktgenerator:inst7
clk_in => counter[0].CLK
clk_in => counter[1].CLK
clk_in => counter[2].CLK
clk_in => counter[3].CLK
clk_in => counter[4].CLK
clk_in => counter[5].CLK
clk_in => counter[6].CLK
clk_in => counter[7].CLK
clk_in => counter[8].CLK
clk_in => counter[9].CLK
clk_in => counter[10].CLK
clk_in => counter[11].CLK
clk_in => counter[12].CLK
clk_in => counter[13].CLK
clk_in => counter[14].CLK
clk_in => counter[15].CLK
clk_in => counter[16].CLK
clk_in => counter[17].CLK
clk_in => counter[18].CLK
clk_in => counter[19].CLK
clk_in => counter[20].CLK
clk_in => counter[21].CLK
clk_in => counter[22].CLK
clk_in => counter[23].CLK
clk_in => counter[24].CLK
clk_in => counter[25].CLK
clk_in => counter[26].CLK
clk_in => counter[27].CLK
clk_in => i_clk_out.CLK


|equalizer|zaehler14:inst4
clk => counter[0].CLK
clk => counter[1].CLK
clk => counter[2].CLK
clk => counter[3].CLK
clk => counter[4].CLK
inc => process_0.IN0
inc => process_0.IN0
dec => process_0.IN1
dec => process_0.IN1
load => counter[4].IN1
input[0] => counter[0].ADATA
input[1] => counter[1].ADATA
input[2] => counter[2].ADATA
input[3] => counter[3].ADATA
input[4] => counter[4].ADATA
reset => process_0.IN1


|equalizer|minus_out:inst21
a_in[0] => Equal0.IN13
a_in[1] => Equal0.IN12
a_in[2] => Equal0.IN11
a_in[3] => Equal0.IN10
a_in[4] => Equal0.IN9
a_in[5] => Equal0.IN8
a_in[6] => Equal0.IN7
b_in[0] => Equal1.IN13
b_in[1] => Equal1.IN12
b_in[2] => Equal1.IN11
b_in[3] => Equal1.IN10
b_in[4] => Equal1.IN9
b_in[5] => Equal1.IN8
b_in[6] => Equal1.IN7


|equalizer|bcd_2_seg8Bit:inst5
bcd[0] => Equal0.IN9
bcd[0] => Equal1.IN9
bcd[0] => Equal2.IN9
bcd[0] => Equal3.IN9
bcd[0] => Equal4.IN9
bcd[0] => Equal5.IN9
bcd[0] => Equal6.IN9
bcd[0] => Equal7.IN9
bcd[0] => Equal8.IN9
bcd[0] => Equal9.IN9
bcd[0] => Equal10.IN9
bcd[0] => Equal11.IN9
bcd[0] => Equal12.IN9
bcd[0] => Equal13.IN9
bcd[0] => Equal14.IN9
bcd[0] => Equal15.IN9
bcd[0] => Equal16.IN9
bcd[0] => Equal17.IN9
bcd[0] => Equal18.IN9
bcd[0] => Equal19.IN9
bcd[0] => Equal20.IN9
bcd[1] => Equal0.IN8
bcd[1] => Equal1.IN8
bcd[1] => Equal2.IN8
bcd[1] => Equal3.IN8
bcd[1] => Equal4.IN8
bcd[1] => Equal5.IN8
bcd[1] => Equal6.IN8
bcd[1] => Equal7.IN8
bcd[1] => Equal8.IN8
bcd[1] => Equal9.IN8
bcd[1] => Equal10.IN8
bcd[1] => Equal11.IN8
bcd[1] => Equal12.IN8
bcd[1] => Equal13.IN8
bcd[1] => Equal14.IN8
bcd[1] => Equal15.IN8
bcd[1] => Equal16.IN8
bcd[1] => Equal17.IN8
bcd[1] => Equal18.IN8
bcd[1] => Equal19.IN8
bcd[1] => Equal20.IN8
bcd[2] => Equal0.IN7
bcd[2] => Equal1.IN7
bcd[2] => Equal2.IN7
bcd[2] => Equal3.IN7
bcd[2] => Equal4.IN7
bcd[2] => Equal5.IN7
bcd[2] => Equal6.IN7
bcd[2] => Equal7.IN7
bcd[2] => Equal8.IN7
bcd[2] => Equal9.IN7
bcd[2] => Equal10.IN7
bcd[2] => Equal11.IN7
bcd[2] => Equal12.IN7
bcd[2] => Equal13.IN7
bcd[2] => Equal14.IN7
bcd[2] => Equal15.IN7
bcd[2] => Equal16.IN7
bcd[2] => Equal17.IN7
bcd[2] => Equal18.IN7
bcd[2] => Equal19.IN7
bcd[2] => Equal20.IN7
bcd[3] => Equal0.IN6
bcd[3] => Equal1.IN6
bcd[3] => Equal2.IN6
bcd[3] => Equal3.IN6
bcd[3] => Equal4.IN6
bcd[3] => Equal5.IN6
bcd[3] => Equal6.IN6
bcd[3] => Equal7.IN6
bcd[3] => Equal8.IN6
bcd[3] => Equal9.IN6
bcd[3] => Equal10.IN6
bcd[3] => Equal11.IN6
bcd[3] => Equal12.IN6
bcd[3] => Equal13.IN6
bcd[3] => Equal14.IN6
bcd[3] => Equal15.IN6
bcd[3] => Equal16.IN6
bcd[3] => Equal17.IN6
bcd[3] => Equal18.IN6
bcd[3] => Equal19.IN6
bcd[3] => Equal20.IN6
bcd[4] => Equal0.IN5
bcd[4] => Equal1.IN5
bcd[4] => Equal2.IN5
bcd[4] => Equal3.IN5
bcd[4] => Equal4.IN5
bcd[4] => Equal5.IN5
bcd[4] => Equal6.IN5
bcd[4] => Equal7.IN5
bcd[4] => Equal8.IN5
bcd[4] => Equal9.IN5
bcd[4] => Equal10.IN5
bcd[4] => Equal11.IN5
bcd[4] => Equal12.IN5
bcd[4] => Equal13.IN5
bcd[4] => Equal14.IN5
bcd[4] => Equal15.IN5
bcd[4] => Equal16.IN5
bcd[4] => Equal17.IN5
bcd[4] => Equal18.IN5
bcd[4] => Equal19.IN5
bcd[4] => Equal20.IN5


|equalizer|equalizer_controller:inst2
clk => muteout~reg0.CLK
clk => en~reg0.CLK
clk => out_c[0]~reg0.CLK
clk => out_c[1]~reg0.CLK
clk => out_c[2]~reg0.CLK
clk => out_c[3]~reg0.CLK
clk => out_c[4]~reg0.CLK
clk => out_c[5]~reg0.CLK
clk => out_c[6]~reg0.CLK
clk => out_c[7]~reg0.CLK
clk => out_c[8]~reg0.CLK
clk => out_c[9]~reg0.CLK
clk => out_c[10]~reg0.CLK
clk => out_c[11]~reg0.CLK
clk => out_c[12]~reg0.CLK
clk => out_c[13]~reg0.CLK
clk => out_c[14]~reg0.CLK
clk => out_c[15]~reg0.CLK
clk => out_LED[0]~reg0.CLK
clk => out_LED[1]~reg0.CLK
clk => out_LED[2]~reg0.CLK
clk => out_LED[3]~reg0.CLK
clk => out_LED[4]~reg0.CLK
clk => out_LED[5]~reg0.CLK
clk => out_LED[6]~reg0.CLK
clk => out_LED[7]~reg0.CLK
clk => out_LED[8]~reg0.CLK
clk => out_LED[9]~reg0.CLK
clk => out_LED[10]~reg0.CLK
clk => out_LED[11]~reg0.CLK
clk => out_LED[12]~reg0.CLK
clk => out_LED[13]~reg0.CLK
input_c[0] => out_c.DATAA
input_c[1] => out_c.DATAA
input_c[1] => out_c.DATAB
input_c[2] => out_c.DATAA
input_c[2] => out_c.DATAB
input_c[2] => out_c.DATAB
input_c[3] => out_c.DATAA
input_c[3] => out_c.DATAB
input_c[3] => out_c.DATAB
input_c[3] => out_c.DATAB
input_c[4] => out_c.DATAA
input_c[4] => out_c.DATAB
input_c[4] => out_c.DATAB
input_c[4] => out_c.DATAB
input_c[4] => out_c.DATAB
input_c[5] => out_c.DATAA
input_c[5] => out_c.DATAB
input_c[5] => out_c.DATAB
input_c[5] => out_c.DATAB
input_c[5] => out_c.DATAB
input_c[5] => out_c.DATAB
input_c[6] => out_c.DATAA
input_c[6] => out_c.DATAB
input_c[6] => out_c.DATAB
input_c[6] => out_c.DATAB
input_c[6] => out_c.DATAB
input_c[6] => out_c.DATAB
input_c[6] => out_c.DATAB
input_c[7] => out_c.DATAA
input_c[7] => out_c.DATAB
input_c[7] => out_c.DATAB
input_c[7] => out_c.DATAB
input_c[7] => out_c.DATAB
input_c[7] => out_c.DATAB
input_c[7] => out_c.DATAB
input_c[7] => out_c.DATAB
input_c[8] => out_c.DATAA
input_c[8] => out_c.DATAB
input_c[8] => out_c.DATAB
input_c[8] => out_c.DATAB
input_c[8] => out_c.DATAB
input_c[8] => out_c.DATAB
input_c[8] => out_c.DATAB
input_c[8] => out_c.DATAB
input_c[8] => out_c.DATAB
input_c[9] => out_c.DATAA
input_c[9] => out_c.DATAB
input_c[9] => out_c.DATAB
input_c[9] => out_c.DATAB
input_c[9] => out_c.DATAB
input_c[9] => out_c.DATAB
input_c[9] => out_c.DATAB
input_c[9] => out_c.DATAB
input_c[9] => out_c.DATAB
input_c[9] => out_c.DATAB
input_c[10] => out_c.DATAA
input_c[10] => out_c.DATAB
input_c[10] => out_c.DATAB
input_c[10] => out_c.DATAB
input_c[10] => out_c.DATAB
input_c[10] => out_c.DATAB
input_c[10] => out_c.DATAB
input_c[10] => out_c.DATAB
input_c[10] => out_c.DATAB
input_c[10] => out_c.DATAB
input_c[10] => out_c.DATAB
input_c[11] => out_c.DATAA
input_c[11] => out_c.DATAB
input_c[11] => out_c.DATAB
input_c[11] => out_c.DATAB
input_c[11] => out_c.DATAB
input_c[11] => out_c.DATAB
input_c[11] => out_c.DATAB
input_c[11] => out_c.DATAB
input_c[11] => out_c.DATAB
input_c[11] => out_c.DATAB
input_c[11] => out_c.DATAB
input_c[11] => out_c.DATAB
input_c[12] => out_c.DATAA
input_c[12] => out_c.DATAB
input_c[12] => out_c.DATAB
input_c[12] => out_c.DATAB
input_c[12] => out_c.DATAB
input_c[12] => out_c.DATAB
input_c[12] => out_c.DATAB
input_c[12] => out_c.DATAB
input_c[12] => out_c.DATAB
input_c[12] => out_c.DATAB
input_c[12] => out_c.DATAB
input_c[12] => out_c.DATAB
input_c[12] => out_c.DATAB
input_c[13] => out_c.DATAA
input_c[13] => out_c.DATAB
input_c[13] => out_c.DATAB
input_c[13] => out_c.DATAB
input_c[13] => out_c.DATAB
input_c[13] => out_c.DATAB
input_c[13] => out_c.DATAB
input_c[13] => out_c.DATAB
input_c[13] => out_c.DATAB
input_c[13] => out_c.DATAB
input_c[13] => out_c.DATAB
input_c[13] => out_c.DATAB
input_c[13] => out_c.DATAB
input_c[13] => out_c.DATAB
input_s[0] => Equal0.IN11
input_s[0] => Equal1.IN11
input_s[0] => Equal2.IN11
input_s[0] => Equal3.IN11
input_s[0] => Equal4.IN11
input_s[0] => Equal5.IN11
input_s[0] => Equal6.IN17
input_s[0] => Equal7.IN11
input_s[0] => Equal8.IN11
input_s[0] => Equal9.IN11
input_s[0] => Equal10.IN11
input_s[0] => Equal11.IN11
input_s[0] => Equal12.IN11
input_s[0] => Equal13.IN11
input_s[1] => Equal0.IN10
input_s[1] => Equal1.IN10
input_s[1] => Equal2.IN10
input_s[1] => Equal3.IN10
input_s[1] => Equal4.IN10
input_s[1] => Equal5.IN10
input_s[1] => Equal6.IN16
input_s[1] => Equal7.IN10
input_s[1] => Equal8.IN10
input_s[1] => Equal9.IN10
input_s[1] => Equal10.IN10
input_s[1] => Equal11.IN10
input_s[1] => Equal12.IN10
input_s[1] => Equal13.IN10
input_s[2] => Equal0.IN9
input_s[2] => Equal1.IN9
input_s[2] => Equal2.IN9
input_s[2] => Equal3.IN9
input_s[2] => Equal4.IN9
input_s[2] => Equal5.IN9
input_s[2] => Equal6.IN15
input_s[2] => Equal7.IN9
input_s[2] => Equal8.IN9
input_s[2] => Equal9.IN9
input_s[2] => Equal10.IN9
input_s[2] => Equal11.IN9
input_s[2] => Equal12.IN9
input_s[2] => Equal13.IN9
input_s[3] => Equal0.IN8
input_s[3] => Equal1.IN8
input_s[3] => Equal2.IN8
input_s[3] => Equal3.IN8
input_s[3] => Equal4.IN8
input_s[3] => Equal5.IN8
input_s[3] => Equal6.IN14
input_s[3] => Equal7.IN8
input_s[3] => Equal8.IN8
input_s[3] => Equal9.IN8
input_s[3] => Equal10.IN8
input_s[3] => Equal11.IN8
input_s[3] => Equal12.IN8
input_s[3] => Equal13.IN8
input_s[4] => Equal0.IN7
input_s[4] => Equal1.IN7
input_s[4] => Equal2.IN7
input_s[4] => Equal3.IN7
input_s[4] => Equal4.IN7
input_s[4] => Equal5.IN7
input_s[4] => Equal6.IN13
input_s[4] => Equal7.IN7
input_s[4] => Equal8.IN7
input_s[4] => Equal9.IN7
input_s[4] => Equal10.IN7
input_s[4] => Equal11.IN7
input_s[4] => Equal12.IN7
input_s[4] => Equal13.IN7
inc => process_0.IN0
inc => process_0.IN0
dec => process_0.IN1
dec => process_0.IN1
mutein => out_c.OUTPUTSELECT
mutein => out_c.OUTPUTSELECT
mutein => out_c.OUTPUTSELECT
mutein => out_c.OUTPUTSELECT
mutein => out_c.OUTPUTSELECT
mutein => out_c.OUTPUTSELECT
mutein => out_c.OUTPUTSELECT
mutein => out_c.OUTPUTSELECT
mutein => out_c.OUTPUTSELECT
mutein => out_c.OUTPUTSELECT
mutein => out_c.OUTPUTSELECT
mutein => out_c.OUTPUTSELECT
mutein => out_c.OUTPUTSELECT
mutein => out_c.OUTPUTSELECT
mutein => en.OUTPUTSELECT
mutein => muteout.OUTPUTSELECT