Classic Timing Analyzer report for Equalizer
Tue May 08 18:37:25 2012
Quartus II Version 7.2 Build 151 09/26/2007 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. tpd
  5. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                      ;
+------------------------------+-------+---------------+-------------+--------+---------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From   ; To      ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+--------+---------+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 9.545 ns    ; SW[16] ; LEDG[8] ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;        ;         ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+--------+---------+------------+----------+--------------+


+---------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                      ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                         ; Setting            ; From ; To ; Entity Name ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                    ; EP2C35F672C6       ;      ;    ;             ;
; Timing Models                                                  ; Final              ;      ;    ;             ;
; Default hold multicycle                                        ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                      ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                         ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                 ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                               ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                          ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                        ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                               ; Off                ;      ;    ;             ;
; Enable Clock Latency                                           ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node          ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                          ; 10                 ;      ;    ;             ;
; Number of paths to report                                      ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                   ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                         ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                     ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                   ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis ; Off                ;      ;    ;             ;
+----------------------------------------------------------------+--------------------+------+----+-------------+


+----------------------------------------------------------------+
; tpd                                                            ;
+-------+-------------------+-----------------+--------+---------+
; Slack ; Required P2P Time ; Actual P2P Time ; From   ; To      ;
+-------+-------------------+-----------------+--------+---------+
; N/A   ; None              ; 9.545 ns        ; SW[16] ; LEDG[8] ;
+-------+-------------------+-----------------+--------+---------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Web Edition
    Info: Processing started: Tue May 08 18:37:25 2012
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Equalizer -c Equalizer --timing_analysis_only
Info: Longest tpd from source pin "SW[16]" to destination pin "LEDG[8]" is 9.545 ns
    Info: 1: + IC(0.000 ns) + CELL(0.852 ns) = 0.852 ns; Loc. = PIN_V1; Fanout = 1; PIN Node = 'SW[16]'
    Info: 2: + IC(5.935 ns) + CELL(2.758 ns) = 9.545 ns; Loc. = PIN_Y12; Fanout = 0; PIN Node = 'LEDG[8]'
    Info: Total cell delay = 3.610 ns ( 37.82 % )
    Info: Total interconnect delay = 5.935 ns ( 62.18 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Allocated 165 megabytes of memory during processing
    Info: Processing ended: Tue May 08 18:37:25 2012
    Info: Elapsed time: 00:00:00


