Analysis & Synthesis report for Equalizer
Fri Jun 08 14:35:30 2012
Quartus II 64-Bit Version 11.1 Build 173 11/01/2011 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. Analysis & Synthesis DSP Block Usage Summary
  9. Analysis & Synthesis IP Cores Summary
 10. State Machine - |Equalizer|audio_unit:inst2|i2c_master:i2c_master_1|reg_fstate
 11. Registers Removed During Synthesis
 12. Removed Registers Triggering Further Register Optimizations
 13. General Register Statistics
 14. Inverted Register Statistics
 15. Multiplexer Restructuring Statistics (Restructuring Performed)
 16. Parameter Settings for User Entity Instance: clock_generator:inst|altpll0:inst|altpll:altpll_component
 17. Parameter Settings for User Entity Instance: clock_generator:inst|altpll1:inst1|altpll:altpll_component
 18. Parameter Settings for User Entity Instance: audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|lpm_mult0:lpm_mult0_1|lpm_mult:lpm_mult_component
 19. Parameter Settings for Inferred Entity Instance: audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|lpm_mult:Mult0
 20. altpll Parameter Settings by Entity Instance
 21. lpm_mult Parameter Settings by Entity Instance
 22. Port Connectivity Checks: "audio_unit:inst2|i2c_master:i2c_master_1"
 23. Elapsed Time Per Partition
 24. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2011 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                   ;
+------------------------------------+-------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Fri Jun 08 14:35:30 2012     ;
; Quartus II 64-Bit Version          ; 11.1 Build 173 11/01/2011 SJ Full Version ;
; Revision Name                      ; Equalizer                                 ;
; Top-level Entity Name              ; Equalizer                                 ;
; Family                             ; Cyclone II                                ;
; Total logic elements               ; 2,579                                     ;
;     Total combinational functions  ; 2,247                                     ;
;     Dedicated logic registers      ; 996                                       ;
; Total registers                    ; 996                                       ;
; Total pins                         ; 79                                        ;
; Total virtual pins                 ; 0                                         ;
; Total memory bits                  ; 0                                         ;
; Embedded Multiplier 9-bit elements ; 27                                        ;
; Total PLLs                         ; 2                                         ;
+------------------------------------+-------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                        ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                     ; Setting            ; Default Value      ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                     ; EP2C35F672C6       ;                    ;
; Top-level entity name                                                      ; Equalizer          ; Equalizer          ;
; Family name                                                                ; Cyclone II         ; Cyclone IV GX      ;
; Use smart compilation                                                      ; Off                ; Off                ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
; Enable compact report table                                                ; Off                ; Off                ;
; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
; Preserve fewer node names                                                  ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
; State Machine Processing                                                   ; Auto               ; Auto               ;
; Safe State Machine                                                         ; Off                ; Off                ;
; Extract Verilog State Machines                                             ; On                 ; On                 ;
; Extract VHDL State Machines                                                ; On                 ; On                 ;
; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
; Parallel Synthesis                                                         ; Off                ; Off                ;
; DSP Block Balancing                                                        ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                         ; On                 ; On                 ;
; Power-Up Don't Care                                                        ; On                 ; On                 ;
; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
; Remove Duplicate Registers                                                 ; On                 ; On                 ;
; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
; Optimization Technique                                                     ; Balanced           ; Balanced           ;
; Carry Chain Length                                                         ; 70                 ; 70                 ;
; Auto Carry Chains                                                          ; On                 ; On                 ;
; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
; Auto ROM Replacement                                                       ; On                 ; On                 ;
; Auto RAM Replacement                                                       ; On                 ; On                 ;
; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
; Strict RAM Replacement                                                     ; Off                ; Off                ;
; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
; Auto Resource Sharing                                                      ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
; Timing-Driven Synthesis                                                    ; Off                ; Off                ;
; Report Parameter Settings                                                  ; On                 ; On                 ;
; Report Source Assignments                                                  ; On                 ; On                 ;
; Report Connectivity Checks                                                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
; HDL message level                                                          ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
; Clock MUX Protection                                                       ; On                 ; On                 ;
; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
; Block Design Naming                                                        ; Auto               ; Auto               ;
; SDC constraint protection                                                  ; Off                ; Off                ;
; Synthesis Effort                                                           ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
; Synthesis Seed                                                             ; 1                  ; 1                  ;
+----------------------------------------------------------------------------+--------------------+--------------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 2      ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                         ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                                         ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------------------+
; Equalizer.bdf                    ; yes             ; User Block Diagram/Schematic File  ; D:/Studium/6.Semester/Programmierbare Logik/APL/Equalizer/Equalizer.bdf              ;
; clock_generator.bdf              ; yes             ; User Block Diagram/Schematic File  ; D:/Studium/6.Semester/Programmierbare Logik/APL/Equalizer/clock_generator.bdf        ;
; altpll0.vhd                      ; yes             ; User Wizard-Generated File         ; D:/Studium/6.Semester/Programmierbare Logik/APL/Equalizer/altpll0.vhd                ;
; altpll1.vhd                      ; yes             ; User Wizard-Generated File         ; D:/Studium/6.Semester/Programmierbare Logik/APL/Equalizer/altpll1.vhd                ;
; clock_divider.vhd                ; yes             ; User VHDL File                     ; D:/Studium/6.Semester/Programmierbare Logik/APL/Equalizer/clock_divider.vhd          ;
; mmi_controller.vhd               ; yes             ; User VHDL File                     ; D:/Studium/6.Semester/Programmierbare Logik/APL/Equalizer/mmi_controller.vhd         ;
; lcd_controller.vhd               ; yes             ; User VHDL File                     ; D:/Studium/6.Semester/Programmierbare Logik/APL/Equalizer/lcd_controller.vhd         ;
; audio_unit.vhd                   ; yes             ; User VHDL File                     ; D:/Studium/6.Semester/Programmierbare Logik/APL/Equalizer/audio_unit.vhd             ;
; MMI.vhd                          ; yes             ; User VHDL File                     ; D:/Studium/6.Semester/Programmierbare Logik/APL/Equalizer/MMI.vhd                    ;
; i2c_master.vhd                   ; yes             ; User VHDL File                     ; D:/Studium/6.Semester/Programmierbare Logik/APL/Equalizer/i2c_master.vhd             ;
; filter_unit.vhd                  ; yes             ; User VHDL File                     ; D:/Studium/6.Semester/Programmierbare Logik/APL/Equalizer/filter_unit.vhd            ;
; filter_arithmetic_unit.vhd       ; yes             ; User VHDL File                     ; D:/Studium/6.Semester/Programmierbare Logik/APL/Equalizer/filter_arithmetic_unit.vhd ;
; audio_input_register.vhd         ; yes             ; User VHDL File                     ; D:/Studium/6.Semester/Programmierbare Logik/APL/Equalizer/audio_input_register.vhd   ;
; audio_output_register.vhd        ; yes             ; User VHDL File                     ; D:/Studium/6.Semester/Programmierbare Logik/APL/Equalizer/audio_output_register.vhd  ;
; iir.vhd                          ; yes             ; User VHDL File                     ; D:/Studium/6.Semester/Programmierbare Logik/APL/Equalizer/iir.vhd                    ;
; db2linear.vhd                    ; yes             ; User VHDL File                     ; D:/Studium/6.Semester/Programmierbare Logik/APL/Equalizer/db2linear.vhd              ;
; lpm_mult0.vhd                    ; yes             ; User Wizard-Generated File         ; D:/Studium/6.Semester/Programmierbare Logik/APL/Equalizer/lpm_mult0.vhd              ;
; altpll.tdf                       ; yes             ; Megafunction                       ; d:/altera/11.1/quartus/libraries/megafunctions/altpll.tdf                            ;
; aglobal111.inc                   ; yes             ; Megafunction                       ; d:/altera/11.1/quartus/libraries/megafunctions/aglobal111.inc                        ;
; stratix_pll.inc                  ; yes             ; Megafunction                       ; d:/altera/11.1/quartus/libraries/megafunctions/stratix_pll.inc                       ;
; stratixii_pll.inc                ; yes             ; Megafunction                       ; d:/altera/11.1/quartus/libraries/megafunctions/stratixii_pll.inc                     ;
; cycloneii_pll.inc                ; yes             ; Megafunction                       ; d:/altera/11.1/quartus/libraries/megafunctions/cycloneii_pll.inc                     ;
; lpm_mult.tdf                     ; yes             ; Megafunction                       ; d:/altera/11.1/quartus/libraries/megafunctions/lpm_mult.tdf                          ;
; lpm_add_sub.inc                  ; yes             ; Megafunction                       ; d:/altera/11.1/quartus/libraries/megafunctions/lpm_add_sub.inc                       ;
; multcore.inc                     ; yes             ; Megafunction                       ; d:/altera/11.1/quartus/libraries/megafunctions/multcore.inc                          ;
; bypassff.inc                     ; yes             ; Megafunction                       ; d:/altera/11.1/quartus/libraries/megafunctions/bypassff.inc                          ;
; altshift.inc                     ; yes             ; Megafunction                       ; d:/altera/11.1/quartus/libraries/megafunctions/altshift.inc                          ;
; db/mult_inq.tdf                  ; yes             ; Auto-Generated Megafunction        ; D:/Studium/6.Semester/Programmierbare Logik/APL/Equalizer/db/mult_inq.tdf            ;
; db/mult_i1t.tdf                  ; yes             ; Auto-Generated Megafunction        ; D:/Studium/6.Semester/Programmierbare Logik/APL/Equalizer/db/mult_i1t.tdf            ;
+----------------------------------+-----------------+------------------------------------+--------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                                                                   ;
+---------------------------------------------+-----------------------------------------------------------------+
; Resource                                    ; Usage                                                           ;
+---------------------------------------------+-----------------------------------------------------------------+
; Estimated Total logic elements              ; 2,579                                                           ;
;                                             ;                                                                 ;
; Total combinational functions               ; 2247                                                            ;
; Logic element usage by number of LUT inputs ;                                                                 ;
;     -- 4 input functions                    ; 1036                                                            ;
;     -- 3 input functions                    ; 657                                                             ;
;     -- <=2 input functions                  ; 554                                                             ;
;                                             ;                                                                 ;
; Logic elements by mode                      ;                                                                 ;
;     -- normal mode                          ; 1509                                                            ;
;     -- arithmetic mode                      ; 738                                                             ;
;                                             ;                                                                 ;
; Total registers                             ; 996                                                             ;
;     -- Dedicated logic registers            ; 996                                                             ;
;     -- I/O registers                        ; 0                                                               ;
;                                             ;                                                                 ;
; I/O pins                                    ; 79                                                              ;
; Embedded Multiplier 9-bit elements          ; 27                                                              ;
; Total PLLs                                  ; 2                                                               ;
;     -- PLLs                                 ; 2                                                               ;
;                                             ;                                                                 ;
; Maximum fan-out node                        ; clock_generator:inst|altpll0:inst|altpll:altpll_component|_clk0 ;
; Maximum fan-out                             ; 782                                                             ;
; Total fan-out                               ; 10702                                                           ;
; Average fan-out                             ; 3.19                                                            ;
+---------------------------------------------+-----------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                ;
+------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node                                 ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                                                                        ; Library Name ;
+------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; |Equalizer                                                 ; 2247 (1)          ; 996 (0)      ; 0           ; 27           ; 1       ; 13        ; 79   ; 0            ; |Equalizer                                                                                                                                                                                 ;              ;
;    |MMI:inst1|                                             ; 926 (0)           ; 270 (0)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Equalizer|MMI:inst1                                                                                                                                                                       ;              ;
;       |lcd_controller:lcd_controller_1|                    ; 131 (131)         ; 39 (39)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Equalizer|MMI:inst1|lcd_controller:lcd_controller_1                                                                                                                                       ;              ;
;       |mmi_controller:mmi_controller_1|                    ; 795 (795)         ; 231 (231)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Equalizer|MMI:inst1|mmi_controller:mmi_controller_1                                                                                                                                       ;              ;
;    |audio_unit:inst2|                                      ; 1307 (1)          ; 716 (0)      ; 0           ; 27           ; 1       ; 13        ; 0    ; 0            ; |Equalizer|audio_unit:inst2                                                                                                                                                                ;              ;
;       |audio_input_register:audio_input_register_1|        ; 95 (95)           ; 84 (84)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Equalizer|audio_unit:inst2|audio_input_register:audio_input_register_1                                                                                                                    ;              ;
;       |audio_output_register:audio_output_register_1|      ; 64 (64)           ; 105 (105)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Equalizer|audio_unit:inst2|audio_output_register:audio_output_register_1                                                                                                                  ;              ;
;       |filter_unit:filter_unit_1|                          ; 1078 (0)          ; 502 (0)      ; 0           ; 27           ; 1       ; 13        ; 0    ; 0            ; |Equalizer|audio_unit:inst2|filter_unit:filter_unit_1                                                                                                                                      ;              ;
;          |filter_arithmetic_unit:filter_arithmetic_unit_1| ; 1078 (165)        ; 502 (195)    ; 0           ; 27           ; 1       ; 13        ; 0    ; 0            ; |Equalizer|audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1                                                                                      ;              ;
;             |db2linear:volume_db2linear|                   ; 319 (319)         ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Equalizer|audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|db2linear:volume_db2linear                                                           ;              ;
;             |iir:filter|                                   ; 472 (249)         ; 307 (307)    ; 0           ; 16           ; 0       ; 8         ; 0    ; 0            ; |Equalizer|audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter                                                                           ;              ;
;                |lpm_mult0:lpm_mult0_1|                     ; 223 (0)           ; 0 (0)        ; 0           ; 16           ; 0       ; 8         ; 0    ; 0            ; |Equalizer|audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|lpm_mult0:lpm_mult0_1                                                     ;              ;
;                   |lpm_mult:lpm_mult_component|            ; 223 (0)           ; 0 (0)        ; 0           ; 16           ; 0       ; 8         ; 0    ; 0            ; |Equalizer|audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|lpm_mult0:lpm_mult0_1|lpm_mult:lpm_mult_component                         ;              ;
;                      |mult_inq:auto_generated|             ; 223 (223)         ; 0 (0)        ; 0           ; 16           ; 0       ; 8         ; 0    ; 0            ; |Equalizer|audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|lpm_mult0:lpm_mult0_1|lpm_mult:lpm_mult_component|mult_inq:auto_generated ;              ;
;             |lpm_mult:Mult0|                               ; 122 (0)           ; 0 (0)        ; 0           ; 11           ; 1       ; 5         ; 0    ; 0            ; |Equalizer|audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|lpm_mult:Mult0                                                                       ;              ;
;                |mult_i1t:auto_generated|                   ; 122 (122)         ; 0 (0)        ; 0           ; 11           ; 1       ; 5         ; 0    ; 0            ; |Equalizer|audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|lpm_mult:Mult0|mult_i1t:auto_generated                                               ;              ;
;       |i2c_master:i2c_master_1|                            ; 69 (69)           ; 25 (25)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Equalizer|audio_unit:inst2|i2c_master:i2c_master_1                                                                                                                                        ;              ;
;    |clock_generator:inst|                                  ; 13 (0)            ; 10 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Equalizer|clock_generator:inst                                                                                                                                                            ;              ;
;       |altpll0:inst|                                       ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Equalizer|clock_generator:inst|altpll0:inst                                                                                                                                               ;              ;
;          |altpll:altpll_component|                         ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Equalizer|clock_generator:inst|altpll0:inst|altpll:altpll_component                                                                                                                       ;              ;
;       |altpll1:inst1|                                      ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Equalizer|clock_generator:inst|altpll1:inst1                                                                                                                                              ;              ;
;          |altpll:altpll_component|                         ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Equalizer|clock_generator:inst|altpll1:inst1|altpll:altpll_component                                                                                                                      ;              ;
;       |clock_divider:inst3|                                ; 13 (13)           ; 10 (10)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Equalizer|clock_generator:inst|clock_divider:inst3                                                                                                                                        ;              ;
+------------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+-----------------------------------------------------+
; Analysis & Synthesis DSP Block Usage Summary        ;
+---------------------------------------+-------------+
; Statistic                             ; Number Used ;
+---------------------------------------+-------------+
; Simple Multipliers (9-bit)            ; 1           ;
; Simple Multipliers (18-bit)           ; 13          ;
; Embedded Multiplier Blocks            ; --          ;
; Embedded Multiplier 9-bit elements    ; 27          ;
; Signed Embedded Multipliers           ; 2           ;
; Unsigned Embedded Multipliers         ; 5           ;
; Mixed Sign Embedded Multipliers       ; 7           ;
; Variable Sign Embedded Multipliers    ; 0           ;
; Dedicated Input Shift Register Chains ; 0           ;
+---------------------------------------+-------------+
Note: number of Embedded Multiplier Blocks used is only available after a successful fit.


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary                                                                                                                                                                                                                                            ;
+--------+--------------+---------+--------------+--------------+----------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------+
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance                                                                                                                        ; IP Include File                                                         ;
+--------+--------------+---------+--------------+--------------+----------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------+
; Altera ; LPM_MULT     ; 11.1    ; N/A          ; N/A          ; |Equalizer|audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|lpm_mult0:lpm_mult0_1 ; D:/Studium/6.Semester/Programmierbare Logik/APL/Equalizer/lpm_mult0.vhd ;
; Altera ; ALTPLL       ; 11.1    ; N/A          ; N/A          ; |Equalizer|clock_generator:inst|altpll0:inst                                                                                           ; D:/Studium/6.Semester/Programmierbare Logik/APL/Equalizer/altpll0.vhd   ;
; Altera ; ALTPLL       ; 11.1    ; N/A          ; N/A          ; |Equalizer|clock_generator:inst|altpll1:inst1                                                                                          ; D:/Studium/6.Semester/Programmierbare Logik/APL/Equalizer/altpll1.vhd   ;
+--------+--------------+---------+--------------+--------------+----------------------------------------------------------------------------------------------------------------------------------------+-------------------------------------------------------------------------+


Encoding Type:  One-Hot
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |Equalizer|audio_unit:inst2|i2c_master:i2c_master_1|reg_fstate                                                                                                                                                                                                        ;
+---------------------------+-----------------+--------------------------+------------------------+------------------+----------------+------------------------+-----------------------+---------------------+------------------+---------------------------+---------------------------+
; Name                      ; reg_fstate.ende ; reg_fstate.stopbedingung ; reg_fstate.stop_warten ; reg_fstate.error ; reg_fstate.ack ; reg_fstate.ack_warten2 ; reg_fstate.ack_warten ; reg_fstate.taktende ; reg_fstate.bit_n ; reg_fstate.startbedingung ; reg_fstate.anfangszustand ;
+---------------------------+-----------------+--------------------------+------------------------+------------------+----------------+------------------------+-----------------------+---------------------+------------------+---------------------------+---------------------------+
; reg_fstate.anfangszustand ; 0               ; 0                        ; 0                      ; 0                ; 0              ; 0                      ; 0                     ; 0                   ; 0                ; 0                         ; 0                         ;
; reg_fstate.startbedingung ; 0               ; 0                        ; 0                      ; 0                ; 0              ; 0                      ; 0                     ; 0                   ; 0                ; 1                         ; 1                         ;
; reg_fstate.bit_n          ; 0               ; 0                        ; 0                      ; 0                ; 0              ; 0                      ; 0                     ; 0                   ; 1                ; 0                         ; 1                         ;
; reg_fstate.taktende       ; 0               ; 0                        ; 0                      ; 0                ; 0              ; 0                      ; 0                     ; 1                   ; 0                ; 0                         ; 1                         ;
; reg_fstate.ack_warten     ; 0               ; 0                        ; 0                      ; 0                ; 0              ; 0                      ; 1                     ; 0                   ; 0                ; 0                         ; 1                         ;
; reg_fstate.ack_warten2    ; 0               ; 0                        ; 0                      ; 0                ; 0              ; 1                      ; 0                     ; 0                   ; 0                ; 0                         ; 1                         ;
; reg_fstate.ack            ; 0               ; 0                        ; 0                      ; 0                ; 1              ; 0                      ; 0                     ; 0                   ; 0                ; 0                         ; 1                         ;
; reg_fstate.error          ; 0               ; 0                        ; 0                      ; 1                ; 0              ; 0                      ; 0                     ; 0                   ; 0                ; 0                         ; 1                         ;
; reg_fstate.stop_warten    ; 0               ; 0                        ; 1                      ; 0                ; 0              ; 0                      ; 0                     ; 0                   ; 0                ; 0                         ; 1                         ;
; reg_fstate.stopbedingung  ; 0               ; 1                        ; 0                      ; 0                ; 0              ; 0                      ; 0                     ; 0                   ; 0                ; 0                         ; 1                         ;
; reg_fstate.ende           ; 1               ; 0                        ; 0                      ; 0                ; 0              ; 0                      ; 0                     ; 0                   ; 0                ; 0                         ; 1                         ;
+---------------------------+-----------------+--------------------------+------------------------+------------------+----------------+------------------------+-----------------------+---------------------+------------------+---------------------------+---------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                                                                                                                                                                                                                                                          ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+
; Register name                                                                                                                                                                    ; Reason for Removal                                                                                                       ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+
; audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|section[0..7]                                                              ; Stuck at GND due to stuck port data_in                                                                                   ;
; MMI:inst1|mmi_controller:mmi_controller_1|db_letter_2[0]                                                                                                                         ; Stuck at VCC due to stuck port data_in                                                                                   ;
; MMI:inst1|mmi_controller:mmi_controller_1|lcd_1[0,3,7]                                                                                                                           ; Stuck at GND due to stuck port data_in                                                                                   ;
; MMI:inst1|mmi_controller:mmi_controller_1|lcd_1[8]                                                                                                                               ; Stuck at VCC due to stuck port data_in                                                                                   ;
; MMI:inst1|mmi_controller:mmi_controller_1|db_letter_2[1]                                                                                                                         ; Stuck at VCC due to stuck port data_in                                                                                   ;
; MMI:inst1|mmi_controller:mmi_controller_1|db_letter_1[0,5]                                                                                                                       ; Stuck at VCC due to stuck port data_in                                                                                   ;
; MMI:inst1|mmi_controller:mmi_controller_1|db_sign[0..5]                                                                                                                          ; Stuck at VCC due to stuck port data_in                                                                                   ;
; MMI:inst1|lcd_controller:lcd_controller_1|stop                                                                                                                                   ; Stuck at GND due to stuck port clock_enable                                                                              ;
; MMI:inst1|lcd_controller:lcd_controller_1|counter[5..7]                                                                                                                          ; Stuck at GND due to stuck port data_in                                                                                   ;
; MMI:inst1|mmi_controller:mmi_controller_1|lcd_1[6]                                                                                                                               ; Merged with MMI:inst1|mmi_controller:mmi_controller_1|lcd_1[2]                                                           ;
; MMI:inst1|mmi_controller:mmi_controller_1|lcd_1[2]                                                                                                                               ; Merged with MMI:inst1|mmi_controller:mmi_controller_1|lcd_1[1]                                                           ;
; MMI:inst1|mmi_controller:mmi_controller_1|lcd_2[5]                                                                                                                               ; Merged with MMI:inst1|mmi_controller:mmi_controller_1|lcd_2[8]                                                           ;
; MMI:inst1|mmi_controller:mmi_controller_1|lcd_3[5,8]                                                                                                                             ; Merged with MMI:inst1|mmi_controller:mmi_controller_1|lcd_2[8]                                                           ;
; MMI:inst1|mmi_controller:mmi_controller_1|lcd_3[7]                                                                                                                               ; Merged with MMI:inst1|mmi_controller:mmi_controller_1|lcd_2[7]                                                           ;
; MMI:inst1|mmi_controller:mmi_controller_1|lcd_2[1..3]                                                                                                                            ; Merged with MMI:inst1|mmi_controller:mmi_controller_1|lcd_2[6]                                                           ;
; MMI:inst1|mmi_controller:mmi_controller_1|lcd_3[6]                                                                                                                               ; Merged with MMI:inst1|mmi_controller:mmi_controller_1|lcd_2[6]                                                           ;
; MMI:inst1|mmi_controller:mmi_controller_1|lcd_3[4]                                                                                                                               ; Merged with MMI:inst1|mmi_controller:mmi_controller_1|lcd_2[4]                                                           ;
; MMI:inst1|mmi_controller:mmi_controller_1|filter_ten[2]                                                                                                                          ; Merged with MMI:inst1|mmi_controller:mmi_controller_1|filter_ten[1]                                                      ;
; audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|b[22,35..37]                                                               ; Merged with audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|b[0]   ;
; audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|b[1,17,20,40,45]                                                           ; Merged with audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|b[13]  ;
; audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|b[2,4,41,46,63]                                                            ; Merged with audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|b[26]  ;
; audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|b[3,8,21,27,28,44]                                                         ; Merged with audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|b[16]  ;
; audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|b[5,9,29,33,42]                                                            ; Merged with audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|b[18]  ;
; audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|b[6,12,30,39]                                                              ; Merged with audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|b[11]  ;
; audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|b[7,14,25,32,47..51]                                                       ; Merged with audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|b[10]  ;
; audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|b[19,23,24,31,34,38,43]                                                    ; Merged with audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|b[15]  ;
; audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|b[54,55,57..61]                                                            ; Merged with audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|b[53]  ;
; audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|a1[1,5,9,13,15,17..20,22..24,29,31,33..38,40,42,43,45,62]                  ; Merged with audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|a1[0]  ;
; audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|a2[0,2..4,8,15,16,19,21..24,26..28,31,34..38,41,43,44,46,52,62,63]         ; Merged with audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|a1[0]  ;
; audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|b0[0..51,62,63]                                                            ; Merged with audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|a1[0]  ;
; audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|b1[0..61,63]                                                               ; Merged with audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|a1[0]  ;
; audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|b2[0..51,62,63]                                                            ; Merged with audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|a1[0]  ;
; audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|s1[1,2,4,7,10,13..15,17,19,20,23..26,31,32,34,38,40,41,43,45..51,56,62,63] ; Merged with audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|a1[0]  ;
; audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|s2[0..51,62,63]                                                            ; Merged with audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|a1[0]  ;
; audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|a1[2..4,6..8,11,12,14,16,21,25..28,30,32,39,41,44,46..61,63]               ; Merged with audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|a1[10] ;
; audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|a2[1,5..7,9..14,17,18,20,25,29,30,32,33,39,40,42,45,47..51,53..61]         ; Merged with audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|a1[10] ;
; audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|b0[52..61]                                                                 ; Merged with audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|a1[10] ;
; audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|b1[62]                                                                     ; Merged with audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|a1[10] ;
; audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|b2[52..61]                                                                 ; Merged with audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|a1[10] ;
; audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|s1[0,3,5,6,8,9,11,12,16,18,21,22,27..30,33,35..37,39,42,44,52..55,57..61]  ; Merged with audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|a1[10] ;
; audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|s2[52..61]                                                                 ; Merged with audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|a1[10] ;
; MMI:inst1|mmi_controller:mmi_controller_1|lcd_4[8]                                                                                                                               ; Merged with MMI:inst1|mmi_controller:mmi_controller_1|lcd_4[5]                                                           ;
; MMI:inst1|mmi_controller:mmi_controller_1|lcd_5[5,8]                                                                                                                             ; Merged with MMI:inst1|mmi_controller:mmi_controller_1|lcd_4[5]                                                           ;
; MMI:inst1|mmi_controller:mmi_controller_1|lcd_6[5,8]                                                                                                                             ; Merged with MMI:inst1|mmi_controller:mmi_controller_1|lcd_4[5]                                                           ;
; MMI:inst1|mmi_controller:mmi_controller_1|lcd_4[4,6,7]                                                                                                                           ; Merged with MMI:inst1|mmi_controller:mmi_controller_1|lcd_4[1]                                                           ;
; MMI:inst1|mmi_controller:mmi_controller_1|lcd_5[3,6,7]                                                                                                                           ; Merged with MMI:inst1|mmi_controller:mmi_controller_1|lcd_4[1]                                                           ;
; MMI:inst1|mmi_controller:mmi_controller_1|lcd_6[6,7]                                                                                                                             ; Merged with MMI:inst1|mmi_controller:mmi_controller_1|lcd_4[1]                                                           ;
; MMI:inst1|mmi_controller:mmi_controller_1|lcd_4[2,3]                                                                                                                             ; Merged with MMI:inst1|mmi_controller:mmi_controller_1|lcd_4[0]                                                           ;
; MMI:inst1|mmi_controller:mmi_controller_1|db_ten[3]                                                                                                                              ; Merged with MMI:inst1|mmi_controller:mmi_controller_1|db_ten[0]                                                          ;
; MMI:inst1|mmi_controller:mmi_controller_1|lcd_6[4]                                                                                                                               ; Merged with MMI:inst1|mmi_controller:mmi_controller_1|lcd_5[4]                                                           ;
; MMI:inst1|mmi_controller:mmi_controller_1|filter_ten[3..5]                                                                                                                       ; Merged with MMI:inst1|mmi_controller:mmi_controller_1|filter_ten[0]                                                      ;
; MMI:inst1|mmi_controller:mmi_controller_1|lcd_2[7]                                                                                                                               ; Stuck at GND due to stuck port data_in                                                                                   ;
; audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|a1[0]                                                                      ; Stuck at GND due to stuck port data_in                                                                                   ;
; audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|a1[10]                                                                     ; Stuck at VCC due to stuck port data_in                                                                                   ;
; MMI:inst1|mmi_controller:mmi_controller_1|filter_ten[6]                                                                                                                          ; Stuck at VCC due to stuck port data_in                                                                                   ;
; audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|b[15]                                                                      ; Stuck at GND due to stuck port data_in                                                                                   ;
; MMI:inst1|mmi_controller:mmi_controller_1|lcd_4[1]                                                                                                                               ; Stuck at GND due to stuck port data_in                                                                                   ;
; MMI:inst1|mmi_controller:mmi_controller_1|lcd_2[8]                                                                                                                               ; Stuck at VCC due to stuck port data_in                                                                                   ;
; MMI:inst1|mmi_controller:mmi_controller_1|lcd_4[5]                                                                                                                               ; Stuck at VCC due to stuck port data_in                                                                                   ;
; audio_unit:inst2|audio_output_register:audio_output_register_1|sdr[0]                                                                                                            ; Stuck at GND due to stuck port data_in                                                                                   ;
; audio_unit:inst2|audio_output_register:audio_output_register_1|sdl[0]                                                                                                            ; Stuck at GND due to stuck port data_in                                                                                   ;
; Total Number of Removed Registers = 566                                                                                                                                          ;                                                                                                                          ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations                                                                                                                                                                                                 ;
+------------------------------------------------------------------------------------------------------------------+---------------------------+--------------------------------------------------------------------------------------------------------------+
; Register name                                                                                                    ; Reason for Removal        ; Registers Removed due to This Register                                                                       ;
+------------------------------------------------------------------------------------------------------------------+---------------------------+--------------------------------------------------------------------------------------------------------------+
; audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|section[0] ; Stuck at GND              ; audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|a1[0], ;
;                                                                                                                  ; due to stuck port data_in ; audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|a1[10] ;
+------------------------------------------------------------------------------------------------------------------+---------------------------+--------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 996   ;
; Number of registers using Synchronous Clear  ; 58    ;
; Number of registers using Synchronous Load   ; 153   ;
; Number of registers using Asynchronous Clear ; 19    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 806   ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+---------------------------------------------------------------+
; Inverted Register Statistics                                  ;
+-----------------------------------------------------+---------+
; Inverted Register                                   ; Fan out ;
+-----------------------------------------------------+---------+
; MMI:inst1|lcd_controller:lcd_controller_1|start     ; 1       ;
; MMI:inst1|mmi_controller:mmi_controller_1|filter[0] ; 19      ;
; audio_unit:inst2|i2c_master:i2c_master_1|SDIN~en    ; 1       ;
; MMI:inst1|mmi_controller:mmi_controller_1|lcd_1[5]  ; 1       ;
; Total number of inverted registers = 4              ;         ;
+-----------------------------------------------------+---------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                                                                                            ;
+--------------------+-----------+---------------+----------------------+------------------------+-----------------------------------------------------------------------------------------------------------------------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered                                                                                                                  ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+-----------------------------------------------------------------------------------------------------------------------------+----------------------------+
; 3:1                ; 24 bits   ; 48 LEs        ; 24 LEs               ; 24 LEs                 ; |Equalizer|audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|idn[8]                ;                            ;
; 3:1                ; 5 bits    ; 10 LEs        ; 5 LEs                ; 5 LEs                  ; |Equalizer|audio_unit:inst2|audio_output_register:audio_output_register_1|counter_right[2]                                  ;                            ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; |Equalizer|MMI:inst1|mmi_controller:mmi_controller_1|filter_ten[6]                                                          ;                            ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; |Equalizer|MMI:inst1|mmi_controller:mmi_controller_1|lcd_2[6]                                                               ;                            ;
; 3:1                ; 12 bits   ; 24 LEs        ; 12 LEs               ; 12 LEs                 ; |Equalizer|audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|counter_left[2]       ;                            ;
; 3:1                ; 12 bits   ; 24 LEs        ; 12 LEs               ; 12 LEs                 ; |Equalizer|audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|counter_right[6]      ;                            ;
; 3:1                ; 5 bits    ; 10 LEs        ; 5 LEs                ; 5 LEs                  ; |Equalizer|audio_unit:inst2|audio_output_register:audio_output_register_1|counter_left[2]                                   ;                            ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; |Equalizer|audio_unit:inst2|i2c_master:i2c_master_1|Byte[1]                                                                 ;                            ;
; 4:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; |Equalizer|audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|counter[0] ;                            ;
; 4:1                ; 24 bits   ; 48 LEs        ; 48 LEs               ; 0 LEs                  ; |Equalizer|audio_unit:inst2|audio_input_register:audio_input_register_1|data[5]                                             ;                            ;
; 4:1                ; 23 bits   ; 46 LEs        ; 23 LEs               ; 23 LEs                 ; |Equalizer|audio_unit:inst2|audio_output_register:audio_output_register_1|sdr[14]                                           ;                            ;
; 4:1                ; 23 bits   ; 46 LEs        ; 23 LEs               ; 23 LEs                 ; |Equalizer|audio_unit:inst2|audio_output_register:audio_output_register_1|sdl[13]                                           ;                            ;
; 5:1                ; 13 bits   ; 39 LEs        ; 26 LEs               ; 13 LEs                 ; |Equalizer|MMI:inst1|mmi_controller:mmi_controller_1|filter[1]                                                              ;                            ;
; 6:1                ; 8 bits    ; 32 LEs        ; 8 LEs                ; 24 LEs                 ; |Equalizer|MMI:inst1|mmi_controller:mmi_controller_1|vol_db[0]                                                              ;                            ;
; 6:1                ; 8 bits    ; 32 LEs        ; 8 LEs                ; 24 LEs                 ; |Equalizer|MMI:inst1|mmi_controller:mmi_controller_1|f1_db[0]                                                               ;                            ;
; 6:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; |Equalizer|MMI:inst1|mmi_controller:mmi_controller_1|f2_db[0]                                                               ;                            ;
; 6:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; |Equalizer|MMI:inst1|mmi_controller:mmi_controller_1|f3_db[2]                                                               ;                            ;
; 6:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; |Equalizer|MMI:inst1|mmi_controller:mmi_controller_1|f4_db[3]                                                               ;                            ;
; 6:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; |Equalizer|MMI:inst1|mmi_controller:mmi_controller_1|f5_db[4]                                                               ;                            ;
; 6:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; |Equalizer|MMI:inst1|mmi_controller:mmi_controller_1|f6_db[1]                                                               ;                            ;
; 6:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; |Equalizer|MMI:inst1|mmi_controller:mmi_controller_1|f7_db[3]                                                               ;                            ;
; 6:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; |Equalizer|MMI:inst1|mmi_controller:mmi_controller_1|f8_db[7]                                                               ;                            ;
; 6:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; |Equalizer|MMI:inst1|mmi_controller:mmi_controller_1|f9_db[2]                                                               ;                            ;
; 6:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; |Equalizer|MMI:inst1|mmi_controller:mmi_controller_1|f10_db[2]                                                              ;                            ;
; 6:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; |Equalizer|MMI:inst1|mmi_controller:mmi_controller_1|f11_db[7]                                                              ;                            ;
; 6:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; |Equalizer|MMI:inst1|mmi_controller:mmi_controller_1|f12_db[7]                                                              ;                            ;
; 6:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; |Equalizer|MMI:inst1|mmi_controller:mmi_controller_1|f13_db[7]                                                              ;                            ;
; 6:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; |Equalizer|MMI:inst1|mmi_controller:mmi_controller_1|f14_db[0]                                                              ;                            ;
; 10:1               ; 3 bits    ; 18 LEs        ; 15 LEs               ; 3 LEs                  ; |Equalizer|MMI:inst1|lcd_controller:lcd_controller_1|index[2]                                                               ;                            ;
; 11:1               ; 20 bits   ; 140 LEs       ; 20 LEs               ; 120 LEs                ; |Equalizer|MMI:inst1|lcd_controller:lcd_controller_1|delay[18]                                                              ;                            ;
; 256:1              ; 10 bits   ; 1700 LEs      ; 400 LEs              ; 1300 LEs               ; |Equalizer|MMI:inst1|mmi_controller:mmi_controller_1|lcd_6[0]                                                               ;                            ;
; 128:1              ; 24 bits   ; 2040 LEs      ; 0 LEs                ; 2040 LEs               ; |Equalizer|audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|tmp1[9]    ;                            ;
; 128:1              ; 24 bits   ; 2040 LEs      ; 0 LEs                ; 2040 LEs               ; |Equalizer|audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|tmp2[12]   ;                            ;
; 128:1              ; 24 bits   ; 2040 LEs      ; 0 LEs                ; 2040 LEs               ; |Equalizer|audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|tmp3[5]    ;                            ;
; 256:1              ; 12 bits   ; 2040 LEs      ; 48 LEs               ; 1992 LEs               ; |Equalizer|audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|b[26]      ;                            ;
; 257:1              ; 13 bits   ; 2223 LEs      ; 520 LEs              ; 1703 LEs               ; |Equalizer|MMI:inst1|mmi_controller:mmi_controller_1|db_ten[1]                                                              ;                            ;
; 130:1              ; 24 bits   ; 2064 LEs      ; 24 LEs               ; 2040 LEs               ; |Equalizer|audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|yn[13]     ;                            ;
; 131:1              ; 24 bits   ; 2088 LEs      ; 72 LEs               ; 2016 LEs               ; |Equalizer|audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|a[13]      ;                            ;
; 3:1                ; 24 bits   ; 48 LEs        ; 24 LEs               ; 24 LEs                 ; |Equalizer|audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|idm[1]                ;                            ;
; 16:1               ; 8 bits    ; 80 LEs        ; 80 LEs               ; 0 LEs                  ; |Equalizer|MMI:inst1|mmi_controller:mmi_controller_1|Selector5                                                              ;                            ;
; 16:1               ; 8 bits    ; 80 LEs        ; 80 LEs               ; 0 LEs                  ; |Equalizer|MMI:inst1|mmi_controller:mmi_controller_1|tmp                                                                    ;                            ;
+--------------------+-----------+---------------+----------------------+------------------------+-----------------------------------------------------------------------------------------------------------------------------+----------------------------+


+--------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: clock_generator:inst|altpll0:inst|altpll:altpll_component ;
+-------------------------------+---------------------------+--------------------------------------------+
; Parameter Name                ; Value                     ; Type                                       ;
+-------------------------------+---------------------------+--------------------------------------------+
; OPERATION_MODE                ; NORMAL                    ; Untyped                                    ;
; PLL_TYPE                      ; AUTO                      ; Untyped                                    ;
; LPM_HINT                      ; CBX_MODULE_PREFIX=altpll0 ; Untyped                                    ;
; QUALIFY_CONF_DONE             ; OFF                       ; Untyped                                    ;
; COMPENSATE_CLOCK              ; CLK0                      ; Untyped                                    ;
; SCAN_CHAIN                    ; LONG                      ; Untyped                                    ;
; PRIMARY_CLOCK                 ; INCLK0                    ; Untyped                                    ;
; INCLK0_INPUT_FREQUENCY        ; 20000                     ; Signed Integer                             ;
; INCLK1_INPUT_FREQUENCY        ; 0                         ; Untyped                                    ;
; GATE_LOCK_SIGNAL              ; NO                        ; Untyped                                    ;
; GATE_LOCK_COUNTER             ; 0                         ; Untyped                                    ;
; LOCK_HIGH                     ; 1                         ; Untyped                                    ;
; LOCK_LOW                      ; 1                         ; Untyped                                    ;
; VALID_LOCK_MULTIPLIER         ; 1                         ; Untyped                                    ;
; INVALID_LOCK_MULTIPLIER       ; 5                         ; Untyped                                    ;
; SWITCH_OVER_ON_LOSSCLK        ; OFF                       ; Untyped                                    ;
; SWITCH_OVER_ON_GATED_LOCK     ; OFF                       ; Untyped                                    ;
; ENABLE_SWITCH_OVER_COUNTER    ; OFF                       ; Untyped                                    ;
; SKIP_VCO                      ; OFF                       ; Untyped                                    ;
; SWITCH_OVER_COUNTER           ; 0                         ; Untyped                                    ;
; SWITCH_OVER_TYPE              ; AUTO                      ; Untyped                                    ;
; FEEDBACK_SOURCE               ; EXTCLK0                   ; Untyped                                    ;
; BANDWIDTH                     ; 0                         ; Untyped                                    ;
; BANDWIDTH_TYPE                ; AUTO                      ; Untyped                                    ;
; SPREAD_FREQUENCY              ; 0                         ; Untyped                                    ;
; DOWN_SPREAD                   ; 0                         ; Untyped                                    ;
; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF                       ; Untyped                                    ;
; SELF_RESET_ON_LOSS_LOCK       ; OFF                       ; Untyped                                    ;
; CLK9_MULTIPLY_BY              ; 0                         ; Untyped                                    ;
; CLK8_MULTIPLY_BY              ; 0                         ; Untyped                                    ;
; CLK7_MULTIPLY_BY              ; 0                         ; Untyped                                    ;
; CLK6_MULTIPLY_BY              ; 0                         ; Untyped                                    ;
; CLK5_MULTIPLY_BY              ; 1                         ; Untyped                                    ;
; CLK4_MULTIPLY_BY              ; 1                         ; Untyped                                    ;
; CLK3_MULTIPLY_BY              ; 1                         ; Untyped                                    ;
; CLK2_MULTIPLY_BY              ; 1                         ; Untyped                                    ;
; CLK1_MULTIPLY_BY              ; 1                         ; Signed Integer                             ;
; CLK0_MULTIPLY_BY              ; 1                         ; Signed Integer                             ;
; CLK9_DIVIDE_BY                ; 0                         ; Untyped                                    ;
; CLK8_DIVIDE_BY                ; 0                         ; Untyped                                    ;
; CLK7_DIVIDE_BY                ; 0                         ; Untyped                                    ;
; CLK6_DIVIDE_BY                ; 0                         ; Untyped                                    ;
; CLK5_DIVIDE_BY                ; 1                         ; Untyped                                    ;
; CLK4_DIVIDE_BY                ; 1                         ; Untyped                                    ;
; CLK3_DIVIDE_BY                ; 1                         ; Untyped                                    ;
; CLK2_DIVIDE_BY                ; 1                         ; Untyped                                    ;
; CLK1_DIVIDE_BY                ; 5                         ; Signed Integer                             ;
; CLK0_DIVIDE_BY                ; 1                         ; Signed Integer                             ;
; CLK9_PHASE_SHIFT              ; 0                         ; Untyped                                    ;
; CLK8_PHASE_SHIFT              ; 0                         ; Untyped                                    ;
; CLK7_PHASE_SHIFT              ; 0                         ; Untyped                                    ;
; CLK6_PHASE_SHIFT              ; 0                         ; Untyped                                    ;
; CLK5_PHASE_SHIFT              ; 0                         ; Untyped                                    ;
; CLK4_PHASE_SHIFT              ; 0                         ; Untyped                                    ;
; CLK3_PHASE_SHIFT              ; 0                         ; Untyped                                    ;
; CLK2_PHASE_SHIFT              ; 0                         ; Untyped                                    ;
; CLK1_PHASE_SHIFT              ; 0                         ; Untyped                                    ;
; CLK0_PHASE_SHIFT              ; 0                         ; Untyped                                    ;
; CLK5_TIME_DELAY               ; 0                         ; Untyped                                    ;
; CLK4_TIME_DELAY               ; 0                         ; Untyped                                    ;
; CLK3_TIME_DELAY               ; 0                         ; Untyped                                    ;
; CLK2_TIME_DELAY               ; 0                         ; Untyped                                    ;
; CLK1_TIME_DELAY               ; 0                         ; Untyped                                    ;
; CLK0_TIME_DELAY               ; 0                         ; Untyped                                    ;
; CLK9_DUTY_CYCLE               ; 50                        ; Untyped                                    ;
; CLK8_DUTY_CYCLE               ; 50                        ; Untyped                                    ;
; CLK7_DUTY_CYCLE               ; 50                        ; Untyped                                    ;
; CLK6_DUTY_CYCLE               ; 50                        ; Untyped                                    ;
; CLK5_DUTY_CYCLE               ; 50                        ; Untyped                                    ;
; CLK4_DUTY_CYCLE               ; 50                        ; Untyped                                    ;
; CLK3_DUTY_CYCLE               ; 50                        ; Untyped                                    ;
; CLK2_DUTY_CYCLE               ; 50                        ; Untyped                                    ;
; CLK1_DUTY_CYCLE               ; 50                        ; Signed Integer                             ;
; CLK0_DUTY_CYCLE               ; 50                        ; Signed Integer                             ;
; CLK9_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                                    ;
; CLK8_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                                    ;
; CLK7_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                                    ;
; CLK6_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                                    ;
; CLK5_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                                    ;
; CLK4_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                                    ;
; CLK3_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                                    ;
; CLK2_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                                    ;
; CLK1_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                                    ;
; CLK0_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                                    ;
; CLK9_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                                    ;
; CLK8_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                                    ;
; CLK7_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                                    ;
; CLK6_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                                    ;
; CLK5_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                                    ;
; CLK4_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                                    ;
; CLK3_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                                    ;
; CLK2_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                                    ;
; CLK1_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                                    ;
; CLK0_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                                    ;
; LOCK_WINDOW_UI                ;  0.05                     ; Untyped                                    ;
; LOCK_WINDOW_UI_BITS           ; UNUSED                    ; Untyped                                    ;
; VCO_RANGE_DETECTOR_LOW_BITS   ; UNUSED                    ; Untyped                                    ;
; VCO_RANGE_DETECTOR_HIGH_BITS  ; UNUSED                    ; Untyped                                    ;
; DPA_MULTIPLY_BY               ; 0                         ; Untyped                                    ;
; DPA_DIVIDE_BY                 ; 1                         ; Untyped                                    ;
; DPA_DIVIDER                   ; 0                         ; Untyped                                    ;
; EXTCLK3_MULTIPLY_BY           ; 1                         ; Untyped                                    ;
; EXTCLK2_MULTIPLY_BY           ; 1                         ; Untyped                                    ;
; EXTCLK1_MULTIPLY_BY           ; 1                         ; Untyped                                    ;
; EXTCLK0_MULTIPLY_BY           ; 1                         ; Untyped                                    ;
; EXTCLK3_DIVIDE_BY             ; 1                         ; Untyped                                    ;
; EXTCLK2_DIVIDE_BY             ; 1                         ; Untyped                                    ;
; EXTCLK1_DIVIDE_BY             ; 1                         ; Untyped                                    ;
; EXTCLK0_DIVIDE_BY             ; 1                         ; Untyped                                    ;
; EXTCLK3_PHASE_SHIFT           ; 0                         ; Untyped                                    ;
; EXTCLK2_PHASE_SHIFT           ; 0                         ; Untyped                                    ;
; EXTCLK1_PHASE_SHIFT           ; 0                         ; Untyped                                    ;
; EXTCLK0_PHASE_SHIFT           ; 0                         ; Untyped                                    ;
; EXTCLK3_TIME_DELAY            ; 0                         ; Untyped                                    ;
; EXTCLK2_TIME_DELAY            ; 0                         ; Untyped                                    ;
; EXTCLK1_TIME_DELAY            ; 0                         ; Untyped                                    ;
; EXTCLK0_TIME_DELAY            ; 0                         ; Untyped                                    ;
; EXTCLK3_DUTY_CYCLE            ; 50                        ; Untyped                                    ;
; EXTCLK2_DUTY_CYCLE            ; 50                        ; Untyped                                    ;
; EXTCLK1_DUTY_CYCLE            ; 50                        ; Untyped                                    ;
; EXTCLK0_DUTY_CYCLE            ; 50                        ; Untyped                                    ;
; VCO_MULTIPLY_BY               ; 0                         ; Untyped                                    ;
; VCO_DIVIDE_BY                 ; 0                         ; Untyped                                    ;
; SCLKOUT0_PHASE_SHIFT          ; 0                         ; Untyped                                    ;
; SCLKOUT1_PHASE_SHIFT          ; 0                         ; Untyped                                    ;
; VCO_MIN                       ; 0                         ; Untyped                                    ;
; VCO_MAX                       ; 0                         ; Untyped                                    ;
; VCO_CENTER                    ; 0                         ; Untyped                                    ;
; PFD_MIN                       ; 0                         ; Untyped                                    ;
; PFD_MAX                       ; 0                         ; Untyped                                    ;
; M_INITIAL                     ; 0                         ; Untyped                                    ;
; M                             ; 0                         ; Untyped                                    ;
; N                             ; 1                         ; Untyped                                    ;
; M2                            ; 1                         ; Untyped                                    ;
; N2                            ; 1                         ; Untyped                                    ;
; SS                            ; 1                         ; Untyped                                    ;
; C0_HIGH                       ; 0                         ; Untyped                                    ;
; C1_HIGH                       ; 0                         ; Untyped                                    ;
; C2_HIGH                       ; 0                         ; Untyped                                    ;
; C3_HIGH                       ; 0                         ; Untyped                                    ;
; C4_HIGH                       ; 0                         ; Untyped                                    ;
; C5_HIGH                       ; 0                         ; Untyped                                    ;
; C6_HIGH                       ; 0                         ; Untyped                                    ;
; C7_HIGH                       ; 0                         ; Untyped                                    ;
; C8_HIGH                       ; 0                         ; Untyped                                    ;
; C9_HIGH                       ; 0                         ; Untyped                                    ;
; C0_LOW                        ; 0                         ; Untyped                                    ;
; C1_LOW                        ; 0                         ; Untyped                                    ;
; C2_LOW                        ; 0                         ; Untyped                                    ;
; C3_LOW                        ; 0                         ; Untyped                                    ;
; C4_LOW                        ; 0                         ; Untyped                                    ;
; C5_LOW                        ; 0                         ; Untyped                                    ;
; C6_LOW                        ; 0                         ; Untyped                                    ;
; C7_LOW                        ; 0                         ; Untyped                                    ;
; C8_LOW                        ; 0                         ; Untyped                                    ;
; C9_LOW                        ; 0                         ; Untyped                                    ;
; C0_INITIAL                    ; 0                         ; Untyped                                    ;
; C1_INITIAL                    ; 0                         ; Untyped                                    ;
; C2_INITIAL                    ; 0                         ; Untyped                                    ;
; C3_INITIAL                    ; 0                         ; Untyped                                    ;
; C4_INITIAL                    ; 0                         ; Untyped                                    ;
; C5_INITIAL                    ; 0                         ; Untyped                                    ;
; C6_INITIAL                    ; 0                         ; Untyped                                    ;
; C7_INITIAL                    ; 0                         ; Untyped                                    ;
; C8_INITIAL                    ; 0                         ; Untyped                                    ;
; C9_INITIAL                    ; 0                         ; Untyped                                    ;
; C0_MODE                       ; BYPASS                    ; Untyped                                    ;
; C1_MODE                       ; BYPASS                    ; Untyped                                    ;
; C2_MODE                       ; BYPASS                    ; Untyped                                    ;
; C3_MODE                       ; BYPASS                    ; Untyped                                    ;
; C4_MODE                       ; BYPASS                    ; Untyped                                    ;
; C5_MODE                       ; BYPASS                    ; Untyped                                    ;
; C6_MODE                       ; BYPASS                    ; Untyped                                    ;
; C7_MODE                       ; BYPASS                    ; Untyped                                    ;
; C8_MODE                       ; BYPASS                    ; Untyped                                    ;
; C9_MODE                       ; BYPASS                    ; Untyped                                    ;
; C0_PH                         ; 0                         ; Untyped                                    ;
; C1_PH                         ; 0                         ; Untyped                                    ;
; C2_PH                         ; 0                         ; Untyped                                    ;
; C3_PH                         ; 0                         ; Untyped                                    ;
; C4_PH                         ; 0                         ; Untyped                                    ;
; C5_PH                         ; 0                         ; Untyped                                    ;
; C6_PH                         ; 0                         ; Untyped                                    ;
; C7_PH                         ; 0                         ; Untyped                                    ;
; C8_PH                         ; 0                         ; Untyped                                    ;
; C9_PH                         ; 0                         ; Untyped                                    ;
; L0_HIGH                       ; 1                         ; Untyped                                    ;
; L1_HIGH                       ; 1                         ; Untyped                                    ;
; G0_HIGH                       ; 1                         ; Untyped                                    ;
; G1_HIGH                       ; 1                         ; Untyped                                    ;
; G2_HIGH                       ; 1                         ; Untyped                                    ;
; G3_HIGH                       ; 1                         ; Untyped                                    ;
; E0_HIGH                       ; 1                         ; Untyped                                    ;
; E1_HIGH                       ; 1                         ; Untyped                                    ;
; E2_HIGH                       ; 1                         ; Untyped                                    ;
; E3_HIGH                       ; 1                         ; Untyped                                    ;
; L0_LOW                        ; 1                         ; Untyped                                    ;
; L1_LOW                        ; 1                         ; Untyped                                    ;
; G0_LOW                        ; 1                         ; Untyped                                    ;
; G1_LOW                        ; 1                         ; Untyped                                    ;
; G2_LOW                        ; 1                         ; Untyped                                    ;
; G3_LOW                        ; 1                         ; Untyped                                    ;
; E0_LOW                        ; 1                         ; Untyped                                    ;
; E1_LOW                        ; 1                         ; Untyped                                    ;
; E2_LOW                        ; 1                         ; Untyped                                    ;
; E3_LOW                        ; 1                         ; Untyped                                    ;
; L0_INITIAL                    ; 1                         ; Untyped                                    ;
; L1_INITIAL                    ; 1                         ; Untyped                                    ;
; G0_INITIAL                    ; 1                         ; Untyped                                    ;
; G1_INITIAL                    ; 1                         ; Untyped                                    ;
; G2_INITIAL                    ; 1                         ; Untyped                                    ;
; G3_INITIAL                    ; 1                         ; Untyped                                    ;
; E0_INITIAL                    ; 1                         ; Untyped                                    ;
; E1_INITIAL                    ; 1                         ; Untyped                                    ;
; E2_INITIAL                    ; 1                         ; Untyped                                    ;
; E3_INITIAL                    ; 1                         ; Untyped                                    ;
; L0_MODE                       ; BYPASS                    ; Untyped                                    ;
; L1_MODE                       ; BYPASS                    ; Untyped                                    ;
; G0_MODE                       ; BYPASS                    ; Untyped                                    ;
; G1_MODE                       ; BYPASS                    ; Untyped                                    ;
; G2_MODE                       ; BYPASS                    ; Untyped                                    ;
; G3_MODE                       ; BYPASS                    ; Untyped                                    ;
; E0_MODE                       ; BYPASS                    ; Untyped                                    ;
; E1_MODE                       ; BYPASS                    ; Untyped                                    ;
; E2_MODE                       ; BYPASS                    ; Untyped                                    ;
; E3_MODE                       ; BYPASS                    ; Untyped                                    ;
; L0_PH                         ; 0                         ; Untyped                                    ;
; L1_PH                         ; 0                         ; Untyped                                    ;
; G0_PH                         ; 0                         ; Untyped                                    ;
; G1_PH                         ; 0                         ; Untyped                                    ;
; G2_PH                         ; 0                         ; Untyped                                    ;
; G3_PH                         ; 0                         ; Untyped                                    ;
; E0_PH                         ; 0                         ; Untyped                                    ;
; E1_PH                         ; 0                         ; Untyped                                    ;
; E2_PH                         ; 0                         ; Untyped                                    ;
; E3_PH                         ; 0                         ; Untyped                                    ;
; M_PH                          ; 0                         ; Untyped                                    ;
; C1_USE_CASC_IN                ; OFF                       ; Untyped                                    ;
; C2_USE_CASC_IN                ; OFF                       ; Untyped                                    ;
; C3_USE_CASC_IN                ; OFF                       ; Untyped                                    ;
; C4_USE_CASC_IN                ; OFF                       ; Untyped                                    ;
; C5_USE_CASC_IN                ; OFF                       ; Untyped                                    ;
; C6_USE_CASC_IN                ; OFF                       ; Untyped                                    ;
; C7_USE_CASC_IN                ; OFF                       ; Untyped                                    ;
; C8_USE_CASC_IN                ; OFF                       ; Untyped                                    ;
; C9_USE_CASC_IN                ; OFF                       ; Untyped                                    ;
; CLK0_COUNTER                  ; G0                        ; Untyped                                    ;
; CLK1_COUNTER                  ; G0                        ; Untyped                                    ;
; CLK2_COUNTER                  ; G0                        ; Untyped                                    ;
; CLK3_COUNTER                  ; G0                        ; Untyped                                    ;
; CLK4_COUNTER                  ; G0                        ; Untyped                                    ;
; CLK5_COUNTER                  ; G0                        ; Untyped                                    ;
; CLK6_COUNTER                  ; E0                        ; Untyped                                    ;
; CLK7_COUNTER                  ; E1                        ; Untyped                                    ;
; CLK8_COUNTER                  ; E2                        ; Untyped                                    ;
; CLK9_COUNTER                  ; E3                        ; Untyped                                    ;
; L0_TIME_DELAY                 ; 0                         ; Untyped                                    ;
; L1_TIME_DELAY                 ; 0                         ; Untyped                                    ;
; G0_TIME_DELAY                 ; 0                         ; Untyped                                    ;
; G1_TIME_DELAY                 ; 0                         ; Untyped                                    ;
; G2_TIME_DELAY                 ; 0                         ; Untyped                                    ;
; G3_TIME_DELAY                 ; 0                         ; Untyped                                    ;
; E0_TIME_DELAY                 ; 0                         ; Untyped                                    ;
; E1_TIME_DELAY                 ; 0                         ; Untyped                                    ;
; E2_TIME_DELAY                 ; 0                         ; Untyped                                    ;
; E3_TIME_DELAY                 ; 0                         ; Untyped                                    ;
; M_TIME_DELAY                  ; 0                         ; Untyped                                    ;
; N_TIME_DELAY                  ; 0                         ; Untyped                                    ;
; EXTCLK3_COUNTER               ; E3                        ; Untyped                                    ;
; EXTCLK2_COUNTER               ; E2                        ; Untyped                                    ;
; EXTCLK1_COUNTER               ; E1                        ; Untyped                                    ;
; EXTCLK0_COUNTER               ; E0                        ; Untyped                                    ;
; ENABLE0_COUNTER               ; L0                        ; Untyped                                    ;
; ENABLE1_COUNTER               ; L0                        ; Untyped                                    ;
; CHARGE_PUMP_CURRENT           ; 2                         ; Untyped                                    ;
; LOOP_FILTER_R                 ;  1.000000                 ; Untyped                                    ;
; LOOP_FILTER_C                 ; 5                         ; Untyped                                    ;
; CHARGE_PUMP_CURRENT_BITS      ; 9999                      ; Untyped                                    ;
; LOOP_FILTER_R_BITS            ; 9999                      ; Untyped                                    ;
; LOOP_FILTER_C_BITS            ; 9999                      ; Untyped                                    ;
; VCO_POST_SCALE                ; 0                         ; Untyped                                    ;
; CLK2_OUTPUT_FREQUENCY         ; 0                         ; Untyped                                    ;
; CLK1_OUTPUT_FREQUENCY         ; 0                         ; Untyped                                    ;
; CLK0_OUTPUT_FREQUENCY         ; 0                         ; Untyped                                    ;
; INTENDED_DEVICE_FAMILY        ; Cyclone II                ; Untyped                                    ;
; PORT_CLKENA0                  ; PORT_UNUSED               ; Untyped                                    ;
; PORT_CLKENA1                  ; PORT_UNUSED               ; Untyped                                    ;
; PORT_CLKENA2                  ; PORT_UNUSED               ; Untyped                                    ;
; PORT_CLKENA3                  ; PORT_UNUSED               ; Untyped                                    ;
; PORT_CLKENA4                  ; PORT_UNUSED               ; Untyped                                    ;
; PORT_CLKENA5                  ; PORT_UNUSED               ; Untyped                                    ;
; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY         ; Untyped                                    ;
; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY         ; Untyped                                    ;
; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY         ; Untyped                                    ;
; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY         ; Untyped                                    ;
; PORT_EXTCLK0                  ; PORT_UNUSED               ; Untyped                                    ;
; PORT_EXTCLK1                  ; PORT_UNUSED               ; Untyped                                    ;
; PORT_EXTCLK2                  ; PORT_UNUSED               ; Untyped                                    ;
; PORT_EXTCLK3                  ; PORT_UNUSED               ; Untyped                                    ;
; PORT_CLKBAD0                  ; PORT_UNUSED               ; Untyped                                    ;
; PORT_CLKBAD1                  ; PORT_UNUSED               ; Untyped                                    ;
; PORT_CLK0                     ; PORT_USED                 ; Untyped                                    ;
; PORT_CLK1                     ; PORT_USED                 ; Untyped                                    ;
; PORT_CLK2                     ; PORT_UNUSED               ; Untyped                                    ;
; PORT_CLK3                     ; PORT_UNUSED               ; Untyped                                    ;
; PORT_CLK4                     ; PORT_UNUSED               ; Untyped                                    ;
; PORT_CLK5                     ; PORT_UNUSED               ; Untyped                                    ;
; PORT_CLK6                     ; PORT_UNUSED               ; Untyped                                    ;
; PORT_CLK7                     ; PORT_UNUSED               ; Untyped                                    ;
; PORT_CLK8                     ; PORT_UNUSED               ; Untyped                                    ;
; PORT_CLK9                     ; PORT_UNUSED               ; Untyped                                    ;
; PORT_SCANDATA                 ; PORT_UNUSED               ; Untyped                                    ;
; PORT_SCANDATAOUT              ; PORT_UNUSED               ; Untyped                                    ;
; PORT_SCANDONE                 ; PORT_UNUSED               ; Untyped                                    ;
; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY         ; Untyped                                    ;
; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY         ; Untyped                                    ;
; PORT_ACTIVECLOCK              ; PORT_UNUSED               ; Untyped                                    ;
; PORT_CLKLOSS                  ; PORT_UNUSED               ; Untyped                                    ;
; PORT_INCLK1                   ; PORT_UNUSED               ; Untyped                                    ;
; PORT_INCLK0                   ; PORT_USED                 ; Untyped                                    ;
; PORT_FBIN                     ; PORT_UNUSED               ; Untyped                                    ;
; PORT_PLLENA                   ; PORT_UNUSED               ; Untyped                                    ;
; PORT_CLKSWITCH                ; PORT_UNUSED               ; Untyped                                    ;
; PORT_ARESET                   ; PORT_UNUSED               ; Untyped                                    ;
; PORT_PFDENA                   ; PORT_UNUSED               ; Untyped                                    ;
; PORT_SCANCLK                  ; PORT_UNUSED               ; Untyped                                    ;
; PORT_SCANACLR                 ; PORT_UNUSED               ; Untyped                                    ;
; PORT_SCANREAD                 ; PORT_UNUSED               ; Untyped                                    ;
; PORT_SCANWRITE                ; PORT_UNUSED               ; Untyped                                    ;
; PORT_ENABLE0                  ; PORT_CONNECTIVITY         ; Untyped                                    ;
; PORT_ENABLE1                  ; PORT_CONNECTIVITY         ; Untyped                                    ;
; PORT_LOCKED                   ; PORT_UNUSED               ; Untyped                                    ;
; PORT_CONFIGUPDATE             ; PORT_UNUSED               ; Untyped                                    ;
; PORT_FBOUT                    ; PORT_CONNECTIVITY         ; Untyped                                    ;
; PORT_PHASEDONE                ; PORT_UNUSED               ; Untyped                                    ;
; PORT_PHASESTEP                ; PORT_UNUSED               ; Untyped                                    ;
; PORT_PHASEUPDOWN              ; PORT_UNUSED               ; Untyped                                    ;
; PORT_SCANCLKENA               ; PORT_UNUSED               ; Untyped                                    ;
; PORT_PHASECOUNTERSELECT       ; PORT_UNUSED               ; Untyped                                    ;
; PORT_VCOOVERRANGE             ; PORT_CONNECTIVITY         ; Untyped                                    ;
; PORT_VCOUNDERRANGE            ; PORT_CONNECTIVITY         ; Untyped                                    ;
; M_TEST_SOURCE                 ; 5                         ; Untyped                                    ;
; C0_TEST_SOURCE                ; 5                         ; Untyped                                    ;
; C1_TEST_SOURCE                ; 5                         ; Untyped                                    ;
; C2_TEST_SOURCE                ; 5                         ; Untyped                                    ;
; C3_TEST_SOURCE                ; 5                         ; Untyped                                    ;
; C4_TEST_SOURCE                ; 5                         ; Untyped                                    ;
; C5_TEST_SOURCE                ; 5                         ; Untyped                                    ;
; C6_TEST_SOURCE                ; 5                         ; Untyped                                    ;
; C7_TEST_SOURCE                ; 5                         ; Untyped                                    ;
; C8_TEST_SOURCE                ; 5                         ; Untyped                                    ;
; C9_TEST_SOURCE                ; 5                         ; Untyped                                    ;
; CBXI_PARAMETER                ; NOTHING                   ; Untyped                                    ;
; VCO_FREQUENCY_CONTROL         ; AUTO                      ; Untyped                                    ;
; VCO_PHASE_SHIFT_STEP          ; 0                         ; Untyped                                    ;
; WIDTH_CLOCK                   ; 6                         ; Untyped                                    ;
; WIDTH_PHASECOUNTERSELECT      ; 4                         ; Untyped                                    ;
; USING_FBMIMICBIDIR_PORT       ; OFF                       ; Untyped                                    ;
; DEVICE_FAMILY                 ; Cyclone II                ; Untyped                                    ;
; SCAN_CHAIN_MIF_FILE           ; UNUSED                    ; Untyped                                    ;
; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF                       ; Untyped                                    ;
; AUTO_CARRY_CHAINS             ; ON                        ; AUTO_CARRY                                 ;
; IGNORE_CARRY_BUFFERS          ; OFF                       ; IGNORE_CARRY                               ;
; AUTO_CASCADE_CHAINS           ; ON                        ; AUTO_CASCADE                               ;
; IGNORE_CASCADE_BUFFERS        ; OFF                       ; IGNORE_CASCADE                             ;
+-------------------------------+---------------------------+--------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: clock_generator:inst|altpll1:inst1|altpll:altpll_component ;
+-------------------------------+---------------------------+---------------------------------------------+
; Parameter Name                ; Value                     ; Type                                        ;
+-------------------------------+---------------------------+---------------------------------------------+
; OPERATION_MODE                ; NORMAL                    ; Untyped                                     ;
; PLL_TYPE                      ; AUTO                      ; Untyped                                     ;
; LPM_HINT                      ; CBX_MODULE_PREFIX=altpll1 ; Untyped                                     ;
; QUALIFY_CONF_DONE             ; OFF                       ; Untyped                                     ;
; COMPENSATE_CLOCK              ; CLK0                      ; Untyped                                     ;
; SCAN_CHAIN                    ; LONG                      ; Untyped                                     ;
; PRIMARY_CLOCK                 ; INCLK0                    ; Untyped                                     ;
; INCLK0_INPUT_FREQUENCY        ; 37037                     ; Signed Integer                              ;
; INCLK1_INPUT_FREQUENCY        ; 0                         ; Untyped                                     ;
; GATE_LOCK_SIGNAL              ; NO                        ; Untyped                                     ;
; GATE_LOCK_COUNTER             ; 0                         ; Untyped                                     ;
; LOCK_HIGH                     ; 1                         ; Untyped                                     ;
; LOCK_LOW                      ; 1                         ; Untyped                                     ;
; VALID_LOCK_MULTIPLIER         ; 1                         ; Untyped                                     ;
; INVALID_LOCK_MULTIPLIER       ; 5                         ; Untyped                                     ;
; SWITCH_OVER_ON_LOSSCLK        ; OFF                       ; Untyped                                     ;
; SWITCH_OVER_ON_GATED_LOCK     ; OFF                       ; Untyped                                     ;
; ENABLE_SWITCH_OVER_COUNTER    ; OFF                       ; Untyped                                     ;
; SKIP_VCO                      ; OFF                       ; Untyped                                     ;
; SWITCH_OVER_COUNTER           ; 0                         ; Untyped                                     ;
; SWITCH_OVER_TYPE              ; AUTO                      ; Untyped                                     ;
; FEEDBACK_SOURCE               ; EXTCLK0                   ; Untyped                                     ;
; BANDWIDTH                     ; 0                         ; Untyped                                     ;
; BANDWIDTH_TYPE                ; AUTO                      ; Untyped                                     ;
; SPREAD_FREQUENCY              ; 0                         ; Untyped                                     ;
; DOWN_SPREAD                   ; 0                         ; Untyped                                     ;
; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF                       ; Untyped                                     ;
; SELF_RESET_ON_LOSS_LOCK       ; OFF                       ; Untyped                                     ;
; CLK9_MULTIPLY_BY              ; 0                         ; Untyped                                     ;
; CLK8_MULTIPLY_BY              ; 0                         ; Untyped                                     ;
; CLK7_MULTIPLY_BY              ; 0                         ; Untyped                                     ;
; CLK6_MULTIPLY_BY              ; 0                         ; Untyped                                     ;
; CLK5_MULTIPLY_BY              ; 1                         ; Untyped                                     ;
; CLK4_MULTIPLY_BY              ; 1                         ; Untyped                                     ;
; CLK3_MULTIPLY_BY              ; 1                         ; Untyped                                     ;
; CLK2_MULTIPLY_BY              ; 1                         ; Untyped                                     ;
; CLK1_MULTIPLY_BY              ; 4                         ; Signed Integer                              ;
; CLK0_MULTIPLY_BY              ; 1                         ; Signed Integer                              ;
; CLK9_DIVIDE_BY                ; 0                         ; Untyped                                     ;
; CLK8_DIVIDE_BY                ; 0                         ; Untyped                                     ;
; CLK7_DIVIDE_BY                ; 0                         ; Untyped                                     ;
; CLK6_DIVIDE_BY                ; 0                         ; Untyped                                     ;
; CLK5_DIVIDE_BY                ; 1                         ; Untyped                                     ;
; CLK4_DIVIDE_BY                ; 1                         ; Untyped                                     ;
; CLK3_DIVIDE_BY                ; 1                         ; Untyped                                     ;
; CLK2_DIVIDE_BY                ; 1                         ; Untyped                                     ;
; CLK1_DIVIDE_BY                ; 9                         ; Signed Integer                              ;
; CLK0_DIVIDE_BY                ; 1                         ; Signed Integer                              ;
; CLK9_PHASE_SHIFT              ; 0                         ; Untyped                                     ;
; CLK8_PHASE_SHIFT              ; 0                         ; Untyped                                     ;
; CLK7_PHASE_SHIFT              ; 0                         ; Untyped                                     ;
; CLK6_PHASE_SHIFT              ; 0                         ; Untyped                                     ;
; CLK5_PHASE_SHIFT              ; 0                         ; Untyped                                     ;
; CLK4_PHASE_SHIFT              ; 0                         ; Untyped                                     ;
; CLK3_PHASE_SHIFT              ; 0                         ; Untyped                                     ;
; CLK2_PHASE_SHIFT              ; 0                         ; Untyped                                     ;
; CLK1_PHASE_SHIFT              ; 0                         ; Untyped                                     ;
; CLK0_PHASE_SHIFT              ; 0                         ; Untyped                                     ;
; CLK5_TIME_DELAY               ; 0                         ; Untyped                                     ;
; CLK4_TIME_DELAY               ; 0                         ; Untyped                                     ;
; CLK3_TIME_DELAY               ; 0                         ; Untyped                                     ;
; CLK2_TIME_DELAY               ; 0                         ; Untyped                                     ;
; CLK1_TIME_DELAY               ; 0                         ; Untyped                                     ;
; CLK0_TIME_DELAY               ; 0                         ; Untyped                                     ;
; CLK9_DUTY_CYCLE               ; 50                        ; Untyped                                     ;
; CLK8_DUTY_CYCLE               ; 50                        ; Untyped                                     ;
; CLK7_DUTY_CYCLE               ; 50                        ; Untyped                                     ;
; CLK6_DUTY_CYCLE               ; 50                        ; Untyped                                     ;
; CLK5_DUTY_CYCLE               ; 50                        ; Untyped                                     ;
; CLK4_DUTY_CYCLE               ; 50                        ; Untyped                                     ;
; CLK3_DUTY_CYCLE               ; 50                        ; Untyped                                     ;
; CLK2_DUTY_CYCLE               ; 50                        ; Untyped                                     ;
; CLK1_DUTY_CYCLE               ; 50                        ; Signed Integer                              ;
; CLK0_DUTY_CYCLE               ; 50                        ; Signed Integer                              ;
; CLK9_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                                     ;
; CLK8_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                                     ;
; CLK7_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                                     ;
; CLK6_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                                     ;
; CLK5_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                                     ;
; CLK4_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                                     ;
; CLK3_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                                     ;
; CLK2_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                                     ;
; CLK1_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                                     ;
; CLK0_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                                     ;
; CLK9_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                                     ;
; CLK8_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                                     ;
; CLK7_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                                     ;
; CLK6_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                                     ;
; CLK5_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                                     ;
; CLK4_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                                     ;
; CLK3_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                                     ;
; CLK2_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                                     ;
; CLK1_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                                     ;
; CLK0_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                                     ;
; LOCK_WINDOW_UI                ;  0.05                     ; Untyped                                     ;
; LOCK_WINDOW_UI_BITS           ; UNUSED                    ; Untyped                                     ;
; VCO_RANGE_DETECTOR_LOW_BITS   ; UNUSED                    ; Untyped                                     ;
; VCO_RANGE_DETECTOR_HIGH_BITS  ; UNUSED                    ; Untyped                                     ;
; DPA_MULTIPLY_BY               ; 0                         ; Untyped                                     ;
; DPA_DIVIDE_BY                 ; 1                         ; Untyped                                     ;
; DPA_DIVIDER                   ; 0                         ; Untyped                                     ;
; EXTCLK3_MULTIPLY_BY           ; 1                         ; Untyped                                     ;
; EXTCLK2_MULTIPLY_BY           ; 1                         ; Untyped                                     ;
; EXTCLK1_MULTIPLY_BY           ; 1                         ; Untyped                                     ;
; EXTCLK0_MULTIPLY_BY           ; 1                         ; Untyped                                     ;
; EXTCLK3_DIVIDE_BY             ; 1                         ; Untyped                                     ;
; EXTCLK2_DIVIDE_BY             ; 1                         ; Untyped                                     ;
; EXTCLK1_DIVIDE_BY             ; 1                         ; Untyped                                     ;
; EXTCLK0_DIVIDE_BY             ; 1                         ; Untyped                                     ;
; EXTCLK3_PHASE_SHIFT           ; 0                         ; Untyped                                     ;
; EXTCLK2_PHASE_SHIFT           ; 0                         ; Untyped                                     ;
; EXTCLK1_PHASE_SHIFT           ; 0                         ; Untyped                                     ;
; EXTCLK0_PHASE_SHIFT           ; 0                         ; Untyped                                     ;
; EXTCLK3_TIME_DELAY            ; 0                         ; Untyped                                     ;
; EXTCLK2_TIME_DELAY            ; 0                         ; Untyped                                     ;
; EXTCLK1_TIME_DELAY            ; 0                         ; Untyped                                     ;
; EXTCLK0_TIME_DELAY            ; 0                         ; Untyped                                     ;
; EXTCLK3_DUTY_CYCLE            ; 50                        ; Untyped                                     ;
; EXTCLK2_DUTY_CYCLE            ; 50                        ; Untyped                                     ;
; EXTCLK1_DUTY_CYCLE            ; 50                        ; Untyped                                     ;
; EXTCLK0_DUTY_CYCLE            ; 50                        ; Untyped                                     ;
; VCO_MULTIPLY_BY               ; 0                         ; Untyped                                     ;
; VCO_DIVIDE_BY                 ; 0                         ; Untyped                                     ;
; SCLKOUT0_PHASE_SHIFT          ; 0                         ; Untyped                                     ;
; SCLKOUT1_PHASE_SHIFT          ; 0                         ; Untyped                                     ;
; VCO_MIN                       ; 0                         ; Untyped                                     ;
; VCO_MAX                       ; 0                         ; Untyped                                     ;
; VCO_CENTER                    ; 0                         ; Untyped                                     ;
; PFD_MIN                       ; 0                         ; Untyped                                     ;
; PFD_MAX                       ; 0                         ; Untyped                                     ;
; M_INITIAL                     ; 0                         ; Untyped                                     ;
; M                             ; 0                         ; Untyped                                     ;
; N                             ; 1                         ; Untyped                                     ;
; M2                            ; 1                         ; Untyped                                     ;
; N2                            ; 1                         ; Untyped                                     ;
; SS                            ; 1                         ; Untyped                                     ;
; C0_HIGH                       ; 0                         ; Untyped                                     ;
; C1_HIGH                       ; 0                         ; Untyped                                     ;
; C2_HIGH                       ; 0                         ; Untyped                                     ;
; C3_HIGH                       ; 0                         ; Untyped                                     ;
; C4_HIGH                       ; 0                         ; Untyped                                     ;
; C5_HIGH                       ; 0                         ; Untyped                                     ;
; C6_HIGH                       ; 0                         ; Untyped                                     ;
; C7_HIGH                       ; 0                         ; Untyped                                     ;
; C8_HIGH                       ; 0                         ; Untyped                                     ;
; C9_HIGH                       ; 0                         ; Untyped                                     ;
; C0_LOW                        ; 0                         ; Untyped                                     ;
; C1_LOW                        ; 0                         ; Untyped                                     ;
; C2_LOW                        ; 0                         ; Untyped                                     ;
; C3_LOW                        ; 0                         ; Untyped                                     ;
; C4_LOW                        ; 0                         ; Untyped                                     ;
; C5_LOW                        ; 0                         ; Untyped                                     ;
; C6_LOW                        ; 0                         ; Untyped                                     ;
; C7_LOW                        ; 0                         ; Untyped                                     ;
; C8_LOW                        ; 0                         ; Untyped                                     ;
; C9_LOW                        ; 0                         ; Untyped                                     ;
; C0_INITIAL                    ; 0                         ; Untyped                                     ;
; C1_INITIAL                    ; 0                         ; Untyped                                     ;
; C2_INITIAL                    ; 0                         ; Untyped                                     ;
; C3_INITIAL                    ; 0                         ; Untyped                                     ;
; C4_INITIAL                    ; 0                         ; Untyped                                     ;
; C5_INITIAL                    ; 0                         ; Untyped                                     ;
; C6_INITIAL                    ; 0                         ; Untyped                                     ;
; C7_INITIAL                    ; 0                         ; Untyped                                     ;
; C8_INITIAL                    ; 0                         ; Untyped                                     ;
; C9_INITIAL                    ; 0                         ; Untyped                                     ;
; C0_MODE                       ; BYPASS                    ; Untyped                                     ;
; C1_MODE                       ; BYPASS                    ; Untyped                                     ;
; C2_MODE                       ; BYPASS                    ; Untyped                                     ;
; C3_MODE                       ; BYPASS                    ; Untyped                                     ;
; C4_MODE                       ; BYPASS                    ; Untyped                                     ;
; C5_MODE                       ; BYPASS                    ; Untyped                                     ;
; C6_MODE                       ; BYPASS                    ; Untyped                                     ;
; C7_MODE                       ; BYPASS                    ; Untyped                                     ;
; C8_MODE                       ; BYPASS                    ; Untyped                                     ;
; C9_MODE                       ; BYPASS                    ; Untyped                                     ;
; C0_PH                         ; 0                         ; Untyped                                     ;
; C1_PH                         ; 0                         ; Untyped                                     ;
; C2_PH                         ; 0                         ; Untyped                                     ;
; C3_PH                         ; 0                         ; Untyped                                     ;
; C4_PH                         ; 0                         ; Untyped                                     ;
; C5_PH                         ; 0                         ; Untyped                                     ;
; C6_PH                         ; 0                         ; Untyped                                     ;
; C7_PH                         ; 0                         ; Untyped                                     ;
; C8_PH                         ; 0                         ; Untyped                                     ;
; C9_PH                         ; 0                         ; Untyped                                     ;
; L0_HIGH                       ; 1                         ; Untyped                                     ;
; L1_HIGH                       ; 1                         ; Untyped                                     ;
; G0_HIGH                       ; 1                         ; Untyped                                     ;
; G1_HIGH                       ; 1                         ; Untyped                                     ;
; G2_HIGH                       ; 1                         ; Untyped                                     ;
; G3_HIGH                       ; 1                         ; Untyped                                     ;
; E0_HIGH                       ; 1                         ; Untyped                                     ;
; E1_HIGH                       ; 1                         ; Untyped                                     ;
; E2_HIGH                       ; 1                         ; Untyped                                     ;
; E3_HIGH                       ; 1                         ; Untyped                                     ;
; L0_LOW                        ; 1                         ; Untyped                                     ;
; L1_LOW                        ; 1                         ; Untyped                                     ;
; G0_LOW                        ; 1                         ; Untyped                                     ;
; G1_LOW                        ; 1                         ; Untyped                                     ;
; G2_LOW                        ; 1                         ; Untyped                                     ;
; G3_LOW                        ; 1                         ; Untyped                                     ;
; E0_LOW                        ; 1                         ; Untyped                                     ;
; E1_LOW                        ; 1                         ; Untyped                                     ;
; E2_LOW                        ; 1                         ; Untyped                                     ;
; E3_LOW                        ; 1                         ; Untyped                                     ;
; L0_INITIAL                    ; 1                         ; Untyped                                     ;
; L1_INITIAL                    ; 1                         ; Untyped                                     ;
; G0_INITIAL                    ; 1                         ; Untyped                                     ;
; G1_INITIAL                    ; 1                         ; Untyped                                     ;
; G2_INITIAL                    ; 1                         ; Untyped                                     ;
; G3_INITIAL                    ; 1                         ; Untyped                                     ;
; E0_INITIAL                    ; 1                         ; Untyped                                     ;
; E1_INITIAL                    ; 1                         ; Untyped                                     ;
; E2_INITIAL                    ; 1                         ; Untyped                                     ;
; E3_INITIAL                    ; 1                         ; Untyped                                     ;
; L0_MODE                       ; BYPASS                    ; Untyped                                     ;
; L1_MODE                       ; BYPASS                    ; Untyped                                     ;
; G0_MODE                       ; BYPASS                    ; Untyped                                     ;
; G1_MODE                       ; BYPASS                    ; Untyped                                     ;
; G2_MODE                       ; BYPASS                    ; Untyped                                     ;
; G3_MODE                       ; BYPASS                    ; Untyped                                     ;
; E0_MODE                       ; BYPASS                    ; Untyped                                     ;
; E1_MODE                       ; BYPASS                    ; Untyped                                     ;
; E2_MODE                       ; BYPASS                    ; Untyped                                     ;
; E3_MODE                       ; BYPASS                    ; Untyped                                     ;
; L0_PH                         ; 0                         ; Untyped                                     ;
; L1_PH                         ; 0                         ; Untyped                                     ;
; G0_PH                         ; 0                         ; Untyped                                     ;
; G1_PH                         ; 0                         ; Untyped                                     ;
; G2_PH                         ; 0                         ; Untyped                                     ;
; G3_PH                         ; 0                         ; Untyped                                     ;
; E0_PH                         ; 0                         ; Untyped                                     ;
; E1_PH                         ; 0                         ; Untyped                                     ;
; E2_PH                         ; 0                         ; Untyped                                     ;
; E3_PH                         ; 0                         ; Untyped                                     ;
; M_PH                          ; 0                         ; Untyped                                     ;
; C1_USE_CASC_IN                ; OFF                       ; Untyped                                     ;
; C2_USE_CASC_IN                ; OFF                       ; Untyped                                     ;
; C3_USE_CASC_IN                ; OFF                       ; Untyped                                     ;
; C4_USE_CASC_IN                ; OFF                       ; Untyped                                     ;
; C5_USE_CASC_IN                ; OFF                       ; Untyped                                     ;
; C6_USE_CASC_IN                ; OFF                       ; Untyped                                     ;
; C7_USE_CASC_IN                ; OFF                       ; Untyped                                     ;
; C8_USE_CASC_IN                ; OFF                       ; Untyped                                     ;
; C9_USE_CASC_IN                ; OFF                       ; Untyped                                     ;
; CLK0_COUNTER                  ; G0                        ; Untyped                                     ;
; CLK1_COUNTER                  ; G0                        ; Untyped                                     ;
; CLK2_COUNTER                  ; G0                        ; Untyped                                     ;
; CLK3_COUNTER                  ; G0                        ; Untyped                                     ;
; CLK4_COUNTER                  ; G0                        ; Untyped                                     ;
; CLK5_COUNTER                  ; G0                        ; Untyped                                     ;
; CLK6_COUNTER                  ; E0                        ; Untyped                                     ;
; CLK7_COUNTER                  ; E1                        ; Untyped                                     ;
; CLK8_COUNTER                  ; E2                        ; Untyped                                     ;
; CLK9_COUNTER                  ; E3                        ; Untyped                                     ;
; L0_TIME_DELAY                 ; 0                         ; Untyped                                     ;
; L1_TIME_DELAY                 ; 0                         ; Untyped                                     ;
; G0_TIME_DELAY                 ; 0                         ; Untyped                                     ;
; G1_TIME_DELAY                 ; 0                         ; Untyped                                     ;
; G2_TIME_DELAY                 ; 0                         ; Untyped                                     ;
; G3_TIME_DELAY                 ; 0                         ; Untyped                                     ;
; E0_TIME_DELAY                 ; 0                         ; Untyped                                     ;
; E1_TIME_DELAY                 ; 0                         ; Untyped                                     ;
; E2_TIME_DELAY                 ; 0                         ; Untyped                                     ;
; E3_TIME_DELAY                 ; 0                         ; Untyped                                     ;
; M_TIME_DELAY                  ; 0                         ; Untyped                                     ;
; N_TIME_DELAY                  ; 0                         ; Untyped                                     ;
; EXTCLK3_COUNTER               ; E3                        ; Untyped                                     ;
; EXTCLK2_COUNTER               ; E2                        ; Untyped                                     ;
; EXTCLK1_COUNTER               ; E1                        ; Untyped                                     ;
; EXTCLK0_COUNTER               ; E0                        ; Untyped                                     ;
; ENABLE0_COUNTER               ; L0                        ; Untyped                                     ;
; ENABLE1_COUNTER               ; L0                        ; Untyped                                     ;
; CHARGE_PUMP_CURRENT           ; 2                         ; Untyped                                     ;
; LOOP_FILTER_R                 ;  1.000000                 ; Untyped                                     ;
; LOOP_FILTER_C                 ; 5                         ; Untyped                                     ;
; CHARGE_PUMP_CURRENT_BITS      ; 9999                      ; Untyped                                     ;
; LOOP_FILTER_R_BITS            ; 9999                      ; Untyped                                     ;
; LOOP_FILTER_C_BITS            ; 9999                      ; Untyped                                     ;
; VCO_POST_SCALE                ; 0                         ; Untyped                                     ;
; CLK2_OUTPUT_FREQUENCY         ; 0                         ; Untyped                                     ;
; CLK1_OUTPUT_FREQUENCY         ; 0                         ; Untyped                                     ;
; CLK0_OUTPUT_FREQUENCY         ; 0                         ; Untyped                                     ;
; INTENDED_DEVICE_FAMILY        ; Cyclone II                ; Untyped                                     ;
; PORT_CLKENA0                  ; PORT_UNUSED               ; Untyped                                     ;
; PORT_CLKENA1                  ; PORT_UNUSED               ; Untyped                                     ;
; PORT_CLKENA2                  ; PORT_UNUSED               ; Untyped                                     ;
; PORT_CLKENA3                  ; PORT_UNUSED               ; Untyped                                     ;
; PORT_CLKENA4                  ; PORT_UNUSED               ; Untyped                                     ;
; PORT_CLKENA5                  ; PORT_UNUSED               ; Untyped                                     ;
; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY         ; Untyped                                     ;
; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY         ; Untyped                                     ;
; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY         ; Untyped                                     ;
; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY         ; Untyped                                     ;
; PORT_EXTCLK0                  ; PORT_UNUSED               ; Untyped                                     ;
; PORT_EXTCLK1                  ; PORT_UNUSED               ; Untyped                                     ;
; PORT_EXTCLK2                  ; PORT_UNUSED               ; Untyped                                     ;
; PORT_EXTCLK3                  ; PORT_UNUSED               ; Untyped                                     ;
; PORT_CLKBAD0                  ; PORT_UNUSED               ; Untyped                                     ;
; PORT_CLKBAD1                  ; PORT_UNUSED               ; Untyped                                     ;
; PORT_CLK0                     ; PORT_USED                 ; Untyped                                     ;
; PORT_CLK1                     ; PORT_USED                 ; Untyped                                     ;
; PORT_CLK2                     ; PORT_UNUSED               ; Untyped                                     ;
; PORT_CLK3                     ; PORT_UNUSED               ; Untyped                                     ;
; PORT_CLK4                     ; PORT_UNUSED               ; Untyped                                     ;
; PORT_CLK5                     ; PORT_UNUSED               ; Untyped                                     ;
; PORT_CLK6                     ; PORT_UNUSED               ; Untyped                                     ;
; PORT_CLK7                     ; PORT_UNUSED               ; Untyped                                     ;
; PORT_CLK8                     ; PORT_UNUSED               ; Untyped                                     ;
; PORT_CLK9                     ; PORT_UNUSED               ; Untyped                                     ;
; PORT_SCANDATA                 ; PORT_UNUSED               ; Untyped                                     ;
; PORT_SCANDATAOUT              ; PORT_UNUSED               ; Untyped                                     ;
; PORT_SCANDONE                 ; PORT_UNUSED               ; Untyped                                     ;
; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY         ; Untyped                                     ;
; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY         ; Untyped                                     ;
; PORT_ACTIVECLOCK              ; PORT_UNUSED               ; Untyped                                     ;
; PORT_CLKLOSS                  ; PORT_UNUSED               ; Untyped                                     ;
; PORT_INCLK1                   ; PORT_UNUSED               ; Untyped                                     ;
; PORT_INCLK0                   ; PORT_USED                 ; Untyped                                     ;
; PORT_FBIN                     ; PORT_UNUSED               ; Untyped                                     ;
; PORT_PLLENA                   ; PORT_UNUSED               ; Untyped                                     ;
; PORT_CLKSWITCH                ; PORT_UNUSED               ; Untyped                                     ;
; PORT_ARESET                   ; PORT_UNUSED               ; Untyped                                     ;
; PORT_PFDENA                   ; PORT_UNUSED               ; Untyped                                     ;
; PORT_SCANCLK                  ; PORT_UNUSED               ; Untyped                                     ;
; PORT_SCANACLR                 ; PORT_UNUSED               ; Untyped                                     ;
; PORT_SCANREAD                 ; PORT_UNUSED               ; Untyped                                     ;
; PORT_SCANWRITE                ; PORT_UNUSED               ; Untyped                                     ;
; PORT_ENABLE0                  ; PORT_CONNECTIVITY         ; Untyped                                     ;
; PORT_ENABLE1                  ; PORT_CONNECTIVITY         ; Untyped                                     ;
; PORT_LOCKED                   ; PORT_UNUSED               ; Untyped                                     ;
; PORT_CONFIGUPDATE             ; PORT_UNUSED               ; Untyped                                     ;
; PORT_FBOUT                    ; PORT_CONNECTIVITY         ; Untyped                                     ;
; PORT_PHASEDONE                ; PORT_UNUSED               ; Untyped                                     ;
; PORT_PHASESTEP                ; PORT_UNUSED               ; Untyped                                     ;
; PORT_PHASEUPDOWN              ; PORT_UNUSED               ; Untyped                                     ;
; PORT_SCANCLKENA               ; PORT_UNUSED               ; Untyped                                     ;
; PORT_PHASECOUNTERSELECT       ; PORT_UNUSED               ; Untyped                                     ;
; PORT_VCOOVERRANGE             ; PORT_CONNECTIVITY         ; Untyped                                     ;
; PORT_VCOUNDERRANGE            ; PORT_CONNECTIVITY         ; Untyped                                     ;
; M_TEST_SOURCE                 ; 5                         ; Untyped                                     ;
; C0_TEST_SOURCE                ; 5                         ; Untyped                                     ;
; C1_TEST_SOURCE                ; 5                         ; Untyped                                     ;
; C2_TEST_SOURCE                ; 5                         ; Untyped                                     ;
; C3_TEST_SOURCE                ; 5                         ; Untyped                                     ;
; C4_TEST_SOURCE                ; 5                         ; Untyped                                     ;
; C5_TEST_SOURCE                ; 5                         ; Untyped                                     ;
; C6_TEST_SOURCE                ; 5                         ; Untyped                                     ;
; C7_TEST_SOURCE                ; 5                         ; Untyped                                     ;
; C8_TEST_SOURCE                ; 5                         ; Untyped                                     ;
; C9_TEST_SOURCE                ; 5                         ; Untyped                                     ;
; CBXI_PARAMETER                ; NOTHING                   ; Untyped                                     ;
; VCO_FREQUENCY_CONTROL         ; AUTO                      ; Untyped                                     ;
; VCO_PHASE_SHIFT_STEP          ; 0                         ; Untyped                                     ;
; WIDTH_CLOCK                   ; 6                         ; Untyped                                     ;
; WIDTH_PHASECOUNTERSELECT      ; 4                         ; Untyped                                     ;
; USING_FBMIMICBIDIR_PORT       ; OFF                       ; Untyped                                     ;
; DEVICE_FAMILY                 ; Cyclone II                ; Untyped                                     ;
; SCAN_CHAIN_MIF_FILE           ; UNUSED                    ; Untyped                                     ;
; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF                       ; Untyped                                     ;
; AUTO_CARRY_CHAINS             ; ON                        ; AUTO_CARRY                                  ;
; IGNORE_CARRY_BUFFERS          ; OFF                       ; IGNORE_CARRY                                ;
; AUTO_CASCADE_CHAINS           ; ON                        ; AUTO_CASCADE                                ;
; IGNORE_CASCADE_BUFFERS        ; OFF                       ; IGNORE_CASCADE                              ;
+-------------------------------+---------------------------+---------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|lpm_mult0:lpm_mult0_1|lpm_mult:lpm_mult_component ;
+------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                                 ; Value      ; Type                                                                                                                                   ;
+------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS                              ; ON         ; AUTO_CARRY                                                                                                                             ;
; IGNORE_CARRY_BUFFERS                           ; OFF        ; IGNORE_CARRY                                                                                                                           ;
; AUTO_CASCADE_CHAINS                            ; ON         ; AUTO_CASCADE                                                                                                                           ;
; IGNORE_CASCADE_BUFFERS                         ; OFF        ; IGNORE_CASCADE                                                                                                                         ;
; LPM_WIDTHA                                     ; 24         ; Signed Integer                                                                                                                         ;
; LPM_WIDTHB                                     ; 64         ; Signed Integer                                                                                                                         ;
; LPM_WIDTHP                                     ; 24         ; Signed Integer                                                                                                                         ;
; LPM_WIDTHR                                     ; 0          ; Untyped                                                                                                                                ;
; LPM_WIDTHS                                     ; 1          ; Untyped                                                                                                                                ;
; LPM_REPRESENTATION                             ; SIGNED     ; Untyped                                                                                                                                ;
; LPM_PIPELINE                                   ; 0          ; Untyped                                                                                                                                ;
; LATENCY                                        ; 0          ; Untyped                                                                                                                                ;
; INPUT_A_IS_CONSTANT                            ; NO         ; Untyped                                                                                                                                ;
; INPUT_B_IS_CONSTANT                            ; NO         ; Untyped                                                                                                                                ;
; USE_EAB                                        ; OFF        ; Untyped                                                                                                                                ;
; MAXIMIZE_SPEED                                 ; 5          ; Untyped                                                                                                                                ;
; DEVICE_FAMILY                                  ; Cyclone II ; Untyped                                                                                                                                ;
; CARRY_CHAIN                                    ; MANUAL     ; Untyped                                                                                                                                ;
; APEX20K_TECHNOLOGY_MAPPER                      ; LUT        ; TECH_MAPPER_APEX20K                                                                                                                    ;
; DEDICATED_MULTIPLIER_CIRCUITRY                 ; YES        ; Untyped                                                                                                                                ;
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0          ; Untyped                                                                                                                                ;
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0          ; Untyped                                                                                                                                ;
; CBXI_PARAMETER                                 ; mult_inq   ; Untyped                                                                                                                                ;
; INPUT_A_FIXED_VALUE                            ; Bx         ; Untyped                                                                                                                                ;
; INPUT_B_FIXED_VALUE                            ; Bx         ; Untyped                                                                                                                                ;
; USE_AHDL_IMPLEMENTATION                        ; OFF        ; Untyped                                                                                                                                ;
+------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|lpm_mult:Mult0 ;
+------------------------------------------------+------------+----------------------------------------------------------------------------------------------+
; Parameter Name                                 ; Value      ; Type                                                                                         ;
+------------------------------------------------+------------+----------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS                              ; ON         ; AUTO_CARRY                                                                                   ;
; IGNORE_CARRY_BUFFERS                           ; OFF        ; IGNORE_CARRY                                                                                 ;
; AUTO_CASCADE_CHAINS                            ; ON         ; AUTO_CASCADE                                                                                 ;
; IGNORE_CASCADE_BUFFERS                         ; OFF        ; IGNORE_CASCADE                                                                               ;
; LPM_WIDTHA                                     ; 24         ; Untyped                                                                                      ;
; LPM_WIDTHB                                     ; 40         ; Untyped                                                                                      ;
; LPM_WIDTHP                                     ; 64         ; Untyped                                                                                      ;
; LPM_WIDTHR                                     ; 64         ; Untyped                                                                                      ;
; LPM_WIDTHS                                     ; 1          ; Untyped                                                                                      ;
; LPM_REPRESENTATION                             ; SIGNED     ; Untyped                                                                                      ;
; LPM_PIPELINE                                   ; 0          ; Untyped                                                                                      ;
; LATENCY                                        ; 0          ; Untyped                                                                                      ;
; INPUT_A_IS_CONSTANT                            ; NO         ; Untyped                                                                                      ;
; INPUT_B_IS_CONSTANT                            ; NO         ; Untyped                                                                                      ;
; USE_EAB                                        ; OFF        ; Untyped                                                                                      ;
; MAXIMIZE_SPEED                                 ; 5          ; Untyped                                                                                      ;
; DEVICE_FAMILY                                  ; Cyclone II ; Untyped                                                                                      ;
; CARRY_CHAIN                                    ; MANUAL     ; Untyped                                                                                      ;
; APEX20K_TECHNOLOGY_MAPPER                      ; LUT        ; TECH_MAPPER_APEX20K                                                                          ;
; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO       ; Untyped                                                                                      ;
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0          ; Untyped                                                                                      ;
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0          ; Untyped                                                                                      ;
; CBXI_PARAMETER                                 ; mult_i1t   ; Untyped                                                                                      ;
; INPUT_A_FIXED_VALUE                            ; Bx         ; Untyped                                                                                      ;
; INPUT_B_FIXED_VALUE                            ; Bx         ; Untyped                                                                                      ;
; USE_AHDL_IMPLEMENTATION                        ; OFF        ; Untyped                                                                                      ;
+------------------------------------------------+------------+----------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------+
; altpll Parameter Settings by Entity Instance                                               ;
+-------------------------------+------------------------------------------------------------+
; Name                          ; Value                                                      ;
+-------------------------------+------------------------------------------------------------+
; Number of entity instances    ; 2                                                          ;
; Entity Instance               ; clock_generator:inst|altpll0:inst|altpll:altpll_component  ;
;     -- OPERATION_MODE         ; NORMAL                                                     ;
;     -- PLL_TYPE               ; AUTO                                                       ;
;     -- PRIMARY_CLOCK          ; INCLK0                                                     ;
;     -- INCLK0_INPUT_FREQUENCY ; 20000                                                      ;
;     -- INCLK1_INPUT_FREQUENCY ; 0                                                          ;
;     -- VCO_MULTIPLY_BY        ; 0                                                          ;
;     -- VCO_DIVIDE_BY          ; 0                                                          ;
; Entity Instance               ; clock_generator:inst|altpll1:inst1|altpll:altpll_component ;
;     -- OPERATION_MODE         ; NORMAL                                                     ;
;     -- PLL_TYPE               ; AUTO                                                       ;
;     -- PRIMARY_CLOCK          ; INCLK0                                                     ;
;     -- INCLK0_INPUT_FREQUENCY ; 37037                                                      ;
;     -- INCLK1_INPUT_FREQUENCY ; 0                                                          ;
;     -- VCO_MULTIPLY_BY        ; 0                                                          ;
;     -- VCO_DIVIDE_BY          ; 0                                                          ;
+-------------------------------+------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; lpm_mult Parameter Settings by Entity Instance                                                                                                                                                  ;
+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; Name                                  ; Value                                                                                                                                                   ;
+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; Number of entity instances            ; 2                                                                                                                                                       ;
; Entity Instance                       ; audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|lpm_mult0:lpm_mult0_1|lpm_mult:lpm_mult_component ;
;     -- LPM_WIDTHA                     ; 24                                                                                                                                                      ;
;     -- LPM_WIDTHB                     ; 64                                                                                                                                                      ;
;     -- LPM_WIDTHP                     ; 24                                                                                                                                                      ;
;     -- LPM_REPRESENTATION             ; SIGNED                                                                                                                                                  ;
;     -- INPUT_A_IS_CONSTANT            ; NO                                                                                                                                                      ;
;     -- INPUT_B_IS_CONSTANT            ; NO                                                                                                                                                      ;
;     -- USE_EAB                        ; OFF                                                                                                                                                     ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; YES                                                                                                                                                     ;
;     -- INPUT_A_FIXED_VALUE            ; Bx                                                                                                                                                      ;
;     -- INPUT_B_FIXED_VALUE            ; Bx                                                                                                                                                      ;
; Entity Instance                       ; audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|lpm_mult:Mult0                                               ;
;     -- LPM_WIDTHA                     ; 24                                                                                                                                                      ;
;     -- LPM_WIDTHB                     ; 40                                                                                                                                                      ;
;     -- LPM_WIDTHP                     ; 64                                                                                                                                                      ;
;     -- LPM_REPRESENTATION             ; SIGNED                                                                                                                                                  ;
;     -- INPUT_A_IS_CONSTANT            ; NO                                                                                                                                                      ;
;     -- INPUT_B_IS_CONSTANT            ; NO                                                                                                                                                      ;
;     -- USE_EAB                        ; OFF                                                                                                                                                     ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                                                                                                                                                    ;
;     -- INPUT_A_FIXED_VALUE            ; Bx                                                                                                                                                      ;
;     -- INPUT_B_FIXED_VALUE            ; Bx                                                                                                                                                      ;
+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "audio_unit:inst2|i2c_master:i2c_master_1"                                                  ;
+-------------+--------+----------+-------------------------------------------------------------------------------------+
; Port        ; Type   ; Severity ; Details                                                                             ;
+-------------+--------+----------+-------------------------------------------------------------------------------------+
; state_count ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+-------------+--------+----------+-------------------------------------------------------------------------------------+


+-------------------------------+
; Elapsed Time Per Partition    ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top            ; 00:00:27     ;
+----------------+--------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
    Info: Version 11.1 Build 173 11/01/2011 SJ Full Version
    Info: Processing started: Fri Jun 08 14:35:01 2012
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Equalizer -c Equalizer
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (12021): Found 1 design units, including 1 entities, in source file equalizer.bdf
    Info (12023): Found entity 1: Equalizer
Info (12021): Found 1 design units, including 1 entities, in source file clock_generator.bdf
    Info (12023): Found entity 1: clock_generator
Info (12021): Found 2 design units, including 1 entities, in source file altpll0.vhd
    Info (12022): Found design unit 1: altpll0-SYN
    Info (12023): Found entity 1: altpll0
Info (12021): Found 2 design units, including 1 entities, in source file altpll1.vhd
    Info (12022): Found design unit 1: altpll1-SYN
    Info (12023): Found entity 1: altpll1
Info (12021): Found 2 design units, including 1 entities, in source file clock_divider.vhd
    Info (12022): Found design unit 1: clock_divider-clock_divider_architecture
    Info (12023): Found entity 1: clock_divider
Info (12021): Found 2 design units, including 1 entities, in source file mmi_controller.vhd
    Info (12022): Found design unit 1: mmi_controller-behavior
    Info (12023): Found entity 1: mmi_controller
Info (12021): Found 2 design units, including 1 entities, in source file lcd_controller.vhd
    Info (12022): Found design unit 1: lcd_controller-a_lcd_controller
    Info (12023): Found entity 1: lcd_controller
Info (12021): Found 2 design units, including 1 entities, in source file audio_unit.vhd
    Info (12022): Found design unit 1: audio_unit-audio_unit_architecture
    Info (12023): Found entity 1: audio_unit
Info (12021): Found 2 design units, including 1 entities, in source file i2c_transmitter.vhd
    Info (12022): Found design unit 1: i2c_transmitter-a_i2c_transmitter
    Info (12023): Found entity 1: i2c_transmitter
Info (12021): Found 2 design units, including 1 entities, in source file i2c_data_register.vhd
    Info (12022): Found design unit 1: i2c_data_register-a_i2c_data_register
    Info (12023): Found entity 1: i2c_data_register
Info (12021): Found 2 design units, including 1 entities, in source file mmi.vhd
    Info (12022): Found design unit 1: MMI-MMI_architecture
    Info (12023): Found entity 1: MMI
Info (12021): Found 2 design units, including 1 entities, in source file i2c_master.vhd
    Info (12022): Found design unit 1: i2c_master-BEHAVIOR
    Info (12023): Found entity 1: i2c_master
Info (12021): Found 2 design units, including 1 entities, in source file filter_unit.vhd
    Info (12022): Found design unit 1: filter_unit-filter_unit_architecture
    Info (12023): Found entity 1: filter_unit
Info (12021): Found 2 design units, including 1 entities, in source file filter_arithmetic_unit.vhd
    Info (12022): Found design unit 1: filter_arithmetic_unit-behavior
    Info (12023): Found entity 1: filter_arithmetic_unit
Info (12021): Found 2 design units, including 1 entities, in source file audio_input_register.vhd
    Info (12022): Found design unit 1: audio_input_register-behavior
    Info (12023): Found entity 1: audio_input_register
Info (12021): Found 2 design units, including 1 entities, in source file audio_output_register.vhd
    Info (12022): Found design unit 1: audio_output_register-behavior
    Info (12023): Found entity 1: audio_output_register
Info (12021): Found 2 design units, including 1 entities, in source file iir.vhd
    Info (12022): Found design unit 1: iir-behavior
    Info (12023): Found entity 1: iir
Info (12021): Found 2 design units, including 1 entities, in source file db2linear.vhd
    Info (12022): Found design unit 1: db2linear-behavior
    Info (12023): Found entity 1: db2linear
Info (12021): Found 2 design units, including 1 entities, in source file lpm_mult0.vhd
    Info (12022): Found design unit 1: lpm_mult0-SYN
    Info (12023): Found entity 1: lpm_mult0
Info (12127): Elaborating entity "Equalizer" for the top level hierarchy
Warning (275083): Bus "filter10[7..0]" found using same base name as "filter1", which might lead to a name conflict.
Warning (275083): Bus "filter11[7..0]" found using same base name as "filter1", which might lead to a name conflict.
Warning (275083): Bus "filter12[7..0]" found using same base name as "filter1", which might lead to a name conflict.
Warning (275083): Bus "filter13[7..0]" found using same base name as "filter1", which might lead to a name conflict.
Warning (275083): Bus "filter14[7..0]" found using same base name as "filter1", which might lead to a name conflict.
Warning (275080): Converted elements in bus name "filter1" using legacy naming rules. Make any assignments on the new names, not on the original names.
    Warning (275081): Converted element name(s) from "filter1[7..0]" to "filter17..0"
Warning (275080): Converted elements in bus name "filter10" using legacy naming rules. Make any assignments on the new names, not on the original names.
    Warning (275081): Converted element name(s) from "filter10[7..0]" to "filter107..0"
Warning (275080): Converted elements in bus name "filter11" using legacy naming rules. Make any assignments on the new names, not on the original names.
    Warning (275081): Converted element name(s) from "filter11[7..0]" to "filter117..0"
Warning (275080): Converted elements in bus name "filter12" using legacy naming rules. Make any assignments on the new names, not on the original names.
    Warning (275081): Converted element name(s) from "filter12[7..0]" to "filter127..0"
Warning (275080): Converted elements in bus name "filter13" using legacy naming rules. Make any assignments on the new names, not on the original names.
    Warning (275081): Converted element name(s) from "filter13[7..0]" to "filter137..0"
Warning (275080): Converted elements in bus name "filter14" using legacy naming rules. Make any assignments on the new names, not on the original names.
    Warning (275081): Converted element name(s) from "filter14[7..0]" to "filter147..0"
Warning (275083): Bus "filter10[7..0]" found using same base name as "filter1", which might lead to a name conflict.
Warning (275083): Bus "filter11[7..0]" found using same base name as "filter1", which might lead to a name conflict.
Warning (275083): Bus "filter12[7..0]" found using same base name as "filter1", which might lead to a name conflict.
Warning (275083): Bus "filter13[7..0]" found using same base name as "filter1", which might lead to a name conflict.
Warning (275083): Bus "filter14[7..0]" found using same base name as "filter1", which might lead to a name conflict.
Warning (275080): Converted elements in bus name "filter1" using legacy naming rules. Make any assignments on the new names, not on the original names.
    Warning (275081): Converted element name(s) from "filter1[7..0]" to "filter17..0"
Warning (275080): Converted elements in bus name "filter10" using legacy naming rules. Make any assignments on the new names, not on the original names.
    Warning (275081): Converted element name(s) from "filter10[7..0]" to "filter107..0"
Warning (275080): Converted elements in bus name "filter11" using legacy naming rules. Make any assignments on the new names, not on the original names.
    Warning (275081): Converted element name(s) from "filter11[7..0]" to "filter117..0"
Warning (275080): Converted elements in bus name "filter12" using legacy naming rules. Make any assignments on the new names, not on the original names.
    Warning (275081): Converted element name(s) from "filter12[7..0]" to "filter127..0"
Warning (275080): Converted elements in bus name "filter13" using legacy naming rules. Make any assignments on the new names, not on the original names.
    Warning (275081): Converted element name(s) from "filter13[7..0]" to "filter137..0"
Warning (275080): Converted elements in bus name "filter14" using legacy naming rules. Make any assignments on the new names, not on the original names.
    Warning (275081): Converted element name(s) from "filter14[7..0]" to "filter147..0"
Info (12128): Elaborating entity "MMI" for hierarchy "MMI:inst1"
Info (12128): Elaborating entity "lcd_controller" for hierarchy "MMI:inst1|lcd_controller:lcd_controller_1"
Info (12128): Elaborating entity "mmi_controller" for hierarchy "MMI:inst1|mmi_controller:mmi_controller_1"
Info (12128): Elaborating entity "clock_generator" for hierarchy "clock_generator:inst"
Warning (275014): INPUTC, OUTPUTC and BIDIRC pins not supported for pin "CLOCK_50"
Warning (275014): INPUTC, OUTPUTC and BIDIRC pins not supported for pin "CLOCK_27"
Warning (275014): INPUTC, OUTPUTC and BIDIRC pins not supported for pin "clk_50MHz"
Warning (275014): INPUTC, OUTPUTC and BIDIRC pins not supported for pin "clk_27MHz"
Warning (275014): INPUTC, OUTPUTC and BIDIRC pins not supported for pin "clk_12MHz"
Warning (275014): INPUTC, OUTPUTC and BIDIRC pins not supported for pin "clk_400kHz"
Warning (275014): INPUTC, OUTPUTC and BIDIRC pins not supported for pin "clk_100Hz"
Info (12128): Elaborating entity "altpll0" for hierarchy "clock_generator:inst|altpll0:inst"
Info (12128): Elaborating entity "altpll" for hierarchy "clock_generator:inst|altpll0:inst|altpll:altpll_component"
Info (12130): Elaborated megafunction instantiation "clock_generator:inst|altpll0:inst|altpll:altpll_component"
Info (12133): Instantiated megafunction "clock_generator:inst|altpll0:inst|altpll:altpll_component" with the following parameter:
    Info (12134): Parameter "clk0_divide_by" = "1"
    Info (12134): Parameter "clk0_duty_cycle" = "50"
    Info (12134): Parameter "clk0_multiply_by" = "1"
    Info (12134): Parameter "clk0_phase_shift" = "0"
    Info (12134): Parameter "clk1_divide_by" = "5"
    Info (12134): Parameter "clk1_duty_cycle" = "50"
    Info (12134): Parameter "clk1_multiply_by" = "1"
    Info (12134): Parameter "clk1_phase_shift" = "0"
    Info (12134): Parameter "compensate_clock" = "CLK0"
    Info (12134): Parameter "inclk0_input_frequency" = "20000"
    Info (12134): Parameter "intended_device_family" = "Cyclone II"
    Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=altpll0"
    Info (12134): Parameter "lpm_type" = "altpll"
    Info (12134): Parameter "operation_mode" = "NORMAL"
    Info (12134): Parameter "port_activeclock" = "PORT_UNUSED"
    Info (12134): Parameter "port_areset" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkloss" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED"
    Info (12134): Parameter "port_configupdate" = "PORT_UNUSED"
    Info (12134): Parameter "port_fbin" = "PORT_UNUSED"
    Info (12134): Parameter "port_inclk0" = "PORT_USED"
    Info (12134): Parameter "port_inclk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_locked" = "PORT_UNUSED"
    Info (12134): Parameter "port_pfdena" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasedone" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasestep" = "PORT_UNUSED"
    Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED"
    Info (12134): Parameter "port_pllena" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanclk" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandata" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandataout" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandone" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanread" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk0" = "PORT_USED"
    Info (12134): Parameter "port_clk1" = "PORT_USED"
    Info (12134): Parameter "port_clk2" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk3" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk4" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk5" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena0" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena2" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena3" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena4" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena5" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk0" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk2" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk3" = "PORT_UNUSED"
Info (12128): Elaborating entity "altpll1" for hierarchy "clock_generator:inst|altpll1:inst1"
Info (12128): Elaborating entity "altpll" for hierarchy "clock_generator:inst|altpll1:inst1|altpll:altpll_component"
Info (12130): Elaborated megafunction instantiation "clock_generator:inst|altpll1:inst1|altpll:altpll_component"
Info (12133): Instantiated megafunction "clock_generator:inst|altpll1:inst1|altpll:altpll_component" with the following parameter:
    Info (12134): Parameter "clk0_divide_by" = "1"
    Info (12134): Parameter "clk0_duty_cycle" = "50"
    Info (12134): Parameter "clk0_multiply_by" = "1"
    Info (12134): Parameter "clk0_phase_shift" = "0"
    Info (12134): Parameter "clk1_divide_by" = "9"
    Info (12134): Parameter "clk1_duty_cycle" = "50"
    Info (12134): Parameter "clk1_multiply_by" = "4"
    Info (12134): Parameter "clk1_phase_shift" = "0"
    Info (12134): Parameter "compensate_clock" = "CLK0"
    Info (12134): Parameter "inclk0_input_frequency" = "37037"
    Info (12134): Parameter "intended_device_family" = "Cyclone II"
    Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=altpll1"
    Info (12134): Parameter "lpm_type" = "altpll"
    Info (12134): Parameter "operation_mode" = "NORMAL"
    Info (12134): Parameter "port_activeclock" = "PORT_UNUSED"
    Info (12134): Parameter "port_areset" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkloss" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED"
    Info (12134): Parameter "port_configupdate" = "PORT_UNUSED"
    Info (12134): Parameter "port_fbin" = "PORT_UNUSED"
    Info (12134): Parameter "port_inclk0" = "PORT_USED"
    Info (12134): Parameter "port_inclk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_locked" = "PORT_UNUSED"
    Info (12134): Parameter "port_pfdena" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasedone" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasestep" = "PORT_UNUSED"
    Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED"
    Info (12134): Parameter "port_pllena" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanclk" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandata" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandataout" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandone" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanread" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk0" = "PORT_USED"
    Info (12134): Parameter "port_clk1" = "PORT_USED"
    Info (12134): Parameter "port_clk2" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk3" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk4" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk5" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena0" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena2" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena3" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena4" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena5" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk0" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk2" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk3" = "PORT_UNUSED"
Info (12128): Elaborating entity "clock_divider" for hierarchy "clock_generator:inst|clock_divider:inst3"
Info (12128): Elaborating entity "audio_unit" for hierarchy "audio_unit:inst2"
Warning (10036): Verilog HDL or VHDL warning at audio_unit.vhd(71): object "sc" assigned a value but never read
Info (12128): Elaborating entity "i2c_master" for hierarchy "audio_unit:inst2|i2c_master:i2c_master_1"
Info (12128): Elaborating entity "audio_input_register" for hierarchy "audio_unit:inst2|audio_input_register:audio_input_register_1"
Info (12128): Elaborating entity "filter_unit" for hierarchy "audio_unit:inst2|filter_unit:filter_unit_1"
Info (12128): Elaborating entity "filter_arithmetic_unit" for hierarchy "audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1"
Info (12128): Elaborating entity "iir" for hierarchy "audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter"
Warning (10036): Verilog HDL or VHDL warning at iir.vhd(57): object "a0" assigned a value but never read
Info (12128): Elaborating entity "lpm_mult0" for hierarchy "audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|lpm_mult0:lpm_mult0_1"
Info (12128): Elaborating entity "lpm_mult" for hierarchy "audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|lpm_mult0:lpm_mult0_1|lpm_mult:lpm_mult_component"
Info (12130): Elaborated megafunction instantiation "audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|lpm_mult0:lpm_mult0_1|lpm_mult:lpm_mult_component"
Info (12133): Instantiated megafunction "audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|lpm_mult0:lpm_mult0_1|lpm_mult:lpm_mult_component" with the following parameter:
    Info (12134): Parameter "lpm_hint" = "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=5"
    Info (12134): Parameter "lpm_representation" = "SIGNED"
    Info (12134): Parameter "lpm_type" = "LPM_MULT"
    Info (12134): Parameter "lpm_widtha" = "24"
    Info (12134): Parameter "lpm_widthb" = "64"
    Info (12134): Parameter "lpm_widthp" = "24"
Info (12021): Found 1 design units, including 1 entities, in source file db/mult_inq.tdf
    Info (12023): Found entity 1: mult_inq
Info (12128): Elaborating entity "mult_inq" for hierarchy "audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|iir:filter|lpm_mult0:lpm_mult0_1|lpm_mult:lpm_mult_component|mult_inq:auto_generated"
Info (12128): Elaborating entity "db2linear" for hierarchy "audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|db2linear:volume_db2linear"
Info (12128): Elaborating entity "audio_output_register" for hierarchy "audio_unit:inst2|audio_output_register:audio_output_register_1"
Info (13014): Ignored 536 buffer(s)
    Info (13019): Ignored 536 SOFT buffer(s)
Info (13005): Duplicate registers merged to single register
Info (13005): Duplicate registers merged to single register
Info (278001): Inferred 1 megafunctions from design logic
    Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|Mult0"
Info (12130): Elaborated megafunction instantiation "audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|lpm_mult:Mult0"
Info (12133): Instantiated megafunction "audio_unit:inst2|filter_unit:filter_unit_1|filter_arithmetic_unit:filter_arithmetic_unit_1|lpm_mult:Mult0" with the following parameter:
    Info (12134): Parameter "LPM_WIDTHA" = "24"
    Info (12134): Parameter "LPM_WIDTHB" = "40"
    Info (12134): Parameter "LPM_WIDTHP" = "64"
    Info (12134): Parameter "LPM_WIDTHR" = "64"
    Info (12134): Parameter "LPM_WIDTHS" = "1"
    Info (12134): Parameter "LPM_REPRESENTATION" = "SIGNED"
    Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO"
    Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "NO"
    Info (12134): Parameter "MAXIMIZE_SPEED" = "5"
Info (12021): Found 1 design units, including 1 entities, in source file db/mult_i1t.tdf
    Info (12023): Found entity 1: mult_i1t
Info (13014): Ignored 314 buffer(s)
    Info (13019): Ignored 314 SOFT buffer(s)
Warning (13034): The following nodes have both tri-state and non-tri-state drivers
    Warning (13035): Inserted always-enabled tri-state buffer between "LCD_DATA[7]" and its non-tri-state driver.
    Warning (13035): Inserted always-enabled tri-state buffer between "LCD_DATA[6]" and its non-tri-state driver.
    Warning (13035): Inserted always-enabled tri-state buffer between "LCD_DATA[5]" and its non-tri-state driver.
    Warning (13035): Inserted always-enabled tri-state buffer between "LCD_DATA[4]" and its non-tri-state driver.
    Warning (13035): Inserted always-enabled tri-state buffer between "LCD_DATA[3]" and its non-tri-state driver.
    Warning (13035): Inserted always-enabled tri-state buffer between "LCD_DATA[2]" and its non-tri-state driver.
    Warning (13035): Inserted always-enabled tri-state buffer between "LCD_DATA[1]" and its non-tri-state driver.
    Warning (13035): Inserted always-enabled tri-state buffer between "LCD_DATA[0]" and its non-tri-state driver.
Info (13000): Registers with preset signals will power-up high
Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Warning (13009): TRI or OPNDRN buffers permanently enabled
    Warning (13010): Node "LCD_DATA~synth"
    Warning (13010): Node "LCD_DATA~synth"
    Warning (13010): Node "LCD_DATA~synth"
    Warning (13010): Node "LCD_DATA~synth"
    Warning (13010): Node "LCD_DATA~synth"
    Warning (13010): Node "LCD_DATA~synth"
    Warning (13010): Node "LCD_DATA~synth"
    Warning (13010): Node "LCD_DATA~synth"
Warning (13024): Output pins are stuck at VCC or GND
    Warning (13410): Pin "LCD_BLON" is stuck at VCC
    Warning (13410): Pin "LCD_ON" is stuck at VCC
    Warning (13410): Pin "LCD_RW" is stuck at GND
    Warning (13410): Pin "HEX0[1]" is stuck at VCC
    Warning (13410): Pin "HEX0[0]" is stuck at VCC
    Warning (13410): Pin "HEX1[5]" is stuck at VCC
    Warning (13410): Pin "HEX1[0]" is stuck at VCC
    Warning (13410): Pin "HEX4[5]" is stuck at VCC
    Warning (13410): Pin "HEX4[4]" is stuck at VCC
    Warning (13410): Pin "HEX4[3]" is stuck at VCC
    Warning (13410): Pin "HEX4[2]" is stuck at VCC
    Warning (13410): Pin "HEX4[1]" is stuck at VCC
    Warning (13410): Pin "HEX4[0]" is stuck at VCC
    Warning (13410): Pin "HEX7[6]" is stuck at VCC
Critical Warning (18061): Ignored Power-Up Level option on the following registers
    Critical Warning (18010): Register audio_unit:inst2|i2c_master:i2c_master_1|SDIN~en will power up to High
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
    Info (16011): Adding node "clock_generator:inst|altpll1:inst1|altpll:altpll_component|pll"
    Info (16011): Adding node "clock_generator:inst|altpll0:inst|altpll:altpll_component|pll"
Info (21057): Implemented 2755 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 13 input pins
    Info (21059): Implemented 57 output pins
    Info (21060): Implemented 9 bidirectional pins
    Info (21061): Implemented 2647 logic cells
    Info (21065): Implemented 2 PLLs
    Info (21062): Implemented 27 DSP elements
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 79 warnings
    Info: Peak virtual memory: 514 megabytes
    Info: Processing ended: Fri Jun 08 14:35:30 2012
    Info: Elapsed time: 00:00:29
    Info: Total CPU time (on all processors): 00:00:27


