Analysis & Synthesis report for Equalizer
Fri Jun 08 00:35:58 2012
Quartus II 64-Bit Version 11.1 Build 173 11/01/2011 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. Analysis & Synthesis RAM Summary
  9. Analysis & Synthesis IP Cores Summary
 10. Registers Removed During Synthesis
 11. Removed Registers Triggering Further Register Optimizations
 12. General Register Statistics
 13. Inverted Register Statistics
 14. Registers Packed Into Inferred Megafunctions
 15. Multiplexer Restructuring Statistics (Restructuring Performed)
 16. Source assignments for mmi:inst2|lcd_controller:inst2|altsyncram:Mux13_rtl_0|altsyncram_dk01:auto_generated
 17. Source assignments for mmi:inst2|lcd_controller:inst2|altsyncram:Mux12_rtl_0|altsyncram_ek01:auto_generated
 18. Source assignments for mmi:inst2|lcd_controller:inst2|altsyncram:Mux11_rtl_0|altsyncram_fk01:auto_generated
 19. Source assignments for mmi:inst2|lcd_controller:inst2|altsyncram:Mux10_rtl_0|altsyncram_gk01:auto_generated
 20. Source assignments for mmi:inst2|lcd_controller:inst2|altsyncram:Mux9_rtl_0|altsyncram_hk01:auto_generated
 21. Parameter Settings for User Entity Instance: clock_generator:inst3|altpll0:inst|altpll:altpll_component
 22. Parameter Settings for User Entity Instance: clock_generator:inst3|altpll2:inst2|altpll:altpll_component
 23. Parameter Settings for Inferred Entity Instance: mmi:inst2|lcd_controller:inst2|altsyncram:Mux13_rtl_0
 24. Parameter Settings for Inferred Entity Instance: mmi:inst2|lcd_controller:inst2|altsyncram:Mux12_rtl_0
 25. Parameter Settings for Inferred Entity Instance: mmi:inst2|lcd_controller:inst2|altsyncram:Mux11_rtl_0
 26. Parameter Settings for Inferred Entity Instance: mmi:inst2|lcd_controller:inst2|altsyncram:Mux10_rtl_0
 27. Parameter Settings for Inferred Entity Instance: mmi:inst2|lcd_controller:inst2|altsyncram:Mux9_rtl_0
 28. altpll Parameter Settings by Entity Instance
 29. altsyncram Parameter Settings by Entity Instance
 30. Elapsed Time Per Partition
 31. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2011 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                   ;
+------------------------------------+-------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Fri Jun 08 00:35:58 2012     ;
; Quartus II 64-Bit Version          ; 11.1 Build 173 11/01/2011 SJ Full Version ;
; Revision Name                      ; Equalizer                                 ;
; Top-level Entity Name              ; Equalizer                                 ;
; Family                             ; Cyclone II                                ;
; Total logic elements               ; 949                                       ;
;     Total combinational functions  ; 907                                       ;
;     Dedicated logic registers      ; 291                                       ;
; Total registers                    ; 291                                       ;
; Total pins                         ; 79                                        ;
; Total virtual pins                 ; 0                                         ;
; Total memory bits                  ; 160                                       ;
; Embedded Multiplier 9-bit elements ; 0                                         ;
; Total PLLs                         ; 2                                         ;
+------------------------------------+-------------------------------------------+


+----------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                  ;
+----------------------------------------------------------------------------+--------------+--------------------+
; Option                                                                     ; Setting      ; Default Value      ;
+----------------------------------------------------------------------------+--------------+--------------------+
; Device                                                                     ; EP2C35F672C6 ;                    ;
; Top-level entity name                                                      ; Equalizer    ; Equalizer          ;
; Family name                                                                ; Cyclone II   ; Cyclone IV GX      ;
; Preserve fewer node names                                                  ; Off          ; On                 ;
; Disable OpenCore Plus hardware evaluation                                  ; On           ; Off                ;
; VHDL Show LMF Mapping Messages                                             ; Off          ;                    ;
; Safe State Machine                                                         ; On           ; Off                ;
; Parallel Synthesis                                                         ; On           ; Off                ;
; Power-Up Don't Care                                                        ; Off          ; On                 ;
; Remove Duplicate Registers                                                 ; Off          ; On                 ;
; Allow Any RAM Size For Recognition                                         ; On           ; Off                ;
; Allow Any ROM Size For Recognition                                         ; On           ; Off                ;
; PowerPlay Power Optimization                                               ; Off          ; Normal compilation ;
; HDL message level                                                          ; Level3       ; Level2             ;
; Use smart compilation                                                      ; Off          ; Off                ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On           ; On                 ;
; Enable compact report table                                                ; Off          ; Off                ;
; Restructure Multiplexers                                                   ; Auto         ; Auto               ;
; Create Debugging Nodes for IP Cores                                        ; Off          ; Off                ;
; Verilog Version                                                            ; Verilog_2001 ; Verilog_2001       ;
; VHDL Version                                                               ; VHDL_1993    ; VHDL_1993          ;
; State Machine Processing                                                   ; Auto         ; Auto               ;
; Extract Verilog State Machines                                             ; On           ; On                 ;
; Extract VHDL State Machines                                                ; On           ; On                 ;
; Ignore Verilog initial constructs                                          ; Off          ; Off                ;
; Iteration limit for constant Verilog loops                                 ; 5000         ; 5000               ;
; Iteration limit for non-constant Verilog loops                             ; 250          ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                                    ; On           ; On                 ;
; Infer RAMs from Raw Logic                                                  ; On           ; On                 ;
; DSP Block Balancing                                                        ; Auto         ; Auto               ;
; NOT Gate Push-Back                                                         ; On           ; On                 ;
; Remove Redundant Logic Cells                                               ; Off          ; Off                ;
; Ignore CARRY Buffers                                                       ; Off          ; Off                ;
; Ignore CASCADE Buffers                                                     ; Off          ; Off                ;
; Ignore GLOBAL Buffers                                                      ; Off          ; Off                ;
; Ignore ROW GLOBAL Buffers                                                  ; Off          ; Off                ;
; Ignore LCELL Buffers                                                       ; Off          ; Off                ;
; Ignore SOFT Buffers                                                        ; On           ; On                 ;
; Limit AHDL Integers to 32 Bits                                             ; Off          ; Off                ;
; Optimization Technique                                                     ; Balanced     ; Balanced           ;
; Carry Chain Length                                                         ; 70           ; 70                 ;
; Auto Carry Chains                                                          ; On           ; On                 ;
; Auto Open-Drain Pins                                                       ; On           ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                      ; Off          ; Off                ;
; Auto ROM Replacement                                                       ; On           ; On                 ;
; Auto RAM Replacement                                                       ; On           ; On                 ;
; Auto Shift Register Replacement                                            ; Auto         ; Auto               ;
; Allow Shift Register Merging across Hierarchies                            ; Auto         ; Auto               ;
; Auto Clock Enable Replacement                                              ; On           ; On                 ;
; Strict RAM Replacement                                                     ; Off          ; Off                ;
; Allow Synchronous Control Signals                                          ; On           ; On                 ;
; Force Use of Synchronous Clear Signals                                     ; Off          ; Off                ;
; Auto RAM to Logic Cell Conversion                                          ; Off          ; Off                ;
; Auto Resource Sharing                                                      ; Off          ; Off                ;
; Allow Any Shift Register Size For Recognition                              ; Off          ; Off                ;
; Use LogicLock Constraints during Resource Balancing                        ; On           ; On                 ;
; Ignore translate_off and synthesis_off directives                          ; Off          ; Off                ;
; Timing-Driven Synthesis                                                    ; Off          ; Off                ;
; Report Parameter Settings                                                  ; On           ; On                 ;
; Report Source Assignments                                                  ; On           ; On                 ;
; Report Connectivity Checks                                                 ; On           ; On                 ;
; Ignore Maximum Fan-Out Assignments                                         ; Off          ; Off                ;
; Synchronization Register Chain Length                                      ; 2            ; 2                  ;
; Suppress Register Optimization Related Messages                            ; Off          ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                   ; 5000         ; 5000               ;
; Number of Inverted Registers Reported in Synthesis Report                  ; 100          ; 100                ;
; Clock MUX Protection                                                       ; On           ; On                 ;
; Auto Gated Clock Conversion                                                ; Off          ; Off                ;
; Block Design Naming                                                        ; Auto         ; Auto               ;
; SDC constraint protection                                                  ; Off          ; Off                ;
; Synthesis Effort                                                           ; Auto         ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On           ; On                 ;
; Analysis & Synthesis Message Level                                         ; Medium       ; Medium             ;
; Disable Register Merging Across Hierarchies                                ; Auto         ; Auto               ;
; Resource Aware Inference For Block RAM                                     ; On           ; On                 ;
; Synthesis Seed                                                             ; 1            ; 1                  ;
+----------------------------------------------------------------------------+--------------+--------------------+


Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation                ;
+----------------------------+--------+
; Processors                 ; Number ;
+----------------------------+--------+
; Number detected on machine ; 2      ;
; Maximum allowed            ; 1      ;
+----------------------------+--------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                                      ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                                                      ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------------------------+
; Equalizer.bdf                    ; yes             ; User Block Diagram/Schematic File  ; D:/Studium/6.Semester/Programmierbare Logik/APL/Equalizer_20120604/Equalizer.bdf                  ;
; audio_unit.bdf                   ; yes             ; User Block Diagram/Schematic File  ; D:/Studium/6.Semester/Programmierbare Logik/APL/Equalizer_20120604/audio_unit.bdf                 ;
; audio_clock_divider.vhd          ; yes             ; User VHDL File                     ; D:/Studium/6.Semester/Programmierbare Logik/APL/Equalizer_20120604/audio_clock_divider.vhd        ;
; i2c_data_register.vhd            ; yes             ; User VHDL File                     ; D:/Studium/6.Semester/Programmierbare Logik/APL/Equalizer_20120604/i2c_data_register.vhd          ;
; i2c_transmitter.vhd              ; yes             ; User VHDL File                     ; D:/Studium/6.Semester/Programmierbare Logik/APL/Equalizer_20120604/i2c_transmitter.vhd            ;
; audio_input_register.vhd         ; yes             ; User VHDL File                     ; D:/Studium/6.Semester/Programmierbare Logik/APL/Equalizer_20120604/audio_input_register.vhd       ;
; audio_output_register.vhd        ; yes             ; User VHDL File                     ; D:/Studium/6.Semester/Programmierbare Logik/APL/Equalizer_20120604/audio_output_register.vhd      ;
; clock_generator.bdf              ; yes             ; User Block Diagram/Schematic File  ; D:/Studium/6.Semester/Programmierbare Logik/APL/Equalizer_20120604/clock_generator.bdf            ;
; filter_unit.bdf                  ; yes             ; User Block Diagram/Schematic File  ; D:/Studium/6.Semester/Programmierbare Logik/APL/Equalizer_20120604/filter_unit.bdf                ;
; filter_arithmetic_unit.vhd       ; yes             ; User VHDL File                     ; D:/Studium/6.Semester/Programmierbare Logik/APL/Equalizer_20120604/filter_arithmetic_unit.vhd     ;
; audio_db_to_factor_decoder.vhd   ; yes             ; User VHDL File                     ; D:/Studium/6.Semester/Programmierbare Logik/APL/Equalizer_20120604/audio_db_to_factor_decoder.vhd ;
; altpll0.vhd                      ; yes             ; User Wizard-Generated File         ; D:/Studium/6.Semester/Programmierbare Logik/APL/Equalizer_20120604/altpll0.vhd                    ;
; mmi.bdf                          ; yes             ; User Block Diagram/Schematic File  ; D:/Studium/6.Semester/Programmierbare Logik/APL/Equalizer_20120604/mmi.bdf                        ;
; mmi_controller.vhd               ; yes             ; User VHDL File                     ; D:/Studium/6.Semester/Programmierbare Logik/APL/Equalizer_20120604/mmi_controller.vhd             ;
; altpll2.vhd                      ; yes             ; User Wizard-Generated File         ; D:/Studium/6.Semester/Programmierbare Logik/APL/Equalizer_20120604/altpll2.vhd                    ;
; iir.vhd                          ; yes             ; User VHDL File                     ; D:/Studium/6.Semester/Programmierbare Logik/APL/Equalizer_20120604/iir.vhd                        ;
; altpll.tdf                       ; yes             ; Megafunction                       ; d:/altera/11.1/quartus/libraries/megafunctions/altpll.tdf                                         ;
; aglobal111.inc                   ; yes             ; Megafunction                       ; d:/altera/11.1/quartus/libraries/megafunctions/aglobal111.inc                                     ;
; stratix_pll.inc                  ; yes             ; Megafunction                       ; d:/altera/11.1/quartus/libraries/megafunctions/stratix_pll.inc                                    ;
; stratixii_pll.inc                ; yes             ; Megafunction                       ; d:/altera/11.1/quartus/libraries/megafunctions/stratixii_pll.inc                                  ;
; cycloneii_pll.inc                ; yes             ; Megafunction                       ; d:/altera/11.1/quartus/libraries/megafunctions/cycloneii_pll.inc                                  ;
; lcd_controller.vhd               ; yes             ; Auto-Found VHDL File               ; D:/Studium/6.Semester/Programmierbare Logik/APL/Equalizer_20120604/lcd_controller.vhd             ;
; altsyncram.tdf                   ; yes             ; Megafunction                       ; d:/altera/11.1/quartus/libraries/megafunctions/altsyncram.tdf                                     ;
; stratix_ram_block.inc            ; yes             ; Megafunction                       ; d:/altera/11.1/quartus/libraries/megafunctions/stratix_ram_block.inc                              ;
; lpm_mux.inc                      ; yes             ; Megafunction                       ; d:/altera/11.1/quartus/libraries/megafunctions/lpm_mux.inc                                        ;
; lpm_decode.inc                   ; yes             ; Megafunction                       ; d:/altera/11.1/quartus/libraries/megafunctions/lpm_decode.inc                                     ;
; a_rdenreg.inc                    ; yes             ; Megafunction                       ; d:/altera/11.1/quartus/libraries/megafunctions/a_rdenreg.inc                                      ;
; altrom.inc                       ; yes             ; Megafunction                       ; d:/altera/11.1/quartus/libraries/megafunctions/altrom.inc                                         ;
; altram.inc                       ; yes             ; Megafunction                       ; d:/altera/11.1/quartus/libraries/megafunctions/altram.inc                                         ;
; altdpram.inc                     ; yes             ; Megafunction                       ; d:/altera/11.1/quartus/libraries/megafunctions/altdpram.inc                                       ;
; db/altsyncram_dk01.tdf           ; yes             ; Auto-Generated Megafunction        ; D:/Studium/6.Semester/Programmierbare Logik/APL/Equalizer_20120604/db/altsyncram_dk01.tdf         ;
; db/altsyncram_ek01.tdf           ; yes             ; Auto-Generated Megafunction        ; D:/Studium/6.Semester/Programmierbare Logik/APL/Equalizer_20120604/db/altsyncram_ek01.tdf         ;
; db/altsyncram_fk01.tdf           ; yes             ; Auto-Generated Megafunction        ; D:/Studium/6.Semester/Programmierbare Logik/APL/Equalizer_20120604/db/altsyncram_fk01.tdf         ;
; db/altsyncram_gk01.tdf           ; yes             ; Auto-Generated Megafunction        ; D:/Studium/6.Semester/Programmierbare Logik/APL/Equalizer_20120604/db/altsyncram_gk01.tdf         ;
; db/altsyncram_hk01.tdf           ; yes             ; Auto-Generated Megafunction        ; D:/Studium/6.Semester/Programmierbare Logik/APL/Equalizer_20120604/db/altsyncram_hk01.tdf         ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                                                                     ;
+---------------------------------------------+-------------------------------------------------------------------+
; Resource                                    ; Usage                                                             ;
+---------------------------------------------+-------------------------------------------------------------------+
; Estimated Total logic elements              ; 949                                                               ;
;                                             ;                                                                   ;
; Total combinational functions               ; 907                                                               ;
; Logic element usage by number of LUT inputs ;                                                                   ;
;     -- 4 input functions                    ; 492                                                               ;
;     -- 3 input functions                    ; 101                                                               ;
;     -- <=2 input functions                  ; 314                                                               ;
;                                             ;                                                                   ;
; Logic elements by mode                      ;                                                                   ;
;     -- normal mode                          ; 651                                                               ;
;     -- arithmetic mode                      ; 256                                                               ;
;                                             ;                                                                   ;
; Total registers                             ; 291                                                               ;
;     -- Dedicated logic registers            ; 291                                                               ;
;     -- I/O registers                        ; 0                                                                 ;
;                                             ;                                                                   ;
; I/O pins                                    ; 79                                                                ;
; Total memory bits                           ; 160                                                               ;
; Total PLLs                                  ; 2                                                                 ;
;     -- PLLs                                 ; 2                                                                 ;
;                                             ;                                                                   ;
; Maximum fan-out node                        ; clock_generator:inst3|altpll2:inst2|altpll:altpll_component|_clk0 ;
; Maximum fan-out                             ; 296                                                               ;
; Total fan-out                               ; 4037                                                              ;
; Average fan-out                             ; 3.14                                                              ;
+---------------------------------------------+-------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                       ;
+----------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node                   ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                             ; Library Name ;
+----------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------+--------------+
; |Equalizer                                   ; 907 (0)           ; 291 (0)      ; 160         ; 0            ; 0       ; 0         ; 79   ; 0            ; |Equalizer                                                                                      ;              ;
;    |clock_generator:inst3|                   ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Equalizer|clock_generator:inst3                                                                ;              ;
;       |altpll0:inst|                         ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Equalizer|clock_generator:inst3|altpll0:inst                                                   ;              ;
;          |altpll:altpll_component|           ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Equalizer|clock_generator:inst3|altpll0:inst|altpll:altpll_component                           ;              ;
;       |altpll2:inst2|                        ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Equalizer|clock_generator:inst3|altpll2:inst2                                                  ;              ;
;          |altpll:altpll_component|           ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Equalizer|clock_generator:inst3|altpll2:inst2|altpll:altpll_component                          ;              ;
;    |mmi:inst2|                               ; 907 (0)           ; 291 (0)      ; 160         ; 0            ; 0       ; 0         ; 0    ; 0            ; |Equalizer|mmi:inst2                                                                            ;              ;
;       |lcd_controller:inst2|                 ; 111 (111)         ; 34 (34)      ; 160         ; 0            ; 0       ; 0         ; 0    ; 0            ; |Equalizer|mmi:inst2|lcd_controller:inst2                                                       ;              ;
;          |altsyncram:Mux10_rtl_0|            ; 0 (0)             ; 0 (0)        ; 32          ; 0            ; 0       ; 0         ; 0    ; 0            ; |Equalizer|mmi:inst2|lcd_controller:inst2|altsyncram:Mux10_rtl_0                                ;              ;
;             |altsyncram_gk01:auto_generated| ; 0 (0)             ; 0 (0)        ; 32          ; 0            ; 0       ; 0         ; 0    ; 0            ; |Equalizer|mmi:inst2|lcd_controller:inst2|altsyncram:Mux10_rtl_0|altsyncram_gk01:auto_generated ;              ;
;          |altsyncram:Mux11_rtl_0|            ; 0 (0)             ; 0 (0)        ; 32          ; 0            ; 0       ; 0         ; 0    ; 0            ; |Equalizer|mmi:inst2|lcd_controller:inst2|altsyncram:Mux11_rtl_0                                ;              ;
;             |altsyncram_fk01:auto_generated| ; 0 (0)             ; 0 (0)        ; 32          ; 0            ; 0       ; 0         ; 0    ; 0            ; |Equalizer|mmi:inst2|lcd_controller:inst2|altsyncram:Mux11_rtl_0|altsyncram_fk01:auto_generated ;              ;
;          |altsyncram:Mux12_rtl_0|            ; 0 (0)             ; 0 (0)        ; 32          ; 0            ; 0       ; 0         ; 0    ; 0            ; |Equalizer|mmi:inst2|lcd_controller:inst2|altsyncram:Mux12_rtl_0                                ;              ;
;             |altsyncram_ek01:auto_generated| ; 0 (0)             ; 0 (0)        ; 32          ; 0            ; 0       ; 0         ; 0    ; 0            ; |Equalizer|mmi:inst2|lcd_controller:inst2|altsyncram:Mux12_rtl_0|altsyncram_ek01:auto_generated ;              ;
;          |altsyncram:Mux13_rtl_0|            ; 0 (0)             ; 0 (0)        ; 32          ; 0            ; 0       ; 0         ; 0    ; 0            ; |Equalizer|mmi:inst2|lcd_controller:inst2|altsyncram:Mux13_rtl_0                                ;              ;
;             |altsyncram_dk01:auto_generated| ; 0 (0)             ; 0 (0)        ; 32          ; 0            ; 0       ; 0         ; 0    ; 0            ; |Equalizer|mmi:inst2|lcd_controller:inst2|altsyncram:Mux13_rtl_0|altsyncram_dk01:auto_generated ;              ;
;          |altsyncram:Mux9_rtl_0|             ; 0 (0)             ; 0 (0)        ; 32          ; 0            ; 0       ; 0         ; 0    ; 0            ; |Equalizer|mmi:inst2|lcd_controller:inst2|altsyncram:Mux9_rtl_0                                 ;              ;
;             |altsyncram_hk01:auto_generated| ; 0 (0)             ; 0 (0)        ; 32          ; 0            ; 0       ; 0         ; 0    ; 0            ; |Equalizer|mmi:inst2|lcd_controller:inst2|altsyncram:Mux9_rtl_0|altsyncram_hk01:auto_generated  ;              ;
;       |mmi_controller:inst|                  ; 796 (796)         ; 257 (257)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Equalizer|mmi:inst2|mmi_controller:inst                                                        ;              ;
+----------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                                                ;
+-------------------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+------------------------------+
; Name                                                                                            ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF                          ;
+-------------------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+------------------------------+
; mmi:inst2|lcd_controller:inst2|altsyncram:Mux10_rtl_0|altsyncram_gk01:auto_generated|ALTSYNCRAM ; AUTO ; ROM  ; 32           ; 1            ; --           ; --           ; 32   ; Equalizer.Equalizer3.rtl.mif ;
; mmi:inst2|lcd_controller:inst2|altsyncram:Mux11_rtl_0|altsyncram_fk01:auto_generated|ALTSYNCRAM ; AUTO ; ROM  ; 32           ; 1            ; --           ; --           ; 32   ; Equalizer.Equalizer2.rtl.mif ;
; mmi:inst2|lcd_controller:inst2|altsyncram:Mux12_rtl_0|altsyncram_ek01:auto_generated|ALTSYNCRAM ; AUTO ; ROM  ; 32           ; 1            ; --           ; --           ; 32   ; Equalizer.Equalizer1.rtl.mif ;
; mmi:inst2|lcd_controller:inst2|altsyncram:Mux13_rtl_0|altsyncram_dk01:auto_generated|ALTSYNCRAM ; AUTO ; ROM  ; 32           ; 1            ; --           ; --           ; 32   ; Equalizer.Equalizer0.rtl.mif ;
; mmi:inst2|lcd_controller:inst2|altsyncram:Mux9_rtl_0|altsyncram_hk01:auto_generated|ALTSYNCRAM  ; AUTO ; ROM  ; 32           ; 1            ; --           ; --           ; 32   ; Equalizer.Equalizer4.rtl.mif ;
+-------------------------------------------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary                                                                                                                                                           ;
+--------+--------------+---------+--------------+--------------+------------------------------------------------+--------------------------------------------------------------------------------+
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance                                ; IP Include File                                                                ;
+--------+--------------+---------+--------------+--------------+------------------------------------------------+--------------------------------------------------------------------------------+
; Altera ; ALTPLL       ; 11.1    ; N/A          ; N/A          ; |Equalizer|clock_generator:inst3|altpll0:inst  ; D:/Studium/6.Semester/Programmierbare Logik/APL/Equalizer_20120604/altpll0.vhd ;
; Altera ; ALTPLL       ; 11.1    ; N/A          ; N/A          ; |Equalizer|clock_generator:inst3|altpll2:inst2 ; D:/Studium/6.Semester/Programmierbare Logik/APL/Equalizer_20120604/altpll2.vhd ;
+--------+--------------+---------+--------------+--------------+------------------------------------------------+--------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                                                      ;
+-----------------------------------------------------------+---------------------------------------------+
; Register name                                             ; Reason for Removal                          ;
+-----------------------------------------------------------+---------------------------------------------+
; mmi:inst2|mmi_controller:inst|lcd_1[0,3,7]                ; Stuck at GND due to stuck port data_in      ;
; mmi:inst2|mmi_controller:inst|lcd_1[8]                    ; Stuck at VCC due to stuck port data_in      ;
; mmi:inst2|lcd_controller:inst2|stop                       ; Stuck at GND due to stuck port clock_enable ;
; clock_generator:inst3|audio_clock_divider:inst1|c1M[0,1]  ; Stuck at GND due to stuck port data_in      ;
; clock_generator:inst3|audio_clock_divider:inst1|c1M[2..9] ; Lost fanout                                 ;
; mmi:inst2|lcd_controller:inst2|counter[5..7]              ; Stuck at GND due to stuck port data_in      ;
; mmi:inst2|mmi_controller:inst|lcd_2[7]                    ; Stuck at GND due to stuck port data_in      ;
; mmi:inst2|mmi_controller:inst|lcd_3[7]                    ; Stuck at GND due to stuck port data_in      ;
; clock_generator:inst3|audio_clock_divider:inst1|clk_1MHz  ; Stuck at GND due to stuck port data_in      ;
; audio_unit:inst|i2c_data_register:inst4|counter[0,1]      ; Stuck at GND due to stuck port clock        ;
; audio_unit:inst|i2c_data_register:inst4|index[0..3]       ; Stuck at GND due to stuck port clock        ;
; audio_unit:inst|i2c_data_register:inst4|start             ; Stuck at GND due to stuck port clock        ;
; audio_unit:inst|i2c_data_register:inst4|data[0..23]       ; Stuck at GND due to stuck port clock        ;
; audio_unit:inst|i2c_transmitter:inst|ready                ; Stuck at VCC due to stuck port clock        ;
; audio_unit:inst|i2c_transmitter:inst|sclk                 ; Stuck at GND due to stuck port clock        ;
; audio_unit:inst|i2c_transmitter:inst|sdin~reg0            ; Stuck at GND due to stuck port clock        ;
; audio_unit:inst|i2c_transmitter:inst|sdin~en              ; Stuck at GND due to stuck port clock        ;
; audio_unit:inst|i2c_transmitter:inst|counter[0..7]        ; Stuck at GND due to stuck port clock        ;
; audio_unit:inst|i2c_transmitter:inst|sd[0..23]            ; Stuck at GND due to stuck port clock        ;
; mmi:inst2|mmi_controller:inst|lcd_2[8]                    ; Stuck at VCC due to stuck port data_in      ;
; mmi:inst2|mmi_controller:inst|lcd_3[8]                    ; Stuck at VCC due to stuck port data_in      ;
; mmi:inst2|mmi_controller:inst|lcd_4[8]                    ; Stuck at VCC due to stuck port data_in      ;
; mmi:inst2|mmi_controller:inst|lcd_5[8]                    ; Stuck at VCC due to stuck port data_in      ;
; mmi:inst2|mmi_controller:inst|lcd_6[8]                    ; Stuck at VCC due to stuck port data_in      ;
; mmi:inst2|mmi_controller:inst|lcd_2[5]                    ; Stuck at VCC due to stuck port data_in      ;
; mmi:inst2|mmi_controller:inst|lcd_3[5]                    ; Stuck at VCC due to stuck port data_in      ;
; mmi:inst2|mmi_controller:inst|lcd_4[5]                    ; Stuck at VCC due to stuck port data_in      ;
; mmi:inst2|mmi_controller:inst|lcd_5[5]                    ; Stuck at VCC due to stuck port data_in      ;
; mmi:inst2|mmi_controller:inst|lcd_6[5]                    ; Stuck at VCC due to stuck port data_in      ;
; mmi:inst2|mmi_controller:inst|lcd_4[7]                    ; Stuck at GND due to stuck port data_in      ;
; mmi:inst2|mmi_controller:inst|lcd_5[7]                    ; Stuck at GND due to stuck port data_in      ;
; mmi:inst2|mmi_controller:inst|lcd_6[7]                    ; Stuck at GND due to stuck port data_in      ;
; mmi:inst2|mmi_controller:inst|lcd_4[6]                    ; Stuck at GND due to stuck port data_in      ;
; mmi:inst2|mmi_controller:inst|lcd_5[6]                    ; Stuck at GND due to stuck port data_in      ;
; mmi:inst2|mmi_controller:inst|lcd_6[6]                    ; Stuck at GND due to stuck port data_in      ;
; mmi:inst2|mmi_controller:inst|lcd_4[4]                    ; Stuck at GND due to stuck port data_in      ;
; mmi:inst2|mmi_controller:inst|lcd_5[3]                    ; Stuck at GND due to stuck port data_in      ;
; mmi:inst2|mmi_controller:inst|lcd_4[1]                    ; Stuck at GND due to stuck port data_in      ;
; Total Number of Removed Registers = 107                   ;                                             ;
+-----------------------------------------------------------+---------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations                                                                                ;
+----------------------------------------------------------+---------------------------+-----------------------------------------------------+
; Register name                                            ; Reason for Removal        ; Registers Removed due to This Register              ;
+----------------------------------------------------------+---------------------------+-----------------------------------------------------+
; clock_generator:inst3|audio_clock_divider:inst1|clk_1MHz ; Stuck at GND              ; audio_unit:inst|i2c_data_register:inst4|counter[0], ;
;                                                          ; due to stuck port data_in ; audio_unit:inst|i2c_data_register:inst4|counter[1], ;
;                                                          ;                           ; audio_unit:inst|i2c_data_register:inst4|index[0],   ;
;                                                          ;                           ; audio_unit:inst|i2c_data_register:inst4|index[1],   ;
;                                                          ;                           ; audio_unit:inst|i2c_data_register:inst4|index[2],   ;
;                                                          ;                           ; audio_unit:inst|i2c_data_register:inst4|index[3],   ;
;                                                          ;                           ; audio_unit:inst|i2c_data_register:inst4|start,      ;
;                                                          ;                           ; audio_unit:inst|i2c_data_register:inst4|data[0],    ;
;                                                          ;                           ; audio_unit:inst|i2c_data_register:inst4|data[1],    ;
;                                                          ;                           ; audio_unit:inst|i2c_data_register:inst4|data[2],    ;
;                                                          ;                           ; audio_unit:inst|i2c_data_register:inst4|data[3],    ;
;                                                          ;                           ; audio_unit:inst|i2c_data_register:inst4|data[4],    ;
;                                                          ;                           ; audio_unit:inst|i2c_data_register:inst4|data[5],    ;
;                                                          ;                           ; audio_unit:inst|i2c_data_register:inst4|data[6],    ;
;                                                          ;                           ; audio_unit:inst|i2c_data_register:inst4|data[7],    ;
;                                                          ;                           ; audio_unit:inst|i2c_data_register:inst4|data[8],    ;
;                                                          ;                           ; audio_unit:inst|i2c_data_register:inst4|data[9],    ;
;                                                          ;                           ; audio_unit:inst|i2c_data_register:inst4|data[10],   ;
;                                                          ;                           ; audio_unit:inst|i2c_data_register:inst4|data[11],   ;
;                                                          ;                           ; audio_unit:inst|i2c_data_register:inst4|data[12],   ;
;                                                          ;                           ; audio_unit:inst|i2c_data_register:inst4|data[13],   ;
;                                                          ;                           ; audio_unit:inst|i2c_data_register:inst4|data[14],   ;
;                                                          ;                           ; audio_unit:inst|i2c_data_register:inst4|data[15],   ;
;                                                          ;                           ; audio_unit:inst|i2c_data_register:inst4|data[16],   ;
;                                                          ;                           ; audio_unit:inst|i2c_data_register:inst4|data[17],   ;
;                                                          ;                           ; audio_unit:inst|i2c_data_register:inst4|data[18],   ;
;                                                          ;                           ; audio_unit:inst|i2c_data_register:inst4|data[19],   ;
;                                                          ;                           ; audio_unit:inst|i2c_data_register:inst4|data[20],   ;
;                                                          ;                           ; audio_unit:inst|i2c_data_register:inst4|data[21],   ;
;                                                          ;                           ; audio_unit:inst|i2c_data_register:inst4|data[22],   ;
;                                                          ;                           ; audio_unit:inst|i2c_data_register:inst4|data[23],   ;
;                                                          ;                           ; audio_unit:inst|i2c_transmitter:inst|ready,         ;
;                                                          ;                           ; audio_unit:inst|i2c_transmitter:inst|sclk,          ;
;                                                          ;                           ; audio_unit:inst|i2c_transmitter:inst|sdin~reg0,     ;
;                                                          ;                           ; audio_unit:inst|i2c_transmitter:inst|sdin~en,       ;
;                                                          ;                           ; audio_unit:inst|i2c_transmitter:inst|counter[0],    ;
;                                                          ;                           ; audio_unit:inst|i2c_transmitter:inst|counter[1],    ;
;                                                          ;                           ; audio_unit:inst|i2c_transmitter:inst|counter[2],    ;
;                                                          ;                           ; audio_unit:inst|i2c_transmitter:inst|counter[3],    ;
;                                                          ;                           ; audio_unit:inst|i2c_transmitter:inst|counter[4],    ;
;                                                          ;                           ; audio_unit:inst|i2c_transmitter:inst|counter[5],    ;
;                                                          ;                           ; audio_unit:inst|i2c_transmitter:inst|counter[6],    ;
;                                                          ;                           ; audio_unit:inst|i2c_transmitter:inst|counter[7],    ;
;                                                          ;                           ; audio_unit:inst|i2c_transmitter:inst|sd[0],         ;
;                                                          ;                           ; audio_unit:inst|i2c_transmitter:inst|sd[1],         ;
;                                                          ;                           ; audio_unit:inst|i2c_transmitter:inst|sd[2],         ;
;                                                          ;                           ; audio_unit:inst|i2c_transmitter:inst|sd[3],         ;
;                                                          ;                           ; audio_unit:inst|i2c_transmitter:inst|sd[4],         ;
;                                                          ;                           ; audio_unit:inst|i2c_transmitter:inst|sd[5],         ;
;                                                          ;                           ; audio_unit:inst|i2c_transmitter:inst|sd[6],         ;
;                                                          ;                           ; audio_unit:inst|i2c_transmitter:inst|sd[7],         ;
;                                                          ;                           ; audio_unit:inst|i2c_transmitter:inst|sd[8],         ;
;                                                          ;                           ; audio_unit:inst|i2c_transmitter:inst|sd[9],         ;
;                                                          ;                           ; audio_unit:inst|i2c_transmitter:inst|sd[10],        ;
;                                                          ;                           ; audio_unit:inst|i2c_transmitter:inst|sd[11],        ;
;                                                          ;                           ; audio_unit:inst|i2c_transmitter:inst|sd[12],        ;
;                                                          ;                           ; audio_unit:inst|i2c_transmitter:inst|sd[13],        ;
;                                                          ;                           ; audio_unit:inst|i2c_transmitter:inst|sd[14],        ;
;                                                          ;                           ; audio_unit:inst|i2c_transmitter:inst|sd[15],        ;
;                                                          ;                           ; audio_unit:inst|i2c_transmitter:inst|sd[16],        ;
;                                                          ;                           ; audio_unit:inst|i2c_transmitter:inst|sd[17],        ;
;                                                          ;                           ; audio_unit:inst|i2c_transmitter:inst|sd[18],        ;
;                                                          ;                           ; audio_unit:inst|i2c_transmitter:inst|sd[19],        ;
;                                                          ;                           ; audio_unit:inst|i2c_transmitter:inst|sd[20],        ;
;                                                          ;                           ; audio_unit:inst|i2c_transmitter:inst|sd[21],        ;
;                                                          ;                           ; audio_unit:inst|i2c_transmitter:inst|sd[22],        ;
;                                                          ;                           ; audio_unit:inst|i2c_transmitter:inst|sd[23]         ;
+----------------------------------------------------------+---------------------------+-----------------------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 291   ;
; Number of registers using Synchronous Clear  ; 28    ;
; Number of registers using Synchronous Load   ; 147   ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 208   ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+---------------------------------------------------+
; Inverted Register Statistics                      ;
+-----------------------------------------+---------+
; Inverted Register                       ; Fan out ;
+-----------------------------------------+---------+
; mmi:inst2|lcd_controller:inst2|start    ; 1       ;
; mmi:inst2|mmi_controller:inst|filter[0] ; 18      ;
; mmi:inst2|mmi_controller:inst|lcd_1[5]  ; 1       ;
; Total number of inverted registers = 3  ;         ;
+-----------------------------------------+---------+


+-----------------------------------------------------------------------------------------------+
; Registers Packed Into Inferred Megafunctions                                                  ;
+-------------------------------------------+--------------------------------------------+------+
; Register Name                             ; Megafunction                               ; Type ;
+-------------------------------------------+--------------------------------------------+------+
; mmi:inst2|lcd_controller:inst2|counter[0] ; mmi:inst2|lcd_controller:inst2|Mux13_rtl_0 ; ROM  ;
; mmi:inst2|lcd_controller:inst2|counter[1] ; mmi:inst2|lcd_controller:inst2|Mux12_rtl_0 ; ROM  ;
; mmi:inst2|lcd_controller:inst2|counter[2] ; mmi:inst2|lcd_controller:inst2|Mux11_rtl_0 ; ROM  ;
; mmi:inst2|lcd_controller:inst2|counter[3] ; mmi:inst2|lcd_controller:inst2|Mux10_rtl_0 ; ROM  ;
; mmi:inst2|lcd_controller:inst2|counter[4] ; mmi:inst2|lcd_controller:inst2|Mux9_rtl_0  ; ROM  ;
+-------------------------------------------+--------------------------------------------+------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                       ;
+--------------------+-----------+---------------+----------------------+------------------------+--------------------------------------------------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered                                             ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+--------------------------------------------------------+----------------------------+
; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; |Equalizer|mmi:inst2|mmi_controller:inst|filter_ten[6] ;                            ;
; 3:1                ; 7 bits    ; 14 LEs        ; 7 LEs                ; 7 LEs                  ; |Equalizer|mmi:inst2|mmi_controller:inst|lcd_2[1]      ;                            ;
; 5:1                ; 13 bits   ; 39 LEs        ; 26 LEs               ; 13 LEs                 ; |Equalizer|mmi:inst2|mmi_controller:inst|filter[10]    ;                            ;
; 6:1                ; 8 bits    ; 32 LEs        ; 8 LEs                ; 24 LEs                 ; |Equalizer|mmi:inst2|mmi_controller:inst|vol_db[2]     ;                            ;
; 6:1                ; 8 bits    ; 32 LEs        ; 8 LEs                ; 24 LEs                 ; |Equalizer|mmi:inst2|mmi_controller:inst|f1_db[3]      ;                            ;
; 6:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; |Equalizer|mmi:inst2|mmi_controller:inst|f2_db[3]      ;                            ;
; 6:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; |Equalizer|mmi:inst2|mmi_controller:inst|f3_db[3]      ;                            ;
; 6:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; |Equalizer|mmi:inst2|mmi_controller:inst|f4_db[7]      ;                            ;
; 6:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; |Equalizer|mmi:inst2|mmi_controller:inst|f5_db[7]      ;                            ;
; 6:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; |Equalizer|mmi:inst2|mmi_controller:inst|f6_db[2]      ;                            ;
; 6:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; |Equalizer|mmi:inst2|mmi_controller:inst|f7_db[2]      ;                            ;
; 6:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; |Equalizer|mmi:inst2|mmi_controller:inst|f8_db[4]      ;                            ;
; 6:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; |Equalizer|mmi:inst2|mmi_controller:inst|f9_db[2]      ;                            ;
; 6:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; |Equalizer|mmi:inst2|mmi_controller:inst|f10_db[1]     ;                            ;
; 6:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; |Equalizer|mmi:inst2|mmi_controller:inst|f11_db[6]     ;                            ;
; 6:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; |Equalizer|mmi:inst2|mmi_controller:inst|f12_db[5]     ;                            ;
; 6:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; |Equalizer|mmi:inst2|mmi_controller:inst|f13_db[3]     ;                            ;
; 6:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; |Equalizer|mmi:inst2|mmi_controller:inst|f14_db[5]     ;                            ;
; 10:1               ; 3 bits    ; 18 LEs        ; 15 LEs               ; 3 LEs                  ; |Equalizer|mmi:inst2|lcd_controller:inst2|index[2]     ;                            ;
; 32:1               ; 3 bits    ; 63 LEs        ; 36 LEs               ; 27 LEs                 ; |Equalizer|mmi:inst2|lcd_controller:inst2|output[3]    ;                            ;
; 32:1               ; 5 bits    ; 105 LEs       ; 70 LEs               ; 35 LEs                 ; |Equalizer|mmi:inst2|lcd_controller:inst2|output[6]    ;                            ;
; 11:1               ; 20 bits   ; 140 LEs       ; 20 LEs               ; 120 LEs                ; |Equalizer|mmi:inst2|lcd_controller:inst2|delay[2]     ;                            ;
; 256:1              ; 21 bits   ; 3570 LEs      ; 840 LEs              ; 2730 LEs               ; |Equalizer|mmi:inst2|mmi_controller:inst|lcd_4[6]      ;                            ;
; 257:1              ; 14 bits   ; 2394 LEs      ; 560 LEs              ; 1834 LEs               ; |Equalizer|mmi:inst2|mmi_controller:inst|db_ones[0]    ;                            ;
; 3:1                ; 4 bits    ; 8 LEs         ; 0 LEs                ; 8 LEs                  ; |Equalizer|mmi:inst2|mmi_controller:inst|lcd_2[8]      ;                            ;
; 256:1              ; 6 bits    ; 1020 LEs      ; 0 LEs                ; 1020 LEs               ; |Equalizer|mmi:inst2|mmi_controller:inst|lcd_6[5]      ;                            ;
; 16:1               ; 8 bits    ; 80 LEs        ; 80 LEs               ; 0 LEs                  ; |Equalizer|mmi:inst2|mmi_controller:inst|Selector0     ;                            ;
; 16:1               ; 8 bits    ; 80 LEs        ; 80 LEs               ; 0 LEs                  ; |Equalizer|mmi:inst2|mmi_controller:inst|tmp           ;                            ;
+--------------------+-----------+---------------+----------------------+------------------------+--------------------------------------------------------+----------------------------+


+-------------------------------------------------------------------------------------------------------------+
; Source assignments for mmi:inst2|lcd_controller:inst2|altsyncram:Mux13_rtl_0|altsyncram_dk01:auto_generated ;
+---------------------------------+-------+------+------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                         ;
+---------------------------------+-------+------+------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; OFF   ; -    ; -                                                          ;
+---------------------------------+-------+------+------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------+
; Source assignments for mmi:inst2|lcd_controller:inst2|altsyncram:Mux12_rtl_0|altsyncram_ek01:auto_generated ;
+---------------------------------+-------+------+------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                         ;
+---------------------------------+-------+------+------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; OFF   ; -    ; -                                                          ;
+---------------------------------+-------+------+------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------+
; Source assignments for mmi:inst2|lcd_controller:inst2|altsyncram:Mux11_rtl_0|altsyncram_fk01:auto_generated ;
+---------------------------------+-------+------+------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                         ;
+---------------------------------+-------+------+------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; OFF   ; -    ; -                                                          ;
+---------------------------------+-------+------+------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------+
; Source assignments for mmi:inst2|lcd_controller:inst2|altsyncram:Mux10_rtl_0|altsyncram_gk01:auto_generated ;
+---------------------------------+-------+------+------------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                         ;
+---------------------------------+-------+------+------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; OFF   ; -    ; -                                                          ;
+---------------------------------+-------+------+------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------+
; Source assignments for mmi:inst2|lcd_controller:inst2|altsyncram:Mux9_rtl_0|altsyncram_hk01:auto_generated ;
+---------------------------------+-------+------+-----------------------------------------------------------+
; Assignment                      ; Value ; From ; To                                                        ;
+---------------------------------+-------+------+-----------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; OFF   ; -    ; -                                                         ;
+---------------------------------+-------+------+-----------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: clock_generator:inst3|altpll0:inst|altpll:altpll_component ;
+-------------------------------+---------------------------+---------------------------------------------+
; Parameter Name                ; Value                     ; Type                                        ;
+-------------------------------+---------------------------+---------------------------------------------+
; OPERATION_MODE                ; NO_COMPENSATION           ; Untyped                                     ;
; PLL_TYPE                      ; AUTO                      ; Untyped                                     ;
; LPM_HINT                      ; CBX_MODULE_PREFIX=altpll0 ; Untyped                                     ;
; QUALIFY_CONF_DONE             ; OFF                       ; Untyped                                     ;
; COMPENSATE_CLOCK              ; CLK0                      ; Untyped                                     ;
; SCAN_CHAIN                    ; LONG                      ; Untyped                                     ;
; PRIMARY_CLOCK                 ; INCLK0                    ; Untyped                                     ;
; INCLK0_INPUT_FREQUENCY        ; 37037                     ; Signed Integer                              ;
; INCLK1_INPUT_FREQUENCY        ; 0                         ; Untyped                                     ;
; GATE_LOCK_SIGNAL              ; NO                        ; Untyped                                     ;
; GATE_LOCK_COUNTER             ; 0                         ; Untyped                                     ;
; LOCK_HIGH                     ; 1                         ; Untyped                                     ;
; LOCK_LOW                      ; 1                         ; Untyped                                     ;
; VALID_LOCK_MULTIPLIER         ; 1                         ; Untyped                                     ;
; INVALID_LOCK_MULTIPLIER       ; 5                         ; Untyped                                     ;
; SWITCH_OVER_ON_LOSSCLK        ; OFF                       ; Untyped                                     ;
; SWITCH_OVER_ON_GATED_LOCK     ; OFF                       ; Untyped                                     ;
; ENABLE_SWITCH_OVER_COUNTER    ; OFF                       ; Untyped                                     ;
; SKIP_VCO                      ; OFF                       ; Untyped                                     ;
; SWITCH_OVER_COUNTER           ; 0                         ; Untyped                                     ;
; SWITCH_OVER_TYPE              ; AUTO                      ; Untyped                                     ;
; FEEDBACK_SOURCE               ; EXTCLK0                   ; Untyped                                     ;
; BANDWIDTH                     ; 0                         ; Untyped                                     ;
; BANDWIDTH_TYPE                ; AUTO                      ; Untyped                                     ;
; SPREAD_FREQUENCY              ; 0                         ; Untyped                                     ;
; DOWN_SPREAD                   ; 0                         ; Untyped                                     ;
; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF                       ; Untyped                                     ;
; SELF_RESET_ON_LOSS_LOCK       ; OFF                       ; Untyped                                     ;
; CLK9_MULTIPLY_BY              ; 0                         ; Untyped                                     ;
; CLK8_MULTIPLY_BY              ; 0                         ; Untyped                                     ;
; CLK7_MULTIPLY_BY              ; 0                         ; Untyped                                     ;
; CLK6_MULTIPLY_BY              ; 0                         ; Untyped                                     ;
; CLK5_MULTIPLY_BY              ; 1                         ; Untyped                                     ;
; CLK4_MULTIPLY_BY              ; 1                         ; Untyped                                     ;
; CLK3_MULTIPLY_BY              ; 1                         ; Untyped                                     ;
; CLK2_MULTIPLY_BY              ; 1                         ; Untyped                                     ;
; CLK1_MULTIPLY_BY              ; 1                         ; Untyped                                     ;
; CLK0_MULTIPLY_BY              ; 4                         ; Signed Integer                              ;
; CLK9_DIVIDE_BY                ; 0                         ; Untyped                                     ;
; CLK8_DIVIDE_BY                ; 0                         ; Untyped                                     ;
; CLK7_DIVIDE_BY                ; 0                         ; Untyped                                     ;
; CLK6_DIVIDE_BY                ; 0                         ; Untyped                                     ;
; CLK5_DIVIDE_BY                ; 1                         ; Untyped                                     ;
; CLK4_DIVIDE_BY                ; 1                         ; Untyped                                     ;
; CLK3_DIVIDE_BY                ; 1                         ; Untyped                                     ;
; CLK2_DIVIDE_BY                ; 1                         ; Untyped                                     ;
; CLK1_DIVIDE_BY                ; 1                         ; Untyped                                     ;
; CLK0_DIVIDE_BY                ; 9                         ; Signed Integer                              ;
; CLK9_PHASE_SHIFT              ; 0                         ; Untyped                                     ;
; CLK8_PHASE_SHIFT              ; 0                         ; Untyped                                     ;
; CLK7_PHASE_SHIFT              ; 0                         ; Untyped                                     ;
; CLK6_PHASE_SHIFT              ; 0                         ; Untyped                                     ;
; CLK5_PHASE_SHIFT              ; 0                         ; Untyped                                     ;
; CLK4_PHASE_SHIFT              ; 0                         ; Untyped                                     ;
; CLK3_PHASE_SHIFT              ; 0                         ; Untyped                                     ;
; CLK2_PHASE_SHIFT              ; 0                         ; Untyped                                     ;
; CLK1_PHASE_SHIFT              ; 0                         ; Untyped                                     ;
; CLK0_PHASE_SHIFT              ; 0                         ; Untyped                                     ;
; CLK5_TIME_DELAY               ; 0                         ; Untyped                                     ;
; CLK4_TIME_DELAY               ; 0                         ; Untyped                                     ;
; CLK3_TIME_DELAY               ; 0                         ; Untyped                                     ;
; CLK2_TIME_DELAY               ; 0                         ; Untyped                                     ;
; CLK1_TIME_DELAY               ; 0                         ; Untyped                                     ;
; CLK0_TIME_DELAY               ; 0                         ; Untyped                                     ;
; CLK9_DUTY_CYCLE               ; 50                        ; Untyped                                     ;
; CLK8_DUTY_CYCLE               ; 50                        ; Untyped                                     ;
; CLK7_DUTY_CYCLE               ; 50                        ; Untyped                                     ;
; CLK6_DUTY_CYCLE               ; 50                        ; Untyped                                     ;
; CLK5_DUTY_CYCLE               ; 50                        ; Untyped                                     ;
; CLK4_DUTY_CYCLE               ; 50                        ; Untyped                                     ;
; CLK3_DUTY_CYCLE               ; 50                        ; Untyped                                     ;
; CLK2_DUTY_CYCLE               ; 50                        ; Untyped                                     ;
; CLK1_DUTY_CYCLE               ; 50                        ; Untyped                                     ;
; CLK0_DUTY_CYCLE               ; 50                        ; Signed Integer                              ;
; CLK9_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                                     ;
; CLK8_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                                     ;
; CLK7_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                                     ;
; CLK6_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                                     ;
; CLK5_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                                     ;
; CLK4_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                                     ;
; CLK3_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                                     ;
; CLK2_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                                     ;
; CLK1_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                                     ;
; CLK0_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                                     ;
; CLK9_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                                     ;
; CLK8_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                                     ;
; CLK7_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                                     ;
; CLK6_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                                     ;
; CLK5_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                                     ;
; CLK4_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                                     ;
; CLK3_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                                     ;
; CLK2_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                                     ;
; CLK1_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                                     ;
; CLK0_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                                     ;
; LOCK_WINDOW_UI                ;  0.05                     ; Untyped                                     ;
; LOCK_WINDOW_UI_BITS           ; UNUSED                    ; Untyped                                     ;
; VCO_RANGE_DETECTOR_LOW_BITS   ; UNUSED                    ; Untyped                                     ;
; VCO_RANGE_DETECTOR_HIGH_BITS  ; UNUSED                    ; Untyped                                     ;
; DPA_MULTIPLY_BY               ; 0                         ; Untyped                                     ;
; DPA_DIVIDE_BY                 ; 1                         ; Untyped                                     ;
; DPA_DIVIDER                   ; 0                         ; Untyped                                     ;
; EXTCLK3_MULTIPLY_BY           ; 1                         ; Untyped                                     ;
; EXTCLK2_MULTIPLY_BY           ; 1                         ; Untyped                                     ;
; EXTCLK1_MULTIPLY_BY           ; 1                         ; Untyped                                     ;
; EXTCLK0_MULTIPLY_BY           ; 1                         ; Untyped                                     ;
; EXTCLK3_DIVIDE_BY             ; 1                         ; Untyped                                     ;
; EXTCLK2_DIVIDE_BY             ; 1                         ; Untyped                                     ;
; EXTCLK1_DIVIDE_BY             ; 1                         ; Untyped                                     ;
; EXTCLK0_DIVIDE_BY             ; 1                         ; Untyped                                     ;
; EXTCLK3_PHASE_SHIFT           ; 0                         ; Untyped                                     ;
; EXTCLK2_PHASE_SHIFT           ; 0                         ; Untyped                                     ;
; EXTCLK1_PHASE_SHIFT           ; 0                         ; Untyped                                     ;
; EXTCLK0_PHASE_SHIFT           ; 0                         ; Untyped                                     ;
; EXTCLK3_TIME_DELAY            ; 0                         ; Untyped                                     ;
; EXTCLK2_TIME_DELAY            ; 0                         ; Untyped                                     ;
; EXTCLK1_TIME_DELAY            ; 0                         ; Untyped                                     ;
; EXTCLK0_TIME_DELAY            ; 0                         ; Untyped                                     ;
; EXTCLK3_DUTY_CYCLE            ; 50                        ; Untyped                                     ;
; EXTCLK2_DUTY_CYCLE            ; 50                        ; Untyped                                     ;
; EXTCLK1_DUTY_CYCLE            ; 50                        ; Untyped                                     ;
; EXTCLK0_DUTY_CYCLE            ; 50                        ; Untyped                                     ;
; VCO_MULTIPLY_BY               ; 0                         ; Untyped                                     ;
; VCO_DIVIDE_BY                 ; 0                         ; Untyped                                     ;
; SCLKOUT0_PHASE_SHIFT          ; 0                         ; Untyped                                     ;
; SCLKOUT1_PHASE_SHIFT          ; 0                         ; Untyped                                     ;
; VCO_MIN                       ; 0                         ; Untyped                                     ;
; VCO_MAX                       ; 0                         ; Untyped                                     ;
; VCO_CENTER                    ; 0                         ; Untyped                                     ;
; PFD_MIN                       ; 0                         ; Untyped                                     ;
; PFD_MAX                       ; 0                         ; Untyped                                     ;
; M_INITIAL                     ; 0                         ; Untyped                                     ;
; M                             ; 0                         ; Untyped                                     ;
; N                             ; 1                         ; Untyped                                     ;
; M2                            ; 1                         ; Untyped                                     ;
; N2                            ; 1                         ; Untyped                                     ;
; SS                            ; 1                         ; Untyped                                     ;
; C0_HIGH                       ; 0                         ; Untyped                                     ;
; C1_HIGH                       ; 0                         ; Untyped                                     ;
; C2_HIGH                       ; 0                         ; Untyped                                     ;
; C3_HIGH                       ; 0                         ; Untyped                                     ;
; C4_HIGH                       ; 0                         ; Untyped                                     ;
; C5_HIGH                       ; 0                         ; Untyped                                     ;
; C6_HIGH                       ; 0                         ; Untyped                                     ;
; C7_HIGH                       ; 0                         ; Untyped                                     ;
; C8_HIGH                       ; 0                         ; Untyped                                     ;
; C9_HIGH                       ; 0                         ; Untyped                                     ;
; C0_LOW                        ; 0                         ; Untyped                                     ;
; C1_LOW                        ; 0                         ; Untyped                                     ;
; C2_LOW                        ; 0                         ; Untyped                                     ;
; C3_LOW                        ; 0                         ; Untyped                                     ;
; C4_LOW                        ; 0                         ; Untyped                                     ;
; C5_LOW                        ; 0                         ; Untyped                                     ;
; C6_LOW                        ; 0                         ; Untyped                                     ;
; C7_LOW                        ; 0                         ; Untyped                                     ;
; C8_LOW                        ; 0                         ; Untyped                                     ;
; C9_LOW                        ; 0                         ; Untyped                                     ;
; C0_INITIAL                    ; 0                         ; Untyped                                     ;
; C1_INITIAL                    ; 0                         ; Untyped                                     ;
; C2_INITIAL                    ; 0                         ; Untyped                                     ;
; C3_INITIAL                    ; 0                         ; Untyped                                     ;
; C4_INITIAL                    ; 0                         ; Untyped                                     ;
; C5_INITIAL                    ; 0                         ; Untyped                                     ;
; C6_INITIAL                    ; 0                         ; Untyped                                     ;
; C7_INITIAL                    ; 0                         ; Untyped                                     ;
; C8_INITIAL                    ; 0                         ; Untyped                                     ;
; C9_INITIAL                    ; 0                         ; Untyped                                     ;
; C0_MODE                       ; BYPASS                    ; Untyped                                     ;
; C1_MODE                       ; BYPASS                    ; Untyped                                     ;
; C2_MODE                       ; BYPASS                    ; Untyped                                     ;
; C3_MODE                       ; BYPASS                    ; Untyped                                     ;
; C4_MODE                       ; BYPASS                    ; Untyped                                     ;
; C5_MODE                       ; BYPASS                    ; Untyped                                     ;
; C6_MODE                       ; BYPASS                    ; Untyped                                     ;
; C7_MODE                       ; BYPASS                    ; Untyped                                     ;
; C8_MODE                       ; BYPASS                    ; Untyped                                     ;
; C9_MODE                       ; BYPASS                    ; Untyped                                     ;
; C0_PH                         ; 0                         ; Untyped                                     ;
; C1_PH                         ; 0                         ; Untyped                                     ;
; C2_PH                         ; 0                         ; Untyped                                     ;
; C3_PH                         ; 0                         ; Untyped                                     ;
; C4_PH                         ; 0                         ; Untyped                                     ;
; C5_PH                         ; 0                         ; Untyped                                     ;
; C6_PH                         ; 0                         ; Untyped                                     ;
; C7_PH                         ; 0                         ; Untyped                                     ;
; C8_PH                         ; 0                         ; Untyped                                     ;
; C9_PH                         ; 0                         ; Untyped                                     ;
; L0_HIGH                       ; 1                         ; Untyped                                     ;
; L1_HIGH                       ; 1                         ; Untyped                                     ;
; G0_HIGH                       ; 1                         ; Untyped                                     ;
; G1_HIGH                       ; 1                         ; Untyped                                     ;
; G2_HIGH                       ; 1                         ; Untyped                                     ;
; G3_HIGH                       ; 1                         ; Untyped                                     ;
; E0_HIGH                       ; 1                         ; Untyped                                     ;
; E1_HIGH                       ; 1                         ; Untyped                                     ;
; E2_HIGH                       ; 1                         ; Untyped                                     ;
; E3_HIGH                       ; 1                         ; Untyped                                     ;
; L0_LOW                        ; 1                         ; Untyped                                     ;
; L1_LOW                        ; 1                         ; Untyped                                     ;
; G0_LOW                        ; 1                         ; Untyped                                     ;
; G1_LOW                        ; 1                         ; Untyped                                     ;
; G2_LOW                        ; 1                         ; Untyped                                     ;
; G3_LOW                        ; 1                         ; Untyped                                     ;
; E0_LOW                        ; 1                         ; Untyped                                     ;
; E1_LOW                        ; 1                         ; Untyped                                     ;
; E2_LOW                        ; 1                         ; Untyped                                     ;
; E3_LOW                        ; 1                         ; Untyped                                     ;
; L0_INITIAL                    ; 1                         ; Untyped                                     ;
; L1_INITIAL                    ; 1                         ; Untyped                                     ;
; G0_INITIAL                    ; 1                         ; Untyped                                     ;
; G1_INITIAL                    ; 1                         ; Untyped                                     ;
; G2_INITIAL                    ; 1                         ; Untyped                                     ;
; G3_INITIAL                    ; 1                         ; Untyped                                     ;
; E0_INITIAL                    ; 1                         ; Untyped                                     ;
; E1_INITIAL                    ; 1                         ; Untyped                                     ;
; E2_INITIAL                    ; 1                         ; Untyped                                     ;
; E3_INITIAL                    ; 1                         ; Untyped                                     ;
; L0_MODE                       ; BYPASS                    ; Untyped                                     ;
; L1_MODE                       ; BYPASS                    ; Untyped                                     ;
; G0_MODE                       ; BYPASS                    ; Untyped                                     ;
; G1_MODE                       ; BYPASS                    ; Untyped                                     ;
; G2_MODE                       ; BYPASS                    ; Untyped                                     ;
; G3_MODE                       ; BYPASS                    ; Untyped                                     ;
; E0_MODE                       ; BYPASS                    ; Untyped                                     ;
; E1_MODE                       ; BYPASS                    ; Untyped                                     ;
; E2_MODE                       ; BYPASS                    ; Untyped                                     ;
; E3_MODE                       ; BYPASS                    ; Untyped                                     ;
; L0_PH                         ; 0                         ; Untyped                                     ;
; L1_PH                         ; 0                         ; Untyped                                     ;
; G0_PH                         ; 0                         ; Untyped                                     ;
; G1_PH                         ; 0                         ; Untyped                                     ;
; G2_PH                         ; 0                         ; Untyped                                     ;
; G3_PH                         ; 0                         ; Untyped                                     ;
; E0_PH                         ; 0                         ; Untyped                                     ;
; E1_PH                         ; 0                         ; Untyped                                     ;
; E2_PH                         ; 0                         ; Untyped                                     ;
; E3_PH                         ; 0                         ; Untyped                                     ;
; M_PH                          ; 0                         ; Untyped                                     ;
; C1_USE_CASC_IN                ; OFF                       ; Untyped                                     ;
; C2_USE_CASC_IN                ; OFF                       ; Untyped                                     ;
; C3_USE_CASC_IN                ; OFF                       ; Untyped                                     ;
; C4_USE_CASC_IN                ; OFF                       ; Untyped                                     ;
; C5_USE_CASC_IN                ; OFF                       ; Untyped                                     ;
; C6_USE_CASC_IN                ; OFF                       ; Untyped                                     ;
; C7_USE_CASC_IN                ; OFF                       ; Untyped                                     ;
; C8_USE_CASC_IN                ; OFF                       ; Untyped                                     ;
; C9_USE_CASC_IN                ; OFF                       ; Untyped                                     ;
; CLK0_COUNTER                  ; G0                        ; Untyped                                     ;
; CLK1_COUNTER                  ; G0                        ; Untyped                                     ;
; CLK2_COUNTER                  ; G0                        ; Untyped                                     ;
; CLK3_COUNTER                  ; G0                        ; Untyped                                     ;
; CLK4_COUNTER                  ; G0                        ; Untyped                                     ;
; CLK5_COUNTER                  ; G0                        ; Untyped                                     ;
; CLK6_COUNTER                  ; E0                        ; Untyped                                     ;
; CLK7_COUNTER                  ; E1                        ; Untyped                                     ;
; CLK8_COUNTER                  ; E2                        ; Untyped                                     ;
; CLK9_COUNTER                  ; E3                        ; Untyped                                     ;
; L0_TIME_DELAY                 ; 0                         ; Untyped                                     ;
; L1_TIME_DELAY                 ; 0                         ; Untyped                                     ;
; G0_TIME_DELAY                 ; 0                         ; Untyped                                     ;
; G1_TIME_DELAY                 ; 0                         ; Untyped                                     ;
; G2_TIME_DELAY                 ; 0                         ; Untyped                                     ;
; G3_TIME_DELAY                 ; 0                         ; Untyped                                     ;
; E0_TIME_DELAY                 ; 0                         ; Untyped                                     ;
; E1_TIME_DELAY                 ; 0                         ; Untyped                                     ;
; E2_TIME_DELAY                 ; 0                         ; Untyped                                     ;
; E3_TIME_DELAY                 ; 0                         ; Untyped                                     ;
; M_TIME_DELAY                  ; 0                         ; Untyped                                     ;
; N_TIME_DELAY                  ; 0                         ; Untyped                                     ;
; EXTCLK3_COUNTER               ; E3                        ; Untyped                                     ;
; EXTCLK2_COUNTER               ; E2                        ; Untyped                                     ;
; EXTCLK1_COUNTER               ; E1                        ; Untyped                                     ;
; EXTCLK0_COUNTER               ; E0                        ; Untyped                                     ;
; ENABLE0_COUNTER               ; L0                        ; Untyped                                     ;
; ENABLE1_COUNTER               ; L0                        ; Untyped                                     ;
; CHARGE_PUMP_CURRENT           ; 2                         ; Untyped                                     ;
; LOOP_FILTER_R                 ;  1.000000                 ; Untyped                                     ;
; LOOP_FILTER_C                 ; 5                         ; Untyped                                     ;
; CHARGE_PUMP_CURRENT_BITS      ; 9999                      ; Untyped                                     ;
; LOOP_FILTER_R_BITS            ; 9999                      ; Untyped                                     ;
; LOOP_FILTER_C_BITS            ; 9999                      ; Untyped                                     ;
; VCO_POST_SCALE                ; 0                         ; Untyped                                     ;
; CLK2_OUTPUT_FREQUENCY         ; 0                         ; Untyped                                     ;
; CLK1_OUTPUT_FREQUENCY         ; 0                         ; Untyped                                     ;
; CLK0_OUTPUT_FREQUENCY         ; 0                         ; Untyped                                     ;
; INTENDED_DEVICE_FAMILY        ; Cyclone II                ; Untyped                                     ;
; PORT_CLKENA0                  ; PORT_UNUSED               ; Untyped                                     ;
; PORT_CLKENA1                  ; PORT_UNUSED               ; Untyped                                     ;
; PORT_CLKENA2                  ; PORT_UNUSED               ; Untyped                                     ;
; PORT_CLKENA3                  ; PORT_UNUSED               ; Untyped                                     ;
; PORT_CLKENA4                  ; PORT_UNUSED               ; Untyped                                     ;
; PORT_CLKENA5                  ; PORT_UNUSED               ; Untyped                                     ;
; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY         ; Untyped                                     ;
; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY         ; Untyped                                     ;
; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY         ; Untyped                                     ;
; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY         ; Untyped                                     ;
; PORT_EXTCLK0                  ; PORT_UNUSED               ; Untyped                                     ;
; PORT_EXTCLK1                  ; PORT_UNUSED               ; Untyped                                     ;
; PORT_EXTCLK2                  ; PORT_UNUSED               ; Untyped                                     ;
; PORT_EXTCLK3                  ; PORT_UNUSED               ; Untyped                                     ;
; PORT_CLKBAD0                  ; PORT_UNUSED               ; Untyped                                     ;
; PORT_CLKBAD1                  ; PORT_UNUSED               ; Untyped                                     ;
; PORT_CLK0                     ; PORT_USED                 ; Untyped                                     ;
; PORT_CLK1                     ; PORT_UNUSED               ; Untyped                                     ;
; PORT_CLK2                     ; PORT_UNUSED               ; Untyped                                     ;
; PORT_CLK3                     ; PORT_UNUSED               ; Untyped                                     ;
; PORT_CLK4                     ; PORT_UNUSED               ; Untyped                                     ;
; PORT_CLK5                     ; PORT_UNUSED               ; Untyped                                     ;
; PORT_CLK6                     ; PORT_UNUSED               ; Untyped                                     ;
; PORT_CLK7                     ; PORT_UNUSED               ; Untyped                                     ;
; PORT_CLK8                     ; PORT_UNUSED               ; Untyped                                     ;
; PORT_CLK9                     ; PORT_UNUSED               ; Untyped                                     ;
; PORT_SCANDATA                 ; PORT_UNUSED               ; Untyped                                     ;
; PORT_SCANDATAOUT              ; PORT_UNUSED               ; Untyped                                     ;
; PORT_SCANDONE                 ; PORT_UNUSED               ; Untyped                                     ;
; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY         ; Untyped                                     ;
; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY         ; Untyped                                     ;
; PORT_ACTIVECLOCK              ; PORT_UNUSED               ; Untyped                                     ;
; PORT_CLKLOSS                  ; PORT_UNUSED               ; Untyped                                     ;
; PORT_INCLK1                   ; PORT_UNUSED               ; Untyped                                     ;
; PORT_INCLK0                   ; PORT_USED                 ; Untyped                                     ;
; PORT_FBIN                     ; PORT_UNUSED               ; Untyped                                     ;
; PORT_PLLENA                   ; PORT_UNUSED               ; Untyped                                     ;
; PORT_CLKSWITCH                ; PORT_UNUSED               ; Untyped                                     ;
; PORT_ARESET                   ; PORT_UNUSED               ; Untyped                                     ;
; PORT_PFDENA                   ; PORT_UNUSED               ; Untyped                                     ;
; PORT_SCANCLK                  ; PORT_UNUSED               ; Untyped                                     ;
; PORT_SCANACLR                 ; PORT_UNUSED               ; Untyped                                     ;
; PORT_SCANREAD                 ; PORT_UNUSED               ; Untyped                                     ;
; PORT_SCANWRITE                ; PORT_UNUSED               ; Untyped                                     ;
; PORT_ENABLE0                  ; PORT_CONNECTIVITY         ; Untyped                                     ;
; PORT_ENABLE1                  ; PORT_CONNECTIVITY         ; Untyped                                     ;
; PORT_LOCKED                   ; PORT_UNUSED               ; Untyped                                     ;
; PORT_CONFIGUPDATE             ; PORT_UNUSED               ; Untyped                                     ;
; PORT_FBOUT                    ; PORT_CONNECTIVITY         ; Untyped                                     ;
; PORT_PHASEDONE                ; PORT_UNUSED               ; Untyped                                     ;
; PORT_PHASESTEP                ; PORT_UNUSED               ; Untyped                                     ;
; PORT_PHASEUPDOWN              ; PORT_UNUSED               ; Untyped                                     ;
; PORT_SCANCLKENA               ; PORT_UNUSED               ; Untyped                                     ;
; PORT_PHASECOUNTERSELECT       ; PORT_UNUSED               ; Untyped                                     ;
; PORT_VCOOVERRANGE             ; PORT_CONNECTIVITY         ; Untyped                                     ;
; PORT_VCOUNDERRANGE            ; PORT_CONNECTIVITY         ; Untyped                                     ;
; M_TEST_SOURCE                 ; 5                         ; Untyped                                     ;
; C0_TEST_SOURCE                ; 5                         ; Untyped                                     ;
; C1_TEST_SOURCE                ; 5                         ; Untyped                                     ;
; C2_TEST_SOURCE                ; 5                         ; Untyped                                     ;
; C3_TEST_SOURCE                ; 5                         ; Untyped                                     ;
; C4_TEST_SOURCE                ; 5                         ; Untyped                                     ;
; C5_TEST_SOURCE                ; 5                         ; Untyped                                     ;
; C6_TEST_SOURCE                ; 5                         ; Untyped                                     ;
; C7_TEST_SOURCE                ; 5                         ; Untyped                                     ;
; C8_TEST_SOURCE                ; 5                         ; Untyped                                     ;
; C9_TEST_SOURCE                ; 5                         ; Untyped                                     ;
; CBXI_PARAMETER                ; NOTHING                   ; Untyped                                     ;
; VCO_FREQUENCY_CONTROL         ; AUTO                      ; Untyped                                     ;
; VCO_PHASE_SHIFT_STEP          ; 0                         ; Untyped                                     ;
; WIDTH_CLOCK                   ; 6                         ; Untyped                                     ;
; WIDTH_PHASECOUNTERSELECT      ; 4                         ; Untyped                                     ;
; USING_FBMIMICBIDIR_PORT       ; OFF                       ; Untyped                                     ;
; DEVICE_FAMILY                 ; Cyclone II                ; Untyped                                     ;
; SCAN_CHAIN_MIF_FILE           ; UNUSED                    ; Untyped                                     ;
; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF                       ; Untyped                                     ;
; AUTO_CARRY_CHAINS             ; ON                        ; AUTO_CARRY                                  ;
; IGNORE_CARRY_BUFFERS          ; OFF                       ; IGNORE_CARRY                                ;
; AUTO_CASCADE_CHAINS           ; ON                        ; AUTO_CASCADE                                ;
; IGNORE_CASCADE_BUFFERS        ; OFF                       ; IGNORE_CASCADE                              ;
+-------------------------------+---------------------------+---------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: clock_generator:inst3|altpll2:inst2|altpll:altpll_component ;
+-------------------------------+---------------------------+----------------------------------------------+
; Parameter Name                ; Value                     ; Type                                         ;
+-------------------------------+---------------------------+----------------------------------------------+
; OPERATION_MODE                ; SOURCE_SYNCHRONOUS        ; Untyped                                      ;
; PLL_TYPE                      ; AUTO                      ; Untyped                                      ;
; LPM_HINT                      ; CBX_MODULE_PREFIX=altpll2 ; Untyped                                      ;
; QUALIFY_CONF_DONE             ; OFF                       ; Untyped                                      ;
; COMPENSATE_CLOCK              ; CLK0                      ; Untyped                                      ;
; SCAN_CHAIN                    ; LONG                      ; Untyped                                      ;
; PRIMARY_CLOCK                 ; INCLK0                    ; Untyped                                      ;
; INCLK0_INPUT_FREQUENCY        ; 20000                     ; Signed Integer                               ;
; INCLK1_INPUT_FREQUENCY        ; 0                         ; Untyped                                      ;
; GATE_LOCK_SIGNAL              ; NO                        ; Untyped                                      ;
; GATE_LOCK_COUNTER             ; 0                         ; Untyped                                      ;
; LOCK_HIGH                     ; 1                         ; Untyped                                      ;
; LOCK_LOW                      ; 1                         ; Untyped                                      ;
; VALID_LOCK_MULTIPLIER         ; 1                         ; Untyped                                      ;
; INVALID_LOCK_MULTIPLIER       ; 5                         ; Untyped                                      ;
; SWITCH_OVER_ON_LOSSCLK        ; OFF                       ; Untyped                                      ;
; SWITCH_OVER_ON_GATED_LOCK     ; OFF                       ; Untyped                                      ;
; ENABLE_SWITCH_OVER_COUNTER    ; OFF                       ; Untyped                                      ;
; SKIP_VCO                      ; OFF                       ; Untyped                                      ;
; SWITCH_OVER_COUNTER           ; 0                         ; Untyped                                      ;
; SWITCH_OVER_TYPE              ; AUTO                      ; Untyped                                      ;
; FEEDBACK_SOURCE               ; EXTCLK0                   ; Untyped                                      ;
; BANDWIDTH                     ; 0                         ; Untyped                                      ;
; BANDWIDTH_TYPE                ; AUTO                      ; Untyped                                      ;
; SPREAD_FREQUENCY              ; 0                         ; Untyped                                      ;
; DOWN_SPREAD                   ; 0                         ; Untyped                                      ;
; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF                       ; Untyped                                      ;
; SELF_RESET_ON_LOSS_LOCK       ; OFF                       ; Untyped                                      ;
; CLK9_MULTIPLY_BY              ; 0                         ; Untyped                                      ;
; CLK8_MULTIPLY_BY              ; 0                         ; Untyped                                      ;
; CLK7_MULTIPLY_BY              ; 0                         ; Untyped                                      ;
; CLK6_MULTIPLY_BY              ; 0                         ; Untyped                                      ;
; CLK5_MULTIPLY_BY              ; 1                         ; Untyped                                      ;
; CLK4_MULTIPLY_BY              ; 1                         ; Untyped                                      ;
; CLK3_MULTIPLY_BY              ; 1                         ; Untyped                                      ;
; CLK2_MULTIPLY_BY              ; 1                         ; Untyped                                      ;
; CLK1_MULTIPLY_BY              ; 1                         ; Untyped                                      ;
; CLK0_MULTIPLY_BY              ; 1                         ; Untyped                                      ;
; CLK9_DIVIDE_BY                ; 0                         ; Untyped                                      ;
; CLK8_DIVIDE_BY                ; 0                         ; Untyped                                      ;
; CLK7_DIVIDE_BY                ; 0                         ; Untyped                                      ;
; CLK6_DIVIDE_BY                ; 0                         ; Untyped                                      ;
; CLK5_DIVIDE_BY                ; 1                         ; Untyped                                      ;
; CLK4_DIVIDE_BY                ; 1                         ; Untyped                                      ;
; CLK3_DIVIDE_BY                ; 1                         ; Untyped                                      ;
; CLK2_DIVIDE_BY                ; 1                         ; Untyped                                      ;
; CLK1_DIVIDE_BY                ; 1                         ; Untyped                                      ;
; CLK0_DIVIDE_BY                ; 1                         ; Untyped                                      ;
; CLK9_PHASE_SHIFT              ; 0                         ; Untyped                                      ;
; CLK8_PHASE_SHIFT              ; 0                         ; Untyped                                      ;
; CLK7_PHASE_SHIFT              ; 0                         ; Untyped                                      ;
; CLK6_PHASE_SHIFT              ; 0                         ; Untyped                                      ;
; CLK5_PHASE_SHIFT              ; 0                         ; Untyped                                      ;
; CLK4_PHASE_SHIFT              ; 0                         ; Untyped                                      ;
; CLK3_PHASE_SHIFT              ; 0                         ; Untyped                                      ;
; CLK2_PHASE_SHIFT              ; 0                         ; Untyped                                      ;
; CLK1_PHASE_SHIFT              ; 0                         ; Untyped                                      ;
; CLK0_PHASE_SHIFT              ; 0                         ; Untyped                                      ;
; CLK5_TIME_DELAY               ; 0                         ; Untyped                                      ;
; CLK4_TIME_DELAY               ; 0                         ; Untyped                                      ;
; CLK3_TIME_DELAY               ; 0                         ; Untyped                                      ;
; CLK2_TIME_DELAY               ; 0                         ; Untyped                                      ;
; CLK1_TIME_DELAY               ; 0                         ; Untyped                                      ;
; CLK0_TIME_DELAY               ; 0                         ; Untyped                                      ;
; CLK9_DUTY_CYCLE               ; 50                        ; Untyped                                      ;
; CLK8_DUTY_CYCLE               ; 50                        ; Untyped                                      ;
; CLK7_DUTY_CYCLE               ; 50                        ; Untyped                                      ;
; CLK6_DUTY_CYCLE               ; 50                        ; Untyped                                      ;
; CLK5_DUTY_CYCLE               ; 50                        ; Untyped                                      ;
; CLK4_DUTY_CYCLE               ; 50                        ; Untyped                                      ;
; CLK3_DUTY_CYCLE               ; 50                        ; Untyped                                      ;
; CLK2_DUTY_CYCLE               ; 50                        ; Untyped                                      ;
; CLK1_DUTY_CYCLE               ; 50                        ; Untyped                                      ;
; CLK0_DUTY_CYCLE               ; 50                        ; Untyped                                      ;
; CLK9_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                                      ;
; CLK8_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                                      ;
; CLK7_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                                      ;
; CLK6_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                                      ;
; CLK5_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                                      ;
; CLK4_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                                      ;
; CLK3_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                                      ;
; CLK2_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                                      ;
; CLK1_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                                      ;
; CLK0_USE_EVEN_COUNTER_MODE    ; OFF                       ; Untyped                                      ;
; CLK9_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                                      ;
; CLK8_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                                      ;
; CLK7_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                                      ;
; CLK6_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                                      ;
; CLK5_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                                      ;
; CLK4_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                                      ;
; CLK3_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                                      ;
; CLK2_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                                      ;
; CLK1_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                                      ;
; CLK0_USE_EVEN_COUNTER_VALUE   ; OFF                       ; Untyped                                      ;
; LOCK_WINDOW_UI                ;  0.05                     ; Untyped                                      ;
; LOCK_WINDOW_UI_BITS           ; UNUSED                    ; Untyped                                      ;
; VCO_RANGE_DETECTOR_LOW_BITS   ; UNUSED                    ; Untyped                                      ;
; VCO_RANGE_DETECTOR_HIGH_BITS  ; UNUSED                    ; Untyped                                      ;
; DPA_MULTIPLY_BY               ; 0                         ; Untyped                                      ;
; DPA_DIVIDE_BY                 ; 1                         ; Untyped                                      ;
; DPA_DIVIDER                   ; 0                         ; Untyped                                      ;
; EXTCLK3_MULTIPLY_BY           ; 1                         ; Untyped                                      ;
; EXTCLK2_MULTIPLY_BY           ; 1                         ; Untyped                                      ;
; EXTCLK1_MULTIPLY_BY           ; 1                         ; Untyped                                      ;
; EXTCLK0_MULTIPLY_BY           ; 1                         ; Untyped                                      ;
; EXTCLK3_DIVIDE_BY             ; 1                         ; Untyped                                      ;
; EXTCLK2_DIVIDE_BY             ; 1                         ; Untyped                                      ;
; EXTCLK1_DIVIDE_BY             ; 1                         ; Untyped                                      ;
; EXTCLK0_DIVIDE_BY             ; 1                         ; Untyped                                      ;
; EXTCLK3_PHASE_SHIFT           ; 0                         ; Untyped                                      ;
; EXTCLK2_PHASE_SHIFT           ; 0                         ; Untyped                                      ;
; EXTCLK1_PHASE_SHIFT           ; 0                         ; Untyped                                      ;
; EXTCLK0_PHASE_SHIFT           ; 0                         ; Untyped                                      ;
; EXTCLK3_TIME_DELAY            ; 0                         ; Untyped                                      ;
; EXTCLK2_TIME_DELAY            ; 0                         ; Untyped                                      ;
; EXTCLK1_TIME_DELAY            ; 0                         ; Untyped                                      ;
; EXTCLK0_TIME_DELAY            ; 0                         ; Untyped                                      ;
; EXTCLK3_DUTY_CYCLE            ; 50                        ; Untyped                                      ;
; EXTCLK2_DUTY_CYCLE            ; 50                        ; Untyped                                      ;
; EXTCLK1_DUTY_CYCLE            ; 50                        ; Untyped                                      ;
; EXTCLK0_DUTY_CYCLE            ; 50                        ; Untyped                                      ;
; VCO_MULTIPLY_BY               ; 0                         ; Untyped                                      ;
; VCO_DIVIDE_BY                 ; 0                         ; Untyped                                      ;
; SCLKOUT0_PHASE_SHIFT          ; 0                         ; Untyped                                      ;
; SCLKOUT1_PHASE_SHIFT          ; 0                         ; Untyped                                      ;
; VCO_MIN                       ; 0                         ; Untyped                                      ;
; VCO_MAX                       ; 0                         ; Untyped                                      ;
; VCO_CENTER                    ; 0                         ; Untyped                                      ;
; PFD_MIN                       ; 0                         ; Untyped                                      ;
; PFD_MAX                       ; 0                         ; Untyped                                      ;
; M_INITIAL                     ; 1                         ; Signed Integer                               ;
; M                             ; 16                        ; Signed Integer                               ;
; N                             ; 1                         ; Signed Integer                               ;
; M2                            ; 1                         ; Untyped                                      ;
; N2                            ; 1                         ; Untyped                                      ;
; SS                            ; 1                         ; Untyped                                      ;
; C0_HIGH                       ; 8                         ; Signed Integer                               ;
; C1_HIGH                       ; 0                         ; Untyped                                      ;
; C2_HIGH                       ; 0                         ; Untyped                                      ;
; C3_HIGH                       ; 0                         ; Untyped                                      ;
; C4_HIGH                       ; 0                         ; Untyped                                      ;
; C5_HIGH                       ; 0                         ; Untyped                                      ;
; C6_HIGH                       ; 0                         ; Untyped                                      ;
; C7_HIGH                       ; 0                         ; Untyped                                      ;
; C8_HIGH                       ; 0                         ; Untyped                                      ;
; C9_HIGH                       ; 0                         ; Untyped                                      ;
; C0_LOW                        ; 8                         ; Signed Integer                               ;
; C1_LOW                        ; 0                         ; Untyped                                      ;
; C2_LOW                        ; 0                         ; Untyped                                      ;
; C3_LOW                        ; 0                         ; Untyped                                      ;
; C4_LOW                        ; 0                         ; Untyped                                      ;
; C5_LOW                        ; 0                         ; Untyped                                      ;
; C6_LOW                        ; 0                         ; Untyped                                      ;
; C7_LOW                        ; 0                         ; Untyped                                      ;
; C8_LOW                        ; 0                         ; Untyped                                      ;
; C9_LOW                        ; 0                         ; Untyped                                      ;
; C0_INITIAL                    ; 1                         ; Signed Integer                               ;
; C1_INITIAL                    ; 0                         ; Untyped                                      ;
; C2_INITIAL                    ; 0                         ; Untyped                                      ;
; C3_INITIAL                    ; 0                         ; Untyped                                      ;
; C4_INITIAL                    ; 0                         ; Untyped                                      ;
; C5_INITIAL                    ; 0                         ; Untyped                                      ;
; C6_INITIAL                    ; 0                         ; Untyped                                      ;
; C7_INITIAL                    ; 0                         ; Untyped                                      ;
; C8_INITIAL                    ; 0                         ; Untyped                                      ;
; C9_INITIAL                    ; 0                         ; Untyped                                      ;
; C0_MODE                       ; even                      ; Untyped                                      ;
; C1_MODE                       ; BYPASS                    ; Untyped                                      ;
; C2_MODE                       ; BYPASS                    ; Untyped                                      ;
; C3_MODE                       ; BYPASS                    ; Untyped                                      ;
; C4_MODE                       ; BYPASS                    ; Untyped                                      ;
; C5_MODE                       ; BYPASS                    ; Untyped                                      ;
; C6_MODE                       ; BYPASS                    ; Untyped                                      ;
; C7_MODE                       ; BYPASS                    ; Untyped                                      ;
; C8_MODE                       ; BYPASS                    ; Untyped                                      ;
; C9_MODE                       ; BYPASS                    ; Untyped                                      ;
; C0_PH                         ; 0                         ; Signed Integer                               ;
; C1_PH                         ; 0                         ; Untyped                                      ;
; C2_PH                         ; 0                         ; Untyped                                      ;
; C3_PH                         ; 0                         ; Untyped                                      ;
; C4_PH                         ; 0                         ; Untyped                                      ;
; C5_PH                         ; 0                         ; Untyped                                      ;
; C6_PH                         ; 0                         ; Untyped                                      ;
; C7_PH                         ; 0                         ; Untyped                                      ;
; C8_PH                         ; 0                         ; Untyped                                      ;
; C9_PH                         ; 0                         ; Untyped                                      ;
; L0_HIGH                       ; 1                         ; Untyped                                      ;
; L1_HIGH                       ; 1                         ; Untyped                                      ;
; G0_HIGH                       ; 1                         ; Untyped                                      ;
; G1_HIGH                       ; 1                         ; Untyped                                      ;
; G2_HIGH                       ; 1                         ; Untyped                                      ;
; G3_HIGH                       ; 1                         ; Untyped                                      ;
; E0_HIGH                       ; 1                         ; Untyped                                      ;
; E1_HIGH                       ; 1                         ; Untyped                                      ;
; E2_HIGH                       ; 1                         ; Untyped                                      ;
; E3_HIGH                       ; 1                         ; Untyped                                      ;
; L0_LOW                        ; 1                         ; Untyped                                      ;
; L1_LOW                        ; 1                         ; Untyped                                      ;
; G0_LOW                        ; 1                         ; Untyped                                      ;
; G1_LOW                        ; 1                         ; Untyped                                      ;
; G2_LOW                        ; 1                         ; Untyped                                      ;
; G3_LOW                        ; 1                         ; Untyped                                      ;
; E0_LOW                        ; 1                         ; Untyped                                      ;
; E1_LOW                        ; 1                         ; Untyped                                      ;
; E2_LOW                        ; 1                         ; Untyped                                      ;
; E3_LOW                        ; 1                         ; Untyped                                      ;
; L0_INITIAL                    ; 1                         ; Untyped                                      ;
; L1_INITIAL                    ; 1                         ; Untyped                                      ;
; G0_INITIAL                    ; 1                         ; Untyped                                      ;
; G1_INITIAL                    ; 1                         ; Untyped                                      ;
; G2_INITIAL                    ; 1                         ; Untyped                                      ;
; G3_INITIAL                    ; 1                         ; Untyped                                      ;
; E0_INITIAL                    ; 1                         ; Untyped                                      ;
; E1_INITIAL                    ; 1                         ; Untyped                                      ;
; E2_INITIAL                    ; 1                         ; Untyped                                      ;
; E3_INITIAL                    ; 1                         ; Untyped                                      ;
; L0_MODE                       ; BYPASS                    ; Untyped                                      ;
; L1_MODE                       ; BYPASS                    ; Untyped                                      ;
; G0_MODE                       ; BYPASS                    ; Untyped                                      ;
; G1_MODE                       ; BYPASS                    ; Untyped                                      ;
; G2_MODE                       ; BYPASS                    ; Untyped                                      ;
; G3_MODE                       ; BYPASS                    ; Untyped                                      ;
; E0_MODE                       ; BYPASS                    ; Untyped                                      ;
; E1_MODE                       ; BYPASS                    ; Untyped                                      ;
; E2_MODE                       ; BYPASS                    ; Untyped                                      ;
; E3_MODE                       ; BYPASS                    ; Untyped                                      ;
; L0_PH                         ; 0                         ; Untyped                                      ;
; L1_PH                         ; 0                         ; Untyped                                      ;
; G0_PH                         ; 0                         ; Untyped                                      ;
; G1_PH                         ; 0                         ; Untyped                                      ;
; G2_PH                         ; 0                         ; Untyped                                      ;
; G3_PH                         ; 0                         ; Untyped                                      ;
; E0_PH                         ; 0                         ; Untyped                                      ;
; E1_PH                         ; 0                         ; Untyped                                      ;
; E2_PH                         ; 0                         ; Untyped                                      ;
; E3_PH                         ; 0                         ; Untyped                                      ;
; M_PH                          ; 0                         ; Signed Integer                               ;
; C1_USE_CASC_IN                ; OFF                       ; Untyped                                      ;
; C2_USE_CASC_IN                ; OFF                       ; Untyped                                      ;
; C3_USE_CASC_IN                ; OFF                       ; Untyped                                      ;
; C4_USE_CASC_IN                ; OFF                       ; Untyped                                      ;
; C5_USE_CASC_IN                ; OFF                       ; Untyped                                      ;
; C6_USE_CASC_IN                ; OFF                       ; Untyped                                      ;
; C7_USE_CASC_IN                ; OFF                       ; Untyped                                      ;
; C8_USE_CASC_IN                ; OFF                       ; Untyped                                      ;
; C9_USE_CASC_IN                ; OFF                       ; Untyped                                      ;
; CLK0_COUNTER                  ; c0                        ; Untyped                                      ;
; CLK1_COUNTER                  ; G0                        ; Untyped                                      ;
; CLK2_COUNTER                  ; G0                        ; Untyped                                      ;
; CLK3_COUNTER                  ; G0                        ; Untyped                                      ;
; CLK4_COUNTER                  ; G0                        ; Untyped                                      ;
; CLK5_COUNTER                  ; G0                        ; Untyped                                      ;
; CLK6_COUNTER                  ; E0                        ; Untyped                                      ;
; CLK7_COUNTER                  ; E1                        ; Untyped                                      ;
; CLK8_COUNTER                  ; E2                        ; Untyped                                      ;
; CLK9_COUNTER                  ; E3                        ; Untyped                                      ;
; L0_TIME_DELAY                 ; 0                         ; Untyped                                      ;
; L1_TIME_DELAY                 ; 0                         ; Untyped                                      ;
; G0_TIME_DELAY                 ; 0                         ; Untyped                                      ;
; G1_TIME_DELAY                 ; 0                         ; Untyped                                      ;
; G2_TIME_DELAY                 ; 0                         ; Untyped                                      ;
; G3_TIME_DELAY                 ; 0                         ; Untyped                                      ;
; E0_TIME_DELAY                 ; 0                         ; Untyped                                      ;
; E1_TIME_DELAY                 ; 0                         ; Untyped                                      ;
; E2_TIME_DELAY                 ; 0                         ; Untyped                                      ;
; E3_TIME_DELAY                 ; 0                         ; Untyped                                      ;
; M_TIME_DELAY                  ; 0                         ; Untyped                                      ;
; N_TIME_DELAY                  ; 0                         ; Untyped                                      ;
; EXTCLK3_COUNTER               ; E3                        ; Untyped                                      ;
; EXTCLK2_COUNTER               ; E2                        ; Untyped                                      ;
; EXTCLK1_COUNTER               ; E1                        ; Untyped                                      ;
; EXTCLK0_COUNTER               ; E0                        ; Untyped                                      ;
; ENABLE0_COUNTER               ; L0                        ; Untyped                                      ;
; ENABLE1_COUNTER               ; L0                        ; Untyped                                      ;
; CHARGE_PUMP_CURRENT           ; 2                         ; Untyped                                      ;
; LOOP_FILTER_R                 ;  1.000000                 ; Untyped                                      ;
; LOOP_FILTER_C                 ; 5                         ; Untyped                                      ;
; CHARGE_PUMP_CURRENT_BITS      ; 9999                      ; Untyped                                      ;
; LOOP_FILTER_R_BITS            ; 9999                      ; Untyped                                      ;
; LOOP_FILTER_C_BITS            ; 9999                      ; Untyped                                      ;
; VCO_POST_SCALE                ; 1                         ; Signed Integer                               ;
; CLK2_OUTPUT_FREQUENCY         ; 0                         ; Untyped                                      ;
; CLK1_OUTPUT_FREQUENCY         ; 0                         ; Untyped                                      ;
; CLK0_OUTPUT_FREQUENCY         ; 0                         ; Untyped                                      ;
; INTENDED_DEVICE_FAMILY        ; Cyclone II                ; Untyped                                      ;
; PORT_CLKENA0                  ; PORT_UNUSED               ; Untyped                                      ;
; PORT_CLKENA1                  ; PORT_UNUSED               ; Untyped                                      ;
; PORT_CLKENA2                  ; PORT_UNUSED               ; Untyped                                      ;
; PORT_CLKENA3                  ; PORT_UNUSED               ; Untyped                                      ;
; PORT_CLKENA4                  ; PORT_UNUSED               ; Untyped                                      ;
; PORT_CLKENA5                  ; PORT_UNUSED               ; Untyped                                      ;
; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY         ; Untyped                                      ;
; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY         ; Untyped                                      ;
; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY         ; Untyped                                      ;
; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY         ; Untyped                                      ;
; PORT_EXTCLK0                  ; PORT_UNUSED               ; Untyped                                      ;
; PORT_EXTCLK1                  ; PORT_UNUSED               ; Untyped                                      ;
; PORT_EXTCLK2                  ; PORT_UNUSED               ; Untyped                                      ;
; PORT_EXTCLK3                  ; PORT_UNUSED               ; Untyped                                      ;
; PORT_CLKBAD0                  ; PORT_UNUSED               ; Untyped                                      ;
; PORT_CLKBAD1                  ; PORT_UNUSED               ; Untyped                                      ;
; PORT_CLK0                     ; PORT_USED                 ; Untyped                                      ;
; PORT_CLK1                     ; PORT_UNUSED               ; Untyped                                      ;
; PORT_CLK2                     ; PORT_UNUSED               ; Untyped                                      ;
; PORT_CLK3                     ; PORT_UNUSED               ; Untyped                                      ;
; PORT_CLK4                     ; PORT_UNUSED               ; Untyped                                      ;
; PORT_CLK5                     ; PORT_UNUSED               ; Untyped                                      ;
; PORT_CLK6                     ; PORT_UNUSED               ; Untyped                                      ;
; PORT_CLK7                     ; PORT_UNUSED               ; Untyped                                      ;
; PORT_CLK8                     ; PORT_UNUSED               ; Untyped                                      ;
; PORT_CLK9                     ; PORT_UNUSED               ; Untyped                                      ;
; PORT_SCANDATA                 ; PORT_UNUSED               ; Untyped                                      ;
; PORT_SCANDATAOUT              ; PORT_UNUSED               ; Untyped                                      ;
; PORT_SCANDONE                 ; PORT_UNUSED               ; Untyped                                      ;
; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY         ; Untyped                                      ;
; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY         ; Untyped                                      ;
; PORT_ACTIVECLOCK              ; PORT_UNUSED               ; Untyped                                      ;
; PORT_CLKLOSS                  ; PORT_UNUSED               ; Untyped                                      ;
; PORT_INCLK1                   ; PORT_UNUSED               ; Untyped                                      ;
; PORT_INCLK0                   ; PORT_USED                 ; Untyped                                      ;
; PORT_FBIN                     ; PORT_UNUSED               ; Untyped                                      ;
; PORT_PLLENA                   ; PORT_UNUSED               ; Untyped                                      ;
; PORT_CLKSWITCH                ; PORT_UNUSED               ; Untyped                                      ;
; PORT_ARESET                   ; PORT_UNUSED               ; Untyped                                      ;
; PORT_PFDENA                   ; PORT_UNUSED               ; Untyped                                      ;
; PORT_SCANCLK                  ; PORT_UNUSED               ; Untyped                                      ;
; PORT_SCANACLR                 ; PORT_UNUSED               ; Untyped                                      ;
; PORT_SCANREAD                 ; PORT_UNUSED               ; Untyped                                      ;
; PORT_SCANWRITE                ; PORT_UNUSED               ; Untyped                                      ;
; PORT_ENABLE0                  ; PORT_CONNECTIVITY         ; Untyped                                      ;
; PORT_ENABLE1                  ; PORT_CONNECTIVITY         ; Untyped                                      ;
; PORT_LOCKED                   ; PORT_UNUSED               ; Untyped                                      ;
; PORT_CONFIGUPDATE             ; PORT_UNUSED               ; Untyped                                      ;
; PORT_FBOUT                    ; PORT_CONNECTIVITY         ; Untyped                                      ;
; PORT_PHASEDONE                ; PORT_UNUSED               ; Untyped                                      ;
; PORT_PHASESTEP                ; PORT_UNUSED               ; Untyped                                      ;
; PORT_PHASEUPDOWN              ; PORT_UNUSED               ; Untyped                                      ;
; PORT_SCANCLKENA               ; PORT_UNUSED               ; Untyped                                      ;
; PORT_PHASECOUNTERSELECT       ; PORT_UNUSED               ; Untyped                                      ;
; PORT_VCOOVERRANGE             ; PORT_CONNECTIVITY         ; Untyped                                      ;
; PORT_VCOUNDERRANGE            ; PORT_CONNECTIVITY         ; Untyped                                      ;
; M_TEST_SOURCE                 ; 5                         ; Untyped                                      ;
; C0_TEST_SOURCE                ; 5                         ; Untyped                                      ;
; C1_TEST_SOURCE                ; 5                         ; Untyped                                      ;
; C2_TEST_SOURCE                ; 5                         ; Untyped                                      ;
; C3_TEST_SOURCE                ; 5                         ; Untyped                                      ;
; C4_TEST_SOURCE                ; 5                         ; Untyped                                      ;
; C5_TEST_SOURCE                ; 5                         ; Untyped                                      ;
; C6_TEST_SOURCE                ; 5                         ; Untyped                                      ;
; C7_TEST_SOURCE                ; 5                         ; Untyped                                      ;
; C8_TEST_SOURCE                ; 5                         ; Untyped                                      ;
; C9_TEST_SOURCE                ; 5                         ; Untyped                                      ;
; CBXI_PARAMETER                ; NOTHING                   ; Untyped                                      ;
; VCO_FREQUENCY_CONTROL         ; AUTO                      ; Untyped                                      ;
; VCO_PHASE_SHIFT_STEP          ; 0                         ; Untyped                                      ;
; WIDTH_CLOCK                   ; 6                         ; Untyped                                      ;
; WIDTH_PHASECOUNTERSELECT      ; 4                         ; Untyped                                      ;
; USING_FBMIMICBIDIR_PORT       ; OFF                       ; Untyped                                      ;
; DEVICE_FAMILY                 ; Cyclone II                ; Untyped                                      ;
; SCAN_CHAIN_MIF_FILE           ; UNUSED                    ; Untyped                                      ;
; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF                       ; Untyped                                      ;
; AUTO_CARRY_CHAINS             ; ON                        ; AUTO_CARRY                                   ;
; IGNORE_CARRY_BUFFERS          ; OFF                       ; IGNORE_CARRY                                 ;
; AUTO_CASCADE_CHAINS           ; ON                        ; AUTO_CASCADE                                 ;
; IGNORE_CASCADE_BUFFERS        ; OFF                       ; IGNORE_CASCADE                               ;
+-------------------------------+---------------------------+----------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: mmi:inst2|lcd_controller:inst2|altsyncram:Mux13_rtl_0 ;
+------------------------------------+------------------------------+------------------------------------+
; Parameter Name                     ; Value                        ; Type                               ;
+------------------------------------+------------------------------+------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                            ; Untyped                            ;
; AUTO_CARRY_CHAINS                  ; ON                           ; AUTO_CARRY                         ;
; IGNORE_CARRY_BUFFERS               ; OFF                          ; IGNORE_CARRY                       ;
; AUTO_CASCADE_CHAINS                ; ON                           ; AUTO_CASCADE                       ;
; IGNORE_CASCADE_BUFFERS             ; OFF                          ; IGNORE_CASCADE                     ;
; WIDTH_BYTEENA                      ; 1                            ; Untyped                            ;
; OPERATION_MODE                     ; ROM                          ; Untyped                            ;
; WIDTH_A                            ; 1                            ; Untyped                            ;
; WIDTHAD_A                          ; 5                            ; Untyped                            ;
; NUMWORDS_A                         ; 32                           ; Untyped                            ;
; OUTDATA_REG_A                      ; UNREGISTERED                 ; Untyped                            ;
; ADDRESS_ACLR_A                     ; NONE                         ; Untyped                            ;
; OUTDATA_ACLR_A                     ; NONE                         ; Untyped                            ;
; WRCONTROL_ACLR_A                   ; NONE                         ; Untyped                            ;
; INDATA_ACLR_A                      ; NONE                         ; Untyped                            ;
; BYTEENA_ACLR_A                     ; NONE                         ; Untyped                            ;
; WIDTH_B                            ; 1                            ; Untyped                            ;
; WIDTHAD_B                          ; 1                            ; Untyped                            ;
; NUMWORDS_B                         ; 1                            ; Untyped                            ;
; INDATA_REG_B                       ; CLOCK1                       ; Untyped                            ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1                       ; Untyped                            ;
; RDCONTROL_REG_B                    ; CLOCK1                       ; Untyped                            ;
; ADDRESS_REG_B                      ; CLOCK1                       ; Untyped                            ;
; OUTDATA_REG_B                      ; UNREGISTERED                 ; Untyped                            ;
; BYTEENA_REG_B                      ; CLOCK1                       ; Untyped                            ;
; INDATA_ACLR_B                      ; NONE                         ; Untyped                            ;
; WRCONTROL_ACLR_B                   ; NONE                         ; Untyped                            ;
; ADDRESS_ACLR_B                     ; NONE                         ; Untyped                            ;
; OUTDATA_ACLR_B                     ; NONE                         ; Untyped                            ;
; RDCONTROL_ACLR_B                   ; NONE                         ; Untyped                            ;
; BYTEENA_ACLR_B                     ; NONE                         ; Untyped                            ;
; WIDTH_BYTEENA_A                    ; 1                            ; Untyped                            ;
; WIDTH_BYTEENA_B                    ; 1                            ; Untyped                            ;
; RAM_BLOCK_TYPE                     ; AUTO                         ; Untyped                            ;
; BYTE_SIZE                          ; 8                            ; Untyped                            ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                    ; Untyped                            ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ         ; Untyped                            ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ         ; Untyped                            ;
; INIT_FILE                          ; Equalizer.Equalizer0.rtl.mif ; Untyped                            ;
; INIT_FILE_LAYOUT                   ; PORT_A                       ; Untyped                            ;
; MAXIMUM_DEPTH                      ; 0                            ; Untyped                            ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL                       ; Untyped                            ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL                       ; Untyped                            ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL                       ; Untyped                            ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL                       ; Untyped                            ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN              ; Untyped                            ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN              ; Untyped                            ;
; ENABLE_ECC                         ; FALSE                        ; Untyped                            ;
; WIDTH_ECCSTATUS                    ; 3                            ; Untyped                            ;
; DEVICE_FAMILY                      ; Cyclone II                   ; Untyped                            ;
; CBXI_PARAMETER                     ; altsyncram_dk01              ; Untyped                            ;
+------------------------------------+------------------------------+------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: mmi:inst2|lcd_controller:inst2|altsyncram:Mux12_rtl_0 ;
+------------------------------------+------------------------------+------------------------------------+
; Parameter Name                     ; Value                        ; Type                               ;
+------------------------------------+------------------------------+------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                            ; Untyped                            ;
; AUTO_CARRY_CHAINS                  ; ON                           ; AUTO_CARRY                         ;
; IGNORE_CARRY_BUFFERS               ; OFF                          ; IGNORE_CARRY                       ;
; AUTO_CASCADE_CHAINS                ; ON                           ; AUTO_CASCADE                       ;
; IGNORE_CASCADE_BUFFERS             ; OFF                          ; IGNORE_CASCADE                     ;
; WIDTH_BYTEENA                      ; 1                            ; Untyped                            ;
; OPERATION_MODE                     ; ROM                          ; Untyped                            ;
; WIDTH_A                            ; 1                            ; Untyped                            ;
; WIDTHAD_A                          ; 5                            ; Untyped                            ;
; NUMWORDS_A                         ; 32                           ; Untyped                            ;
; OUTDATA_REG_A                      ; UNREGISTERED                 ; Untyped                            ;
; ADDRESS_ACLR_A                     ; NONE                         ; Untyped                            ;
; OUTDATA_ACLR_A                     ; NONE                         ; Untyped                            ;
; WRCONTROL_ACLR_A                   ; NONE                         ; Untyped                            ;
; INDATA_ACLR_A                      ; NONE                         ; Untyped                            ;
; BYTEENA_ACLR_A                     ; NONE                         ; Untyped                            ;
; WIDTH_B                            ; 1                            ; Untyped                            ;
; WIDTHAD_B                          ; 1                            ; Untyped                            ;
; NUMWORDS_B                         ; 1                            ; Untyped                            ;
; INDATA_REG_B                       ; CLOCK1                       ; Untyped                            ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1                       ; Untyped                            ;
; RDCONTROL_REG_B                    ; CLOCK1                       ; Untyped                            ;
; ADDRESS_REG_B                      ; CLOCK1                       ; Untyped                            ;
; OUTDATA_REG_B                      ; UNREGISTERED                 ; Untyped                            ;
; BYTEENA_REG_B                      ; CLOCK1                       ; Untyped                            ;
; INDATA_ACLR_B                      ; NONE                         ; Untyped                            ;
; WRCONTROL_ACLR_B                   ; NONE                         ; Untyped                            ;
; ADDRESS_ACLR_B                     ; NONE                         ; Untyped                            ;
; OUTDATA_ACLR_B                     ; NONE                         ; Untyped                            ;
; RDCONTROL_ACLR_B                   ; NONE                         ; Untyped                            ;
; BYTEENA_ACLR_B                     ; NONE                         ; Untyped                            ;
; WIDTH_BYTEENA_A                    ; 1                            ; Untyped                            ;
; WIDTH_BYTEENA_B                    ; 1                            ; Untyped                            ;
; RAM_BLOCK_TYPE                     ; AUTO                         ; Untyped                            ;
; BYTE_SIZE                          ; 8                            ; Untyped                            ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                    ; Untyped                            ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ         ; Untyped                            ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ         ; Untyped                            ;
; INIT_FILE                          ; Equalizer.Equalizer1.rtl.mif ; Untyped                            ;
; INIT_FILE_LAYOUT                   ; PORT_A                       ; Untyped                            ;
; MAXIMUM_DEPTH                      ; 0                            ; Untyped                            ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL                       ; Untyped                            ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL                       ; Untyped                            ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL                       ; Untyped                            ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL                       ; Untyped                            ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN              ; Untyped                            ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN              ; Untyped                            ;
; ENABLE_ECC                         ; FALSE                        ; Untyped                            ;
; WIDTH_ECCSTATUS                    ; 3                            ; Untyped                            ;
; DEVICE_FAMILY                      ; Cyclone II                   ; Untyped                            ;
; CBXI_PARAMETER                     ; altsyncram_ek01              ; Untyped                            ;
+------------------------------------+------------------------------+------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: mmi:inst2|lcd_controller:inst2|altsyncram:Mux11_rtl_0 ;
+------------------------------------+------------------------------+------------------------------------+
; Parameter Name                     ; Value                        ; Type                               ;
+------------------------------------+------------------------------+------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                            ; Untyped                            ;
; AUTO_CARRY_CHAINS                  ; ON                           ; AUTO_CARRY                         ;
; IGNORE_CARRY_BUFFERS               ; OFF                          ; IGNORE_CARRY                       ;
; AUTO_CASCADE_CHAINS                ; ON                           ; AUTO_CASCADE                       ;
; IGNORE_CASCADE_BUFFERS             ; OFF                          ; IGNORE_CASCADE                     ;
; WIDTH_BYTEENA                      ; 1                            ; Untyped                            ;
; OPERATION_MODE                     ; ROM                          ; Untyped                            ;
; WIDTH_A                            ; 1                            ; Untyped                            ;
; WIDTHAD_A                          ; 5                            ; Untyped                            ;
; NUMWORDS_A                         ; 32                           ; Untyped                            ;
; OUTDATA_REG_A                      ; UNREGISTERED                 ; Untyped                            ;
; ADDRESS_ACLR_A                     ; NONE                         ; Untyped                            ;
; OUTDATA_ACLR_A                     ; NONE                         ; Untyped                            ;
; WRCONTROL_ACLR_A                   ; NONE                         ; Untyped                            ;
; INDATA_ACLR_A                      ; NONE                         ; Untyped                            ;
; BYTEENA_ACLR_A                     ; NONE                         ; Untyped                            ;
; WIDTH_B                            ; 1                            ; Untyped                            ;
; WIDTHAD_B                          ; 1                            ; Untyped                            ;
; NUMWORDS_B                         ; 1                            ; Untyped                            ;
; INDATA_REG_B                       ; CLOCK1                       ; Untyped                            ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1                       ; Untyped                            ;
; RDCONTROL_REG_B                    ; CLOCK1                       ; Untyped                            ;
; ADDRESS_REG_B                      ; CLOCK1                       ; Untyped                            ;
; OUTDATA_REG_B                      ; UNREGISTERED                 ; Untyped                            ;
; BYTEENA_REG_B                      ; CLOCK1                       ; Untyped                            ;
; INDATA_ACLR_B                      ; NONE                         ; Untyped                            ;
; WRCONTROL_ACLR_B                   ; NONE                         ; Untyped                            ;
; ADDRESS_ACLR_B                     ; NONE                         ; Untyped                            ;
; OUTDATA_ACLR_B                     ; NONE                         ; Untyped                            ;
; RDCONTROL_ACLR_B                   ; NONE                         ; Untyped                            ;
; BYTEENA_ACLR_B                     ; NONE                         ; Untyped                            ;
; WIDTH_BYTEENA_A                    ; 1                            ; Untyped                            ;
; WIDTH_BYTEENA_B                    ; 1                            ; Untyped                            ;
; RAM_BLOCK_TYPE                     ; AUTO                         ; Untyped                            ;
; BYTE_SIZE                          ; 8                            ; Untyped                            ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                    ; Untyped                            ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ         ; Untyped                            ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ         ; Untyped                            ;
; INIT_FILE                          ; Equalizer.Equalizer2.rtl.mif ; Untyped                            ;
; INIT_FILE_LAYOUT                   ; PORT_A                       ; Untyped                            ;
; MAXIMUM_DEPTH                      ; 0                            ; Untyped                            ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL                       ; Untyped                            ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL                       ; Untyped                            ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL                       ; Untyped                            ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL                       ; Untyped                            ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN              ; Untyped                            ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN              ; Untyped                            ;
; ENABLE_ECC                         ; FALSE                        ; Untyped                            ;
; WIDTH_ECCSTATUS                    ; 3                            ; Untyped                            ;
; DEVICE_FAMILY                      ; Cyclone II                   ; Untyped                            ;
; CBXI_PARAMETER                     ; altsyncram_fk01              ; Untyped                            ;
+------------------------------------+------------------------------+------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: mmi:inst2|lcd_controller:inst2|altsyncram:Mux10_rtl_0 ;
+------------------------------------+------------------------------+------------------------------------+
; Parameter Name                     ; Value                        ; Type                               ;
+------------------------------------+------------------------------+------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                            ; Untyped                            ;
; AUTO_CARRY_CHAINS                  ; ON                           ; AUTO_CARRY                         ;
; IGNORE_CARRY_BUFFERS               ; OFF                          ; IGNORE_CARRY                       ;
; AUTO_CASCADE_CHAINS                ; ON                           ; AUTO_CASCADE                       ;
; IGNORE_CASCADE_BUFFERS             ; OFF                          ; IGNORE_CASCADE                     ;
; WIDTH_BYTEENA                      ; 1                            ; Untyped                            ;
; OPERATION_MODE                     ; ROM                          ; Untyped                            ;
; WIDTH_A                            ; 1                            ; Untyped                            ;
; WIDTHAD_A                          ; 5                            ; Untyped                            ;
; NUMWORDS_A                         ; 32                           ; Untyped                            ;
; OUTDATA_REG_A                      ; UNREGISTERED                 ; Untyped                            ;
; ADDRESS_ACLR_A                     ; NONE                         ; Untyped                            ;
; OUTDATA_ACLR_A                     ; NONE                         ; Untyped                            ;
; WRCONTROL_ACLR_A                   ; NONE                         ; Untyped                            ;
; INDATA_ACLR_A                      ; NONE                         ; Untyped                            ;
; BYTEENA_ACLR_A                     ; NONE                         ; Untyped                            ;
; WIDTH_B                            ; 1                            ; Untyped                            ;
; WIDTHAD_B                          ; 1                            ; Untyped                            ;
; NUMWORDS_B                         ; 1                            ; Untyped                            ;
; INDATA_REG_B                       ; CLOCK1                       ; Untyped                            ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1                       ; Untyped                            ;
; RDCONTROL_REG_B                    ; CLOCK1                       ; Untyped                            ;
; ADDRESS_REG_B                      ; CLOCK1                       ; Untyped                            ;
; OUTDATA_REG_B                      ; UNREGISTERED                 ; Untyped                            ;
; BYTEENA_REG_B                      ; CLOCK1                       ; Untyped                            ;
; INDATA_ACLR_B                      ; NONE                         ; Untyped                            ;
; WRCONTROL_ACLR_B                   ; NONE                         ; Untyped                            ;
; ADDRESS_ACLR_B                     ; NONE                         ; Untyped                            ;
; OUTDATA_ACLR_B                     ; NONE                         ; Untyped                            ;
; RDCONTROL_ACLR_B                   ; NONE                         ; Untyped                            ;
; BYTEENA_ACLR_B                     ; NONE                         ; Untyped                            ;
; WIDTH_BYTEENA_A                    ; 1                            ; Untyped                            ;
; WIDTH_BYTEENA_B                    ; 1                            ; Untyped                            ;
; RAM_BLOCK_TYPE                     ; AUTO                         ; Untyped                            ;
; BYTE_SIZE                          ; 8                            ; Untyped                            ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                    ; Untyped                            ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ         ; Untyped                            ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ         ; Untyped                            ;
; INIT_FILE                          ; Equalizer.Equalizer3.rtl.mif ; Untyped                            ;
; INIT_FILE_LAYOUT                   ; PORT_A                       ; Untyped                            ;
; MAXIMUM_DEPTH                      ; 0                            ; Untyped                            ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL                       ; Untyped                            ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL                       ; Untyped                            ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL                       ; Untyped                            ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL                       ; Untyped                            ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN              ; Untyped                            ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN              ; Untyped                            ;
; ENABLE_ECC                         ; FALSE                        ; Untyped                            ;
; WIDTH_ECCSTATUS                    ; 3                            ; Untyped                            ;
; DEVICE_FAMILY                      ; Cyclone II                   ; Untyped                            ;
; CBXI_PARAMETER                     ; altsyncram_gk01              ; Untyped                            ;
+------------------------------------+------------------------------+------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: mmi:inst2|lcd_controller:inst2|altsyncram:Mux9_rtl_0 ;
+------------------------------------+------------------------------+-----------------------------------+
; Parameter Name                     ; Value                        ; Type                              ;
+------------------------------------+------------------------------+-----------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                            ; Untyped                           ;
; AUTO_CARRY_CHAINS                  ; ON                           ; AUTO_CARRY                        ;
; IGNORE_CARRY_BUFFERS               ; OFF                          ; IGNORE_CARRY                      ;
; AUTO_CASCADE_CHAINS                ; ON                           ; AUTO_CASCADE                      ;
; IGNORE_CASCADE_BUFFERS             ; OFF                          ; IGNORE_CASCADE                    ;
; WIDTH_BYTEENA                      ; 1                            ; Untyped                           ;
; OPERATION_MODE                     ; ROM                          ; Untyped                           ;
; WIDTH_A                            ; 1                            ; Untyped                           ;
; WIDTHAD_A                          ; 5                            ; Untyped                           ;
; NUMWORDS_A                         ; 32                           ; Untyped                           ;
; OUTDATA_REG_A                      ; UNREGISTERED                 ; Untyped                           ;
; ADDRESS_ACLR_A                     ; NONE                         ; Untyped                           ;
; OUTDATA_ACLR_A                     ; NONE                         ; Untyped                           ;
; WRCONTROL_ACLR_A                   ; NONE                         ; Untyped                           ;
; INDATA_ACLR_A                      ; NONE                         ; Untyped                           ;
; BYTEENA_ACLR_A                     ; NONE                         ; Untyped                           ;
; WIDTH_B                            ; 1                            ; Untyped                           ;
; WIDTHAD_B                          ; 1                            ; Untyped                           ;
; NUMWORDS_B                         ; 1                            ; Untyped                           ;
; INDATA_REG_B                       ; CLOCK1                       ; Untyped                           ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1                       ; Untyped                           ;
; RDCONTROL_REG_B                    ; CLOCK1                       ; Untyped                           ;
; ADDRESS_REG_B                      ; CLOCK1                       ; Untyped                           ;
; OUTDATA_REG_B                      ; UNREGISTERED                 ; Untyped                           ;
; BYTEENA_REG_B                      ; CLOCK1                       ; Untyped                           ;
; INDATA_ACLR_B                      ; NONE                         ; Untyped                           ;
; WRCONTROL_ACLR_B                   ; NONE                         ; Untyped                           ;
; ADDRESS_ACLR_B                     ; NONE                         ; Untyped                           ;
; OUTDATA_ACLR_B                     ; NONE                         ; Untyped                           ;
; RDCONTROL_ACLR_B                   ; NONE                         ; Untyped                           ;
; BYTEENA_ACLR_B                     ; NONE                         ; Untyped                           ;
; WIDTH_BYTEENA_A                    ; 1                            ; Untyped                           ;
; WIDTH_BYTEENA_B                    ; 1                            ; Untyped                           ;
; RAM_BLOCK_TYPE                     ; AUTO                         ; Untyped                           ;
; BYTE_SIZE                          ; 8                            ; Untyped                           ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                    ; Untyped                           ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ         ; Untyped                           ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ         ; Untyped                           ;
; INIT_FILE                          ; Equalizer.Equalizer4.rtl.mif ; Untyped                           ;
; INIT_FILE_LAYOUT                   ; PORT_A                       ; Untyped                           ;
; MAXIMUM_DEPTH                      ; 0                            ; Untyped                           ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL                       ; Untyped                           ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL                       ; Untyped                           ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL                       ; Untyped                           ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL                       ; Untyped                           ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN              ; Untyped                           ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN              ; Untyped                           ;
; ENABLE_ECC                         ; FALSE                        ; Untyped                           ;
; WIDTH_ECCSTATUS                    ; 3                            ; Untyped                           ;
; DEVICE_FAMILY                      ; Cyclone II                   ; Untyped                           ;
; CBXI_PARAMETER                     ; altsyncram_hk01              ; Untyped                           ;
+------------------------------------+------------------------------+-----------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------+
; altpll Parameter Settings by Entity Instance                                                ;
+-------------------------------+-------------------------------------------------------------+
; Name                          ; Value                                                       ;
+-------------------------------+-------------------------------------------------------------+
; Number of entity instances    ; 2                                                           ;
; Entity Instance               ; clock_generator:inst3|altpll0:inst|altpll:altpll_component  ;
;     -- OPERATION_MODE         ; NO_COMPENSATION                                             ;
;     -- PLL_TYPE               ; AUTO                                                        ;
;     -- PRIMARY_CLOCK          ; INCLK0                                                      ;
;     -- INCLK0_INPUT_FREQUENCY ; 37037                                                       ;
;     -- INCLK1_INPUT_FREQUENCY ; 0                                                           ;
;     -- VCO_MULTIPLY_BY        ; 0                                                           ;
;     -- VCO_DIVIDE_BY          ; 0                                                           ;
; Entity Instance               ; clock_generator:inst3|altpll2:inst2|altpll:altpll_component ;
;     -- OPERATION_MODE         ; SOURCE_SYNCHRONOUS                                          ;
;     -- PLL_TYPE               ; AUTO                                                        ;
;     -- PRIMARY_CLOCK          ; INCLK0                                                      ;
;     -- INCLK0_INPUT_FREQUENCY ; 20000                                                       ;
;     -- INCLK1_INPUT_FREQUENCY ; 0                                                           ;
;     -- VCO_MULTIPLY_BY        ; 0                                                           ;
;     -- VCO_DIVIDE_BY          ; 0                                                           ;
+-------------------------------+-------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------+
; altsyncram Parameter Settings by Entity Instance                                                  ;
+-------------------------------------------+-------------------------------------------------------+
; Name                                      ; Value                                                 ;
+-------------------------------------------+-------------------------------------------------------+
; Number of entity instances                ; 5                                                     ;
; Entity Instance                           ; mmi:inst2|lcd_controller:inst2|altsyncram:Mux13_rtl_0 ;
;     -- OPERATION_MODE                     ; ROM                                                   ;
;     -- WIDTH_A                            ; 1                                                     ;
;     -- NUMWORDS_A                         ; 32                                                    ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                          ;
;     -- WIDTH_B                            ; 1                                                     ;
;     -- NUMWORDS_B                         ; 1                                                     ;
;     -- ADDRESS_REG_B                      ; CLOCK1                                                ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                          ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                  ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                             ;
; Entity Instance                           ; mmi:inst2|lcd_controller:inst2|altsyncram:Mux12_rtl_0 ;
;     -- OPERATION_MODE                     ; ROM                                                   ;
;     -- WIDTH_A                            ; 1                                                     ;
;     -- NUMWORDS_A                         ; 32                                                    ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                          ;
;     -- WIDTH_B                            ; 1                                                     ;
;     -- NUMWORDS_B                         ; 1                                                     ;
;     -- ADDRESS_REG_B                      ; CLOCK1                                                ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                          ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                  ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                             ;
; Entity Instance                           ; mmi:inst2|lcd_controller:inst2|altsyncram:Mux11_rtl_0 ;
;     -- OPERATION_MODE                     ; ROM                                                   ;
;     -- WIDTH_A                            ; 1                                                     ;
;     -- NUMWORDS_A                         ; 32                                                    ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                          ;
;     -- WIDTH_B                            ; 1                                                     ;
;     -- NUMWORDS_B                         ; 1                                                     ;
;     -- ADDRESS_REG_B                      ; CLOCK1                                                ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                          ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                  ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                             ;
; Entity Instance                           ; mmi:inst2|lcd_controller:inst2|altsyncram:Mux10_rtl_0 ;
;     -- OPERATION_MODE                     ; ROM                                                   ;
;     -- WIDTH_A                            ; 1                                                     ;
;     -- NUMWORDS_A                         ; 32                                                    ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                          ;
;     -- WIDTH_B                            ; 1                                                     ;
;     -- NUMWORDS_B                         ; 1                                                     ;
;     -- ADDRESS_REG_B                      ; CLOCK1                                                ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                          ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                  ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                             ;
; Entity Instance                           ; mmi:inst2|lcd_controller:inst2|altsyncram:Mux9_rtl_0  ;
;     -- OPERATION_MODE                     ; ROM                                                   ;
;     -- WIDTH_A                            ; 1                                                     ;
;     -- NUMWORDS_A                         ; 32                                                    ;
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                          ;
;     -- WIDTH_B                            ; 1                                                     ;
;     -- NUMWORDS_B                         ; 1                                                     ;
;     -- ADDRESS_REG_B                      ; CLOCK1                                                ;
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                          ;
;     -- RAM_BLOCK_TYPE                     ; AUTO                                                  ;
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                             ;
+-------------------------------------------+-------------------------------------------------------+


+-------------------------------+
; Elapsed Time Per Partition    ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top            ; 00:00:07     ;
+----------------+--------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit Analysis & Synthesis
    Info: Version 11.1 Build 173 11/01/2011 SJ Full Version
    Info: Processing started: Fri Jun 08 00:35:48 2012
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Equalizer -c Equalizer
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (12021): Found 2 design units, including 1 entities, in source file dec_24bit_to_7seg.vhd
    Info (12022): Found design unit 1: dec_24bit_to_7seg-a_dec_24bit_to_7seg
    Info (12023): Found entity 1: dec_24bit_to_7seg
Info (12021): Found 1 design units, including 1 entities, in source file equalizer.bdf
    Info (12023): Found entity 1: Equalizer
Info (12021): Found 1 design units, including 1 entities, in source file audio_unit.bdf
    Info (12023): Found entity 1: audio_unit
Info (12021): Found 1 design units, including 1 entities, in source file audio_clock_generator.bdf
    Info (12023): Found entity 1: audio_clock_generator
Info (12021): Found 2 design units, including 1 entities, in source file audio_clock_divider.vhd
    Info (12022): Found design unit 1: audio_clock_divider-a_audio_clock_divider
    Info (12023): Found entity 1: audio_clock_divider
Info (12021): Found 2 design units, including 1 entities, in source file i2c_data_register.vhd
    Info (12022): Found design unit 1: i2c_data_register-a_i2c_data_register
    Info (12023): Found entity 1: i2c_data_register
Info (12021): Found 2 design units, including 1 entities, in source file i2c_transmitter.vhd
    Info (12022): Found design unit 1: i2c_transmitter-a_i2c_transmitter
    Info (12023): Found entity 1: i2c_transmitter
Info (12021): Found 2 design units, including 1 entities, in source file audio_input_register.vhd
    Info (12022): Found design unit 1: audio_input_register-behavior
    Info (12023): Found entity 1: audio_input_register
Info (12021): Found 2 design units, including 1 entities, in source file audio_output_register.vhd
    Info (12022): Found design unit 1: audio_output_register-behavior
    Info (12023): Found entity 1: audio_output_register
Info (12021): Found 1 design units, including 1 entities, in source file clock_generator.bdf
    Info (12023): Found entity 1: clock_generator
Info (12021): Found 1 design units, including 1 entities, in source file filter_unit.bdf
    Info (12023): Found entity 1: filter_unit
Info (12021): Found 2 design units, including 1 entities, in source file filter_arithmetic_unit.vhd
    Info (12022): Found design unit 1: filter_arithmetic_unit-behavior
    Info (12023): Found entity 1: filter_arithmetic_unit
Info (12021): Found 2 design units, including 1 entities, in source file audio_test.vhd
    Info (12022): Found design unit 1: audio_test-behavior
    Info (12023): Found entity 1: audio_test
Info (12021): Found 2 design units, including 1 entities, in source file mmi_input_mux.vhd
    Info (12022): Found design unit 1: mmi_input_mux-behavior
    Info (12023): Found entity 1: mmi_input_mux
Info (12021): Found 2 design units, including 1 entities, in source file mmi_7seg_decoder.vhd
    Info (12022): Found design unit 1: mmi_7seg_decoder-behavior
    Info (12023): Found entity 1: mmi_7seg_decoder
Info (12021): Found 2 design units, including 1 entities, in source file audio_db_to_factor_decoder.vhd
    Info (12022): Found design unit 1: audio_db_to_factor_decoder-behavior
    Info (12023): Found entity 1: audio_db_to_factor_decoder
Info (12021): Found 2 design units, including 1 entities, in source file altpll0.vhd
    Info (12022): Found design unit 1: altpll0-SYN
    Info (12023): Found entity 1: altpll0
Info (12021): Found 1 design units, including 1 entities, in source file mmi.bdf
    Info (12023): Found entity 1: mmi
Info (12021): Found 2 design units, including 1 entities, in source file mmi_controller.vhd
    Info (12022): Found design unit 1: mmi_controller-behavior
    Info (12023): Found entity 1: mmi_controller
Info (12021): Found 2 design units, including 1 entities, in source file filter_construction_unit.vhd
    Info (12022): Found design unit 1: filter_construction_unit-behavior
    Info (12023): Found entity 1: filter_construction_unit
Info (12021): Found 2 design units, including 1 entities, in source file iir_sos_element.vhd
    Info (12022): Found design unit 1: iir_sos_element-behavior
    Info (12023): Found entity 1: iir_sos_element
Info (12021): Found 2 design units, including 1 entities, in source file altpll1.vhd
    Info (12022): Found design unit 1: altpll1-SYN
    Info (12023): Found entity 1: altpll1
Info (12021): Found 2 design units, including 1 entities, in source file altpll2.vhd
    Info (12022): Found design unit 1: altpll2-SYN
    Info (12023): Found entity 1: altpll2
Info (12021): Found 2 design units, including 1 entities, in source file iir.vhd
    Info (12022): Found design unit 1: iir-behavior
    Info (12023): Found entity 1: iir
Info (12021): Found 2 design units, including 1 entities, in source file altpll3.vhd
    Info (12022): Found design unit 1: altpll3-SYN
    Info (12023): Found entity 1: altpll3
Info (12127): Elaborating entity "Equalizer" for the top level hierarchy
Info (12128): Elaborating entity "audio_unit" for hierarchy "audio_unit:inst"
Warning (275009): Pin "MUTE" not connected
Warning (275008): Primitive "AND2" of instance "inst3" not used
Info (12128): Elaborating entity "i2c_transmitter" for hierarchy "audio_unit:inst|i2c_transmitter:inst"
Info (10035): Verilog HDL or VHDL information at i2c_transmitter.vhd(13): object "clk" declared but not used
Info (10035): Verilog HDL or VHDL information at i2c_transmitter.vhd(29): object "ack" declared but not used
Warning (10862): input port "clk" at i2c_transmitter.vhd(13) has no fan-out
Warning (10862): bidir port "sdin" at i2c_transmitter.vhd(20) has no fan-out
Info (12128): Elaborating entity "i2c_data_register" for hierarchy "audio_unit:inst|i2c_data_register:inst4"
Info (10035): Verilog HDL or VHDL information at i2c_data_register.vhd(26): object "clk_counter" declared but not used
Info (12128): Elaborating entity "audio_input_register" for hierarchy "audio_unit:inst|audio_input_register:inst1"
Info (12128): Elaborating entity "audio_db_to_factor_decoder" for hierarchy "audio_unit:inst|audio_db_to_factor_decoder:inst10"
Info (12128): Elaborating entity "filter_unit" for hierarchy "audio_unit:inst|filter_unit:inst12"
Info (12128): Elaborating entity "filter_arithmetic_unit" for hierarchy "audio_unit:inst|filter_unit:inst12|filter_arithmetic_unit:inst"
Info (10035): Verilog HDL or VHDL information at filter_arithmetic_unit.vhd(35): object "f2" declared but not used
Info (10035): Verilog HDL or VHDL information at filter_arithmetic_unit.vhd(36): object "f3" declared but not used
Info (10035): Verilog HDL or VHDL information at filter_arithmetic_unit.vhd(37): object "f4" declared but not used
Info (10035): Verilog HDL or VHDL information at filter_arithmetic_unit.vhd(38): object "f5" declared but not used
Info (10035): Verilog HDL or VHDL information at filter_arithmetic_unit.vhd(39): object "f6" declared but not used
Info (10035): Verilog HDL or VHDL information at filter_arithmetic_unit.vhd(40): object "f7" declared but not used
Info (10035): Verilog HDL or VHDL information at filter_arithmetic_unit.vhd(41): object "f8" declared but not used
Info (10035): Verilog HDL or VHDL information at filter_arithmetic_unit.vhd(42): object "f9" declared but not used
Info (10035): Verilog HDL or VHDL information at filter_arithmetic_unit.vhd(43): object "f10" declared but not used
Info (10035): Verilog HDL or VHDL information at filter_arithmetic_unit.vhd(44): object "f11" declared but not used
Info (10035): Verilog HDL or VHDL information at filter_arithmetic_unit.vhd(45): object "f12" declared but not used
Info (10035): Verilog HDL or VHDL information at filter_arithmetic_unit.vhd(46): object "f13" declared but not used
Info (10035): Verilog HDL or VHDL information at filter_arithmetic_unit.vhd(47): object "f14" declared but not used
Info (10035): Verilog HDL or VHDL information at filter_arithmetic_unit.vhd(71): object "el" declared but not used
Info (10035): Verilog HDL or VHDL information at filter_arithmetic_unit.vhd(73): object "yl" declared but not used
Info (10035): Verilog HDL or VHDL information at filter_arithmetic_unit.vhd(74): object "yr" declared but not used
Info (10035): Verilog HDL or VHDL information at filter_arithmetic_unit.vhd(93): object "tmp" declared but not used
Warning (10862): input port "f2" at filter_arithmetic_unit.vhd(35) has no fan-out
Warning (10862): input port "f3" at filter_arithmetic_unit.vhd(36) has no fan-out
Warning (10862): input port "f4" at filter_arithmetic_unit.vhd(37) has no fan-out
Warning (10862): input port "f5" at filter_arithmetic_unit.vhd(38) has no fan-out
Warning (10862): input port "f6" at filter_arithmetic_unit.vhd(39) has no fan-out
Warning (10862): input port "f7" at filter_arithmetic_unit.vhd(40) has no fan-out
Warning (10862): input port "f8" at filter_arithmetic_unit.vhd(41) has no fan-out
Warning (10862): input port "f9" at filter_arithmetic_unit.vhd(42) has no fan-out
Warning (10862): input port "f10" at filter_arithmetic_unit.vhd(43) has no fan-out
Warning (10862): input port "f11" at filter_arithmetic_unit.vhd(44) has no fan-out
Warning (10862): input port "f12" at filter_arithmetic_unit.vhd(45) has no fan-out
Warning (10862): input port "f13" at filter_arithmetic_unit.vhd(46) has no fan-out
Warning (10862): input port "f14" at filter_arithmetic_unit.vhd(47) has no fan-out
Info (12128): Elaborating entity "iir" for hierarchy "audio_unit:inst|filter_unit:inst12|filter_arithmetic_unit:inst|iir:filter"
Info (10035): Verilog HDL or VHDL information at iir.vhd(27): object "v" declared but not used
Warning (10036): Verilog HDL or VHDL warning at iir.vhd(165): object "a0" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at iir.vhd(169): object "s2" assigned a value but never read
Info (10035): Verilog HDL or VHDL information at iir.vhd(175): object "tmp3" declared but not used
Info (10035): Verilog HDL or VHDL information at iir.vhd(176): object "tmp4" declared but not used
Warning (10862): input port "v" at iir.vhd(27) has no fan-out
Info (12128): Elaborating entity "audio_output_register" for hierarchy "audio_unit:inst|audio_output_register:inst2"
Info (12128): Elaborating entity "clock_generator" for hierarchy "clock_generator:inst3"
Info (12128): Elaborating entity "altpll0" for hierarchy "clock_generator:inst3|altpll0:inst"
Info (12128): Elaborating entity "altpll" for hierarchy "clock_generator:inst3|altpll0:inst|altpll:altpll_component"
Info (12130): Elaborated megafunction instantiation "clock_generator:inst3|altpll0:inst|altpll:altpll_component"
Info (12133): Instantiated megafunction "clock_generator:inst3|altpll0:inst|altpll:altpll_component" with the following parameter:
    Info (12134): Parameter "clk0_divide_by" = "9"
    Info (12134): Parameter "clk0_duty_cycle" = "50"
    Info (12134): Parameter "clk0_multiply_by" = "4"
    Info (12134): Parameter "clk0_phase_shift" = "0"
    Info (12134): Parameter "inclk0_input_frequency" = "37037"
    Info (12134): Parameter "intended_device_family" = "Cyclone II"
    Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=altpll0"
    Info (12134): Parameter "lpm_type" = "altpll"
    Info (12134): Parameter "operation_mode" = "NO_COMPENSATION"
    Info (12134): Parameter "port_activeclock" = "PORT_UNUSED"
    Info (12134): Parameter "port_areset" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkloss" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED"
    Info (12134): Parameter "port_configupdate" = "PORT_UNUSED"
    Info (12134): Parameter "port_fbin" = "PORT_UNUSED"
    Info (12134): Parameter "port_inclk0" = "PORT_USED"
    Info (12134): Parameter "port_inclk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_locked" = "PORT_UNUSED"
    Info (12134): Parameter "port_pfdena" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasedone" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasestep" = "PORT_UNUSED"
    Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED"
    Info (12134): Parameter "port_pllena" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanclk" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandata" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandataout" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandone" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanread" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk0" = "PORT_USED"
    Info (12134): Parameter "port_clk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk2" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk3" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk4" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk5" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena0" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena2" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena3" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena4" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena5" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk0" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk2" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk3" = "PORT_UNUSED"
Info (12128): Elaborating entity "altpll2" for hierarchy "clock_generator:inst3|altpll2:inst2"
Info (12128): Elaborating entity "altpll" for hierarchy "clock_generator:inst3|altpll2:inst2|altpll:altpll_component"
Info (12130): Elaborated megafunction instantiation "clock_generator:inst3|altpll2:inst2|altpll:altpll_component"
Info (12133): Instantiated megafunction "clock_generator:inst3|altpll2:inst2|altpll:altpll_component" with the following parameter:
    Info (12134): Parameter "compensate_clock" = "CLK0"
    Info (12134): Parameter "inclk0_input_frequency" = "20000"
    Info (12134): Parameter "intended_device_family" = "Cyclone II"
    Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=altpll2"
    Info (12134): Parameter "lpm_type" = "altpll"
    Info (12134): Parameter "m" = "16"
    Info (12134): Parameter "m_initial" = "1"
    Info (12134): Parameter "m_ph" = "0"
    Info (12134): Parameter "n" = "1"
    Info (12134): Parameter "operation_mode" = "SOURCE_SYNCHRONOUS"
    Info (12134): Parameter "port_activeclock" = "PORT_UNUSED"
    Info (12134): Parameter "port_areset" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkloss" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED"
    Info (12134): Parameter "port_configupdate" = "PORT_UNUSED"
    Info (12134): Parameter "port_fbin" = "PORT_UNUSED"
    Info (12134): Parameter "port_inclk0" = "PORT_USED"
    Info (12134): Parameter "port_inclk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_locked" = "PORT_UNUSED"
    Info (12134): Parameter "port_pfdena" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasedone" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasestep" = "PORT_UNUSED"
    Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED"
    Info (12134): Parameter "port_pllena" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanclk" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandata" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandataout" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandone" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanread" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk0" = "PORT_USED"
    Info (12134): Parameter "port_clk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk2" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk3" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk4" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk5" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena0" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena2" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena3" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena4" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena5" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk0" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk2" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk3" = "PORT_UNUSED"
    Info (12134): Parameter "vco_post_scale" = "1"
    Info (12134): Parameter "c0_high" = "8"
    Info (12134): Parameter "c0_initial" = "1"
    Info (12134): Parameter "c0_low" = "8"
    Info (12134): Parameter "c0_mode" = "even"
    Info (12134): Parameter "c0_ph" = "0"
    Info (12134): Parameter "clk0_counter" = "c0"
Info (12128): Elaborating entity "audio_clock_divider" for hierarchy "clock_generator:inst3|audio_clock_divider:inst1"
Info (12128): Elaborating entity "mmi" for hierarchy "mmi:inst2"
Warning (12125): Using design file lcd_controller.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info (12022): Found design unit 1: lcd_controller-a_lcd_controller
    Info (12023): Found entity 1: lcd_controller
Info (12128): Elaborating entity "lcd_controller" for hierarchy "mmi:inst2|lcd_controller:inst2"
Warning (10862): input port "lcd_1[11..9]" at lcd_controller.vhd(14) has no fan-out
Warning (10862): input port "lcd_2[11..9]" at lcd_controller.vhd(15) has no fan-out
Warning (10862): input port "lcd_3[11..9]" at lcd_controller.vhd(16) has no fan-out
Warning (10862): input port "lcd_4[11..9]" at lcd_controller.vhd(17) has no fan-out
Warning (10862): input port "lcd_5[11..9]" at lcd_controller.vhd(18) has no fan-out
Warning (10862): input port "lcd_6[11..9]" at lcd_controller.vhd(19) has no fan-out
Warning (10862): bidir port "lcd_data" at lcd_controller.vhd(29) has no fan-out
Info (12128): Elaborating entity "mmi_controller" for hierarchy "mmi:inst2|mmi_controller:inst"
Info (10035): Verilog HDL or VHDL information at mmi_controller.vhd(73): object "incdec" declared but not used
Info (10035): Verilog HDL or VHDL information at mmi_controller.vhd(74): object "inc_f" declared but not used
Info (10035): Verilog HDL or VHDL information at mmi_controller.vhd(75): object "dec_f" declared but not used
Info (10035): Verilog HDL or VHDL information at mmi_controller.vhd(125): object "tmp" declared but not used
Info (19000): Inferred 5 megafunctions from design logic
    Info (276031): Inferred altsyncram megafunction from the following design logic: "mmi:inst2|lcd_controller:inst2|Mux13_rtl_0"
        Info (286033): Parameter OPERATION_MODE set to ROM
        Info (286033): Parameter WIDTH_A set to 1
        Info (286033): Parameter WIDTHAD_A set to 5
        Info (286033): Parameter NUMWORDS_A set to 32
        Info (286033): Parameter OUTDATA_REG_A set to UNREGISTERED
        Info (286033): Parameter RAM_BLOCK_TYPE set to AUTO
        Info (286033): Parameter INIT_FILE set to Equalizer.Equalizer0.rtl.mif
    Info (276031): Inferred altsyncram megafunction from the following design logic: "mmi:inst2|lcd_controller:inst2|Mux12_rtl_0"
        Info (286033): Parameter OPERATION_MODE set to ROM
        Info (286033): Parameter WIDTH_A set to 1
        Info (286033): Parameter WIDTHAD_A set to 5
        Info (286033): Parameter NUMWORDS_A set to 32
        Info (286033): Parameter OUTDATA_REG_A set to UNREGISTERED
        Info (286033): Parameter RAM_BLOCK_TYPE set to AUTO
        Info (286033): Parameter INIT_FILE set to Equalizer.Equalizer1.rtl.mif
    Info (276031): Inferred altsyncram megafunction from the following design logic: "mmi:inst2|lcd_controller:inst2|Mux11_rtl_0"
        Info (286033): Parameter OPERATION_MODE set to ROM
        Info (286033): Parameter WIDTH_A set to 1
        Info (286033): Parameter WIDTHAD_A set to 5
        Info (286033): Parameter NUMWORDS_A set to 32
        Info (286033): Parameter OUTDATA_REG_A set to UNREGISTERED
        Info (286033): Parameter RAM_BLOCK_TYPE set to AUTO
        Info (286033): Parameter INIT_FILE set to Equalizer.Equalizer2.rtl.mif
    Info (276031): Inferred altsyncram megafunction from the following design logic: "mmi:inst2|lcd_controller:inst2|Mux10_rtl_0"
        Info (286033): Parameter OPERATION_MODE set to ROM
        Info (286033): Parameter WIDTH_A set to 1
        Info (286033): Parameter WIDTHAD_A set to 5
        Info (286033): Parameter NUMWORDS_A set to 32
        Info (286033): Parameter OUTDATA_REG_A set to UNREGISTERED
        Info (286033): Parameter RAM_BLOCK_TYPE set to AUTO
        Info (286033): Parameter INIT_FILE set to Equalizer.Equalizer3.rtl.mif
    Info (276031): Inferred altsyncram megafunction from the following design logic: "mmi:inst2|lcd_controller:inst2|Mux9_rtl_0"
        Info (286033): Parameter OPERATION_MODE set to ROM
        Info (286033): Parameter WIDTH_A set to 1
        Info (286033): Parameter WIDTHAD_A set to 5
        Info (286033): Parameter NUMWORDS_A set to 32
        Info (286033): Parameter OUTDATA_REG_A set to UNREGISTERED
        Info (286033): Parameter RAM_BLOCK_TYPE set to AUTO
        Info (286033): Parameter INIT_FILE set to Equalizer.Equalizer4.rtl.mif
Info (12130): Elaborated megafunction instantiation "mmi:inst2|lcd_controller:inst2|altsyncram:Mux13_rtl_0"
Info (12133): Instantiated megafunction "mmi:inst2|lcd_controller:inst2|altsyncram:Mux13_rtl_0" with the following parameter:
    Info (12134): Parameter "OPERATION_MODE" = "ROM"
    Info (12134): Parameter "WIDTH_A" = "1"
    Info (12134): Parameter "WIDTHAD_A" = "5"
    Info (12134): Parameter "NUMWORDS_A" = "32"
    Info (12134): Parameter "OUTDATA_REG_A" = "UNREGISTERED"
    Info (12134): Parameter "RAM_BLOCK_TYPE" = "AUTO"
    Info (12134): Parameter "INIT_FILE" = "Equalizer.Equalizer0.rtl.mif"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_dk01.tdf
    Info (12023): Found entity 1: altsyncram_dk01
Info (12130): Elaborated megafunction instantiation "mmi:inst2|lcd_controller:inst2|altsyncram:Mux12_rtl_0"
Info (12133): Instantiated megafunction "mmi:inst2|lcd_controller:inst2|altsyncram:Mux12_rtl_0" with the following parameter:
    Info (12134): Parameter "OPERATION_MODE" = "ROM"
    Info (12134): Parameter "WIDTH_A" = "1"
    Info (12134): Parameter "WIDTHAD_A" = "5"
    Info (12134): Parameter "NUMWORDS_A" = "32"
    Info (12134): Parameter "OUTDATA_REG_A" = "UNREGISTERED"
    Info (12134): Parameter "RAM_BLOCK_TYPE" = "AUTO"
    Info (12134): Parameter "INIT_FILE" = "Equalizer.Equalizer1.rtl.mif"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_ek01.tdf
    Info (12023): Found entity 1: altsyncram_ek01
Info (12130): Elaborated megafunction instantiation "mmi:inst2|lcd_controller:inst2|altsyncram:Mux11_rtl_0"
Info (12133): Instantiated megafunction "mmi:inst2|lcd_controller:inst2|altsyncram:Mux11_rtl_0" with the following parameter:
    Info (12134): Parameter "OPERATION_MODE" = "ROM"
    Info (12134): Parameter "WIDTH_A" = "1"
    Info (12134): Parameter "WIDTHAD_A" = "5"
    Info (12134): Parameter "NUMWORDS_A" = "32"
    Info (12134): Parameter "OUTDATA_REG_A" = "UNREGISTERED"
    Info (12134): Parameter "RAM_BLOCK_TYPE" = "AUTO"
    Info (12134): Parameter "INIT_FILE" = "Equalizer.Equalizer2.rtl.mif"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_fk01.tdf
    Info (12023): Found entity 1: altsyncram_fk01
Info (12130): Elaborated megafunction instantiation "mmi:inst2|lcd_controller:inst2|altsyncram:Mux10_rtl_0"
Info (12133): Instantiated megafunction "mmi:inst2|lcd_controller:inst2|altsyncram:Mux10_rtl_0" with the following parameter:
    Info (12134): Parameter "OPERATION_MODE" = "ROM"
    Info (12134): Parameter "WIDTH_A" = "1"
    Info (12134): Parameter "WIDTHAD_A" = "5"
    Info (12134): Parameter "NUMWORDS_A" = "32"
    Info (12134): Parameter "OUTDATA_REG_A" = "UNREGISTERED"
    Info (12134): Parameter "RAM_BLOCK_TYPE" = "AUTO"
    Info (12134): Parameter "INIT_FILE" = "Equalizer.Equalizer3.rtl.mif"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_gk01.tdf
    Info (12023): Found entity 1: altsyncram_gk01
Info (12130): Elaborated megafunction instantiation "mmi:inst2|lcd_controller:inst2|altsyncram:Mux9_rtl_0"
Info (12133): Instantiated megafunction "mmi:inst2|lcd_controller:inst2|altsyncram:Mux9_rtl_0" with the following parameter:
    Info (12134): Parameter "OPERATION_MODE" = "ROM"
    Info (12134): Parameter "WIDTH_A" = "1"
    Info (12134): Parameter "WIDTHAD_A" = "5"
    Info (12134): Parameter "NUMWORDS_A" = "32"
    Info (12134): Parameter "OUTDATA_REG_A" = "UNREGISTERED"
    Info (12134): Parameter "RAM_BLOCK_TYPE" = "AUTO"
    Info (12134): Parameter "INIT_FILE" = "Equalizer.Equalizer4.rtl.mif"
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_hk01.tdf
    Info (12023): Found entity 1: altsyncram_hk01
Warning (13034): The following nodes have both tri-state and non-tri-state drivers
    Warning (13035): Inserted always-enabled tri-state buffer between "LCD_DATA[7]" and its non-tri-state driver.
    Warning (13035): Inserted always-enabled tri-state buffer between "LCD_DATA[6]" and its non-tri-state driver.
    Warning (13035): Inserted always-enabled tri-state buffer between "LCD_DATA[5]" and its non-tri-state driver.
    Warning (13035): Inserted always-enabled tri-state buffer between "LCD_DATA[4]" and its non-tri-state driver.
    Warning (13035): Inserted always-enabled tri-state buffer between "LCD_DATA[3]" and its non-tri-state driver.
    Warning (13035): Inserted always-enabled tri-state buffer between "LCD_DATA[2]" and its non-tri-state driver.
    Warning (13035): Inserted always-enabled tri-state buffer between "LCD_DATA[1]" and its non-tri-state driver.
    Warning (13035): Inserted always-enabled tri-state buffer between "LCD_DATA[0]" and its non-tri-state driver.
Warning (13009): TRI or OPNDRN buffers permanently enabled
    Warning (13010): Node "LCD_DATA~synth"
    Warning (13010): Node "LCD_DATA~synth"
    Warning (13010): Node "LCD_DATA~synth"
    Warning (13010): Node "LCD_DATA~synth"
    Warning (13010): Node "LCD_DATA~synth"
    Warning (13010): Node "LCD_DATA~synth"
    Warning (13010): Node "LCD_DATA~synth"
    Warning (13010): Node "LCD_DATA~synth"
Warning (13024): Output pins are stuck at VCC or GND
    Warning (13410): Pin "I2C_SCLK" is stuck at GND
    Warning (13410): Pin "LCD_BLON" is stuck at VCC
    Warning (13410): Pin "LCD_ON" is stuck at VCC
    Warning (13410): Pin "LCD_RW" is stuck at GND
Info (17049): 8 registers lost all their fanouts during netlist optimizations. The first 8 are displayed below.
    Info (17050): Register "clock_generator:inst3|audio_clock_divider:inst1|c1M[9]" lost all its fanouts during netlist optimizations.
    Info (17050): Register "clock_generator:inst3|audio_clock_divider:inst1|c1M[8]" lost all its fanouts during netlist optimizations.
    Info (17050): Register "clock_generator:inst3|audio_clock_divider:inst1|c1M[7]" lost all its fanouts during netlist optimizations.
    Info (17050): Register "clock_generator:inst3|audio_clock_divider:inst1|c1M[6]" lost all its fanouts during netlist optimizations.
    Info (17050): Register "clock_generator:inst3|audio_clock_divider:inst1|c1M[5]" lost all its fanouts during netlist optimizations.
    Info (17050): Register "clock_generator:inst3|audio_clock_divider:inst1|c1M[4]" lost all its fanouts during netlist optimizations.
    Info (17050): Register "clock_generator:inst3|audio_clock_divider:inst1|c1M[3]" lost all its fanouts during netlist optimizations.
    Info (17050): Register "clock_generator:inst3|audio_clock_divider:inst1|c1M[2]" lost all its fanouts during netlist optimizations.
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
    Info (16011): Adding node "clock_generator:inst3|altpll0:inst|altpll:altpll_component|pll"
    Info (16011): Adding node "clock_generator:inst3|altpll2:inst2|altpll:altpll_component|pll"
Warning (21074): Design contains 5 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "AUD_ADCLRCK"
    Warning (15610): No output dependent on input pin "AUD_BCLK"
    Warning (15610): No output dependent on input pin "AUD_DACLRCK"
    Warning (15610): No output dependent on input pin "SW[2]"
    Warning (15610): No output dependent on input pin "SW[0]"
Info (21057): Implemented 1056 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 13 input pins
    Info (21059): Implemented 57 output pins
    Info (21060): Implemented 9 bidirectional pins
    Info (21061): Implemented 970 logic cells
    Info (21064): Implemented 5 RAM segments
    Info (21065): Implemented 2 PLLs
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 58 warnings
    Info: Peak virtual memory: 527 megabytes
    Info: Processing ended: Fri Jun 08 00:35:58 2012
    Info: Elapsed time: 00:00:10
    Info: Total CPU time (on all processors): 00:00:10


