ADDRESS_REG_B=CLOCK0
CLOCK_ENABLE_INPUT_A=BYPASS
CLOCK_ENABLE_INPUT_B=BYPASS
CLOCK_ENABLE_OUTPUT_A=BYPASS
CLOCK_ENABLE_OUTPUT_B=BYPASS
INTENDED_DEVICE_FAMILY="Cyclone II"
LPM_TYPE=altsyncram
NUMWORDS_A=32
NUMWORDS_B=32
OPERATION_MODE=DUAL_PORT
OUTDATA_ACLR_B=NONE
OUTDATA_REG_B=CLOCK0
POWER_UP_UNINITIALIZED=FALSE
RAM_BLOCK_TYPE=M4K
READ_DURING_WRITE_MODE_MIXED_PORTS=DONT_CARE
WIDTHAD_A=5
WIDTHAD_B=5
WIDTH_A=64
WIDTH_B=64
WIDTH_BYTEENA_A=1
DEVICE_FAMILY="Cyclone II"
address_a
address_b
clock0
data_a
wren_a
q_b