TimeQuest Timing Analyzer report for Equalizer
Fri May 22 21:51:09 2015
Quartus II 32-bit Version 13.0.0 Build 156 04/24/2013 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. Clocks
  5. Slow Model Fmax Summary
  6. Slow Model Setup Summary
  7. Slow Model Hold Summary
  8. Slow Model Recovery Summary
  9. Slow Model Removal Summary
 10. Slow Model Minimum Pulse Width Summary
 11. Slow Model Setup: 'clock_generator_1|pll_1|altpll_component|pll|clk[0]'
 12. Slow Model Setup: 'AUD_BCLK'
 13. Slow Model Setup: 'clock_generator_1|pll_2|altpll_component|pll|clk[1]'
 14. Slow Model Setup: 'audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr'
 15. Slow Model Setup: 'audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql'
 16. Slow Model Setup: 'CLOCK_27'
 17. Slow Model Setup: 'clock_generator_1|pll_1|altpll_component|pll|clk[1]'
 18. Slow Model Hold: 'audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr'
 19. Slow Model Hold: 'audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql'
 20. Slow Model Hold: 'clock_generator_1|pll_1|altpll_component|pll|clk[0]'
 21. Slow Model Hold: 'AUD_BCLK'
 22. Slow Model Hold: 'CLOCK_27'
 23. Slow Model Hold: 'clock_generator_1|pll_1|altpll_component|pll|clk[1]'
 24. Slow Model Hold: 'clock_generator_1|pll_2|altpll_component|pll|clk[1]'
 25. Slow Model Recovery: 'clock_generator_1|pll_2|altpll_component|pll|clk[1]'
 26. Slow Model Removal: 'clock_generator_1|pll_2|altpll_component|pll|clk[1]'
 27. Slow Model Minimum Pulse Width: 'AUD_BCLK'
 28. Slow Model Minimum Pulse Width: 'audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql'
 29. Slow Model Minimum Pulse Width: 'audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr'
 30. Slow Model Minimum Pulse Width: 'clock_generator_1|pll_1|altpll_component|pll|clk[0]'
 31. Slow Model Minimum Pulse Width: 'CLOCK_50'
 32. Slow Model Minimum Pulse Width: 'CLOCK_27'
 33. Slow Model Minimum Pulse Width: 'clock_generator_1|pll_2|altpll_component|pll|clk[1]'
 34. Slow Model Minimum Pulse Width: 'clock_generator_1|pll_1|altpll_component|pll|clk[1]'
 35. Setup Times
 36. Hold Times
 37. Clock to Output Times
 38. Minimum Clock to Output Times
 39. Propagation Delay
 40. Minimum Propagation Delay
 41. Output Enable Times
 42. Minimum Output Enable Times
 43. Output Disable Times
 44. Minimum Output Disable Times
 45. Fast Model Setup Summary
 46. Fast Model Hold Summary
 47. Fast Model Recovery Summary
 48. Fast Model Removal Summary
 49. Fast Model Minimum Pulse Width Summary
 50. Fast Model Setup: 'clock_generator_1|pll_1|altpll_component|pll|clk[0]'
 51. Fast Model Setup: 'clock_generator_1|pll_2|altpll_component|pll|clk[1]'
 52. Fast Model Setup: 'AUD_BCLK'
 53. Fast Model Setup: 'audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr'
 54. Fast Model Setup: 'audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql'
 55. Fast Model Setup: 'CLOCK_27'
 56. Fast Model Setup: 'clock_generator_1|pll_1|altpll_component|pll|clk[1]'
 57. Fast Model Hold: 'audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql'
 58. Fast Model Hold: 'audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr'
 59. Fast Model Hold: 'clock_generator_1|pll_1|altpll_component|pll|clk[0]'
 60. Fast Model Hold: 'AUD_BCLK'
 61. Fast Model Hold: 'CLOCK_27'
 62. Fast Model Hold: 'clock_generator_1|pll_1|altpll_component|pll|clk[1]'
 63. Fast Model Hold: 'clock_generator_1|pll_2|altpll_component|pll|clk[1]'
 64. Fast Model Recovery: 'clock_generator_1|pll_2|altpll_component|pll|clk[1]'
 65. Fast Model Removal: 'clock_generator_1|pll_2|altpll_component|pll|clk[1]'
 66. Fast Model Minimum Pulse Width: 'AUD_BCLK'
 67. Fast Model Minimum Pulse Width: 'audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql'
 68. Fast Model Minimum Pulse Width: 'audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr'
 69. Fast Model Minimum Pulse Width: 'clock_generator_1|pll_1|altpll_component|pll|clk[0]'
 70. Fast Model Minimum Pulse Width: 'CLOCK_50'
 71. Fast Model Minimum Pulse Width: 'CLOCK_27'
 72. Fast Model Minimum Pulse Width: 'clock_generator_1|pll_2|altpll_component|pll|clk[1]'
 73. Fast Model Minimum Pulse Width: 'clock_generator_1|pll_1|altpll_component|pll|clk[1]'
 74. Setup Times
 75. Hold Times
 76. Clock to Output Times
 77. Minimum Clock to Output Times
 78. Propagation Delay
 79. Minimum Propagation Delay
 80. Output Enable Times
 81. Minimum Output Enable Times
 82. Output Disable Times
 83. Minimum Output Disable Times
 84. Multicorner Timing Analysis Summary
 85. Setup Times
 86. Hold Times
 87. Clock to Output Times
 88. Minimum Clock to Output Times
 89. Progagation Delay
 90. Minimum Progagation Delay
 91. Setup Transfers
 92. Hold Transfers
 93. Recovery Transfers
 94. Removal Transfers
 95. Report TCCS
 96. Report RSKM
 97. Unconstrained Paths
 98. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
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to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                       ;
+--------------------+----------------------------------------------------+
; Quartus II Version ; Version 13.0.0 Build 156 04/24/2013 SJ Web Edition ;
; Revision Name      ; Equalizer                                          ;
; Device Family      ; Cyclone II                                         ;
; Device Name        ; EP2C35F672C6                                       ;
; Timing Models      ; Final                                              ;
; Delay Model        ; Combined                                           ;
; Rise/Fall Delays   ; Unavailable                                        ;
+--------------------+----------------------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 2           ;
; Maximum allowed            ; 2           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 2           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processor 2            ; < 0.1%      ;
+----------------------------+-------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                                                                                                                 ;
+--------------------------------------------------------+-----------+---------+------------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+----------+-------------------------------------------------------+------------------------------------------------------------+
; Clock Name                                             ; Type      ; Period  ; Frequency  ; Rise  ; Fall   ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master   ; Source                                                ; Targets                                                    ;
+--------------------------------------------------------+-----------+---------+------------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+----------+-------------------------------------------------------+------------------------------------------------------------+
; AUD_BCLK                                               ; Base      ; 1.000   ; 1000.0 MHz ; 0.000 ; 0.500  ;            ;           ;             ;       ;        ;           ;            ;          ;          ;                                                       ; { AUD_BCLK }                                               ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Base      ; 1.000   ; 1000.0 MHz ; 0.000 ; 0.500  ;            ;           ;             ;       ;        ;           ;            ;          ;          ;                                                       ; { audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql } ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Base      ; 1.000   ; 1000.0 MHz ; 0.000 ; 0.500  ;            ;           ;             ;       ;        ;           ;            ;          ;          ;                                                       ; { audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr } ;
; CLOCK_27                                               ; Base      ; 37.037  ; 27.0 MHz   ; 0.000 ; 18.518 ;            ;           ;             ;       ;        ;           ;            ;          ;          ;                                                       ; { CLOCK_27 }                                               ;
; CLOCK_50                                               ; Base      ; 20.000  ; 50.0 MHz   ; 0.000 ; 10.000 ;            ;           ;             ;       ;        ;           ;            ;          ;          ;                                                       ; { CLOCK_50 }                                               ;
; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; Generated ; 20.000  ; 50.0 MHz   ; 0.000 ; 10.000 ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; CLOCK_50 ; clock_generator_1|pll_1|altpll_component|pll|inclk[0] ; { clock_generator_1|pll_1|altpll_component|pll|clk[0] }    ;
; clock_generator_1|pll_1|altpll_component|pll|clk[1]    ; Generated ; 100.000 ; 10.0 MHz   ; 0.000 ; 50.000 ; 50.00      ; 5         ; 1           ;       ;        ;           ;            ; false    ; CLOCK_50 ; clock_generator_1|pll_1|altpll_component|pll|inclk[0] ; { clock_generator_1|pll_1|altpll_component|pll|clk[1] }    ;
; clock_generator_1|pll_2|altpll_component|pll|clk[1]    ; Generated ; 83.333  ; 12.0 MHz   ; 0.000 ; 41.666 ; 50.00      ; 9         ; 4           ;       ;        ;           ;            ; false    ; CLOCK_27 ; clock_generator_1|pll_2|altpll_component|pll|inclk[0] ; { clock_generator_1|pll_2|altpll_component|pll|clk[1] }    ;
+--------------------------------------------------------+-----------+---------+------------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+----------+-------------------------------------------------------+------------------------------------------------------------+


+-------------------------------------------------------------------------------------------+
; Slow Model Fmax Summary                                                                   ;
+------------+-----------------+-----------------------------------------------------+------+
; Fmax       ; Restricted Fmax ; Clock Name                                          ; Note ;
+------------+-----------------+-----------------------------------------------------+------+
; 53.91 MHz  ; 53.91 MHz       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;      ;
; 146.37 MHz ; 146.37 MHz      ; CLOCK_27                                            ;      ;
; 160.9 MHz  ; 160.9 MHz       ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ;      ;
; 318.37 MHz ; 318.37 MHz      ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ;      ;
; 337.61 MHz ; 337.61 MHz      ; AUD_BCLK                                            ;      ;
+------------+-----------------+-----------------------------------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+---------------------------------------------------------------------------------+
; Slow Model Setup Summary                                                        ;
+--------------------------------------------------------+--------+---------------+
; Clock                                                  ; Slack  ; End Point TNS ;
+--------------------------------------------------------+--------+---------------+
; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; -5.130 ; -1103.783     ;
; AUD_BCLK                                               ; -1.962 ; -215.939      ;
; clock_generator_1|pll_2|altpll_component|pll|clk[1]    ; -1.791 ; -36.071       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.558  ; 0.000         ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.567  ; 0.000         ;
; CLOCK_27                                               ; 30.205 ; 0.000         ;
; clock_generator_1|pll_1|altpll_component|pll|clk[1]    ; 96.859 ; 0.000         ;
+--------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------+
; Slow Model Hold Summary                                                         ;
+--------------------------------------------------------+--------+---------------+
; Clock                                                  ; Slack  ; End Point TNS ;
+--------------------------------------------------------+--------+---------------+
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; -1.407 ; -23.818       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; -1.388 ; -26.503       ;
; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; -0.166 ; -0.317        ;
; AUD_BCLK                                               ; 0.154  ; 0.000         ;
; CLOCK_27                                               ; 0.391  ; 0.000         ;
; clock_generator_1|pll_1|altpll_component|pll|clk[1]    ; 0.391  ; 0.000         ;
; clock_generator_1|pll_2|altpll_component|pll|clk[1]    ; 0.391  ; 0.000         ;
+--------------------------------------------------------+--------+---------------+


+-----------------------------------------------------------------------------+
; Slow Model Recovery Summary                                                 ;
+-----------------------------------------------------+-------+---------------+
; Clock                                               ; Slack ; End Point TNS ;
+-----------------------------------------------------+-------+---------------+
; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 2.904 ; 0.000         ;
+-----------------------------------------------------+-------+---------------+


+-----------------------------------------------------------------------------+
; Slow Model Removal Summary                                                  ;
+-----------------------------------------------------+-------+---------------+
; Clock                                               ; Slack ; End Point TNS ;
+-----------------------------------------------------+-------+---------------+
; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 6.117 ; 0.000         ;
+-----------------------------------------------------+-------+---------------+


+---------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width Summary                                          ;
+--------------------------------------------------------+--------+---------------+
; Clock                                                  ; Slack  ; End Point TNS ;
+--------------------------------------------------------+--------+---------------+
; AUD_BCLK                                               ; -1.222 ; -142.222      ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; -0.500 ; -24.000       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; -0.500 ; -24.000       ;
; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; 8.077  ; 0.000         ;
; CLOCK_50                                               ; 10.000 ; 0.000         ;
; CLOCK_27                                               ; 17.518 ; 0.000         ;
; clock_generator_1|pll_2|altpll_component|pll|clk[1]    ; 40.666 ; 0.000         ;
; clock_generator_1|pll_1|altpll_component|pll|clk[1]    ; 49.000 ; 0.000         ;
+--------------------------------------------------------+--------+---------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'clock_generator_1|pll_1|altpll_component|pll|clk[0]'                                                                                                                                                    ;
+--------+-----------------------------------------+-----------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                               ; To Node                                                   ; Launch Clock ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------+-----------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
; -5.130 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f6_db[0]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.365     ; 2.802      ;
; -5.130 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f6_db[4]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.365     ; 2.802      ;
; -5.130 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f6_db[5]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.365     ; 2.802      ;
; -5.130 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f6_db[6]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.365     ; 2.802      ;
; -5.130 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f6_db[7]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.365     ; 2.802      ;
; -5.130 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f6_db[1]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.365     ; 2.802      ;
; -5.130 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f6_db[3]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.365     ; 2.802      ;
; -5.107 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f12_db[1]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.360     ; 2.784      ;
; -5.107 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f12_db[2]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.360     ; 2.784      ;
; -5.107 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f12_db[4]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.360     ; 2.784      ;
; -5.107 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f12_db[5]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.360     ; 2.784      ;
; -5.107 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f12_db[7]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.360     ; 2.784      ;
; -5.107 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f12_db[0]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.360     ; 2.784      ;
; -5.107 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f12_db[6]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.360     ; 2.784      ;
; -5.107 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f12_db[3]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.360     ; 2.784      ;
; -5.039 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f14_db[1]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.353     ; 2.723      ;
; -5.039 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f14_db[2]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.353     ; 2.723      ;
; -5.039 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f14_db[4]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.353     ; 2.723      ;
; -5.039 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f14_db[6]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.353     ; 2.723      ;
; -5.039 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f14_db[7]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.353     ; 2.723      ;
; -5.039 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f14_db[0]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.353     ; 2.723      ;
; -5.039 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f14_db[5]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.353     ; 2.723      ;
; -5.039 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f14_db[3]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.353     ; 2.723      ;
; -5.018 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[1]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.354     ; 2.701      ;
; -5.018 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[2]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.354     ; 2.701      ;
; -5.018 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[4]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.354     ; 2.701      ;
; -5.018 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[5]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.354     ; 2.701      ;
; -5.018 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[6]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.354     ; 2.701      ;
; -5.018 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[0]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.354     ; 2.701      ;
; -5.018 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[7]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.354     ; 2.701      ;
; -5.018 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[3]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.354     ; 2.701      ;
; -5.005 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f3_db[4]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.352     ; 2.690      ;
; -5.005 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f3_db[6]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.352     ; 2.690      ;
; -5.005 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f3_db[7]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.352     ; 2.690      ;
; -5.005 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f3_db[2]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.352     ; 2.690      ;
; -4.999 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f9_db[0]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.356     ; 2.680      ;
; -4.999 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f9_db[1]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.356     ; 2.680      ;
; -4.999 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f9_db[4]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.356     ; 2.680      ;
; -4.999 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f9_db[5]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.356     ; 2.680      ;
; -4.999 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f9_db[6]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.356     ; 2.680      ;
; -4.999 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f9_db[7]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.356     ; 2.680      ;
; -4.999 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f9_db[2]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.356     ; 2.680      ;
; -4.999 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f9_db[3]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.356     ; 2.680      ;
; -4.957 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f11_db[1]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.353     ; 2.641      ;
; -4.957 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f11_db[2]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.353     ; 2.641      ;
; -4.957 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f11_db[4]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.353     ; 2.641      ;
; -4.957 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f11_db[6]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.353     ; 2.641      ;
; -4.957 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f11_db[7]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.353     ; 2.641      ;
; -4.957 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f11_db[0]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.353     ; 2.641      ;
; -4.957 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f11_db[5]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.353     ; 2.641      ;
; -4.957 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f11_db[3]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.353     ; 2.641      ;
; -4.941 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f8_db[1]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.363     ; 2.615      ;
; -4.941 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f8_db[2]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.363     ; 2.615      ;
; -4.941 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f8_db[5]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.363     ; 2.615      ;
; -4.941 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f8_db[6]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.363     ; 2.615      ;
; -4.941 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f8_db[7]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.363     ; 2.615      ;
; -4.941 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f8_db[0]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.363     ; 2.615      ;
; -4.941 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f8_db[4]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.363     ; 2.615      ;
; -4.941 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f8_db[3]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.363     ; 2.615      ;
; -4.906 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|clk_counter[21] ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.371     ; 2.572      ;
; -4.906 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|clk_counter[15] ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.371     ; 2.572      ;
; -4.906 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|clk_counter[14] ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.371     ; 2.572      ;
; -4.906 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|clk_counter[17] ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.371     ; 2.572      ;
; -4.906 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|clk_counter[16] ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.371     ; 2.572      ;
; -4.906 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|clk_counter[18] ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.371     ; 2.572      ;
; -4.906 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|clk_counter[19] ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.371     ; 2.572      ;
; -4.906 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|clk_counter[20] ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.371     ; 2.572      ;
; -4.906 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|clk_counter[22] ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.371     ; 2.572      ;
; -4.906 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|clk_counter[24] ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.371     ; 2.572      ;
; -4.906 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|clk_counter[25] ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.371     ; 2.572      ;
; -4.906 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|clk_counter[26] ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.371     ; 2.572      ;
; -4.906 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|clk_counter[27] ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.371     ; 2.572      ;
; -4.906 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|clk_counter[23] ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.371     ; 2.572      ;
; -4.878 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f1_db[4]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.353     ; 2.562      ;
; -4.826 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|lcd_controller:lcd_controller_1|output[0]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.363     ; 2.500      ;
; -4.826 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|lcd_controller:lcd_controller_1|output[1]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.363     ; 2.500      ;
; -4.826 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|lcd_controller:lcd_controller_1|output[3]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.363     ; 2.500      ;
; -4.820 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|lcd_controller:lcd_controller_1|delay[9]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.350     ; 2.507      ;
; -4.820 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|lcd_controller:lcd_controller_1|delay[6]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.350     ; 2.507      ;
; -4.820 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|lcd_controller:lcd_controller_1|delay[7]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.350     ; 2.507      ;
; -4.820 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|lcd_controller:lcd_controller_1|delay[4]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.350     ; 2.507      ;
; -4.820 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|lcd_controller:lcd_controller_1|delay[5]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.350     ; 2.507      ;
; -4.820 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|lcd_controller:lcd_controller_1|delay[8]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.350     ; 2.507      ;
; -4.812 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|lcd_controller:lcd_controller_1|output[8]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.362     ; 2.487      ;
; -4.812 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|lcd_controller:lcd_controller_1|output[4]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.362     ; 2.487      ;
; -4.812 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|lcd_controller:lcd_controller_1|output[7]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.362     ; 2.487      ;
; -4.798 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f13_db[1]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.358     ; 2.477      ;
; -4.798 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f13_db[2]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.358     ; 2.477      ;
; -4.798 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f13_db[4]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.358     ; 2.477      ;
; -4.798 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f13_db[6]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.358     ; 2.477      ;
; -4.798 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f13_db[7]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.358     ; 2.477      ;
; -4.798 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f13_db[0]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.358     ; 2.477      ;
; -4.798 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f13_db[5]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.358     ; 2.477      ;
; -4.798 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f13_db[3]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.358     ; 2.477      ;
; -4.792 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|clk_counter[9]  ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.368     ; 2.461      ;
; -4.792 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|clk_counter[10] ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.368     ; 2.461      ;
; -4.792 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|clk_counter[11] ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.368     ; 2.461      ;
; -4.792 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|clk_counter[12] ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.368     ; 2.461      ;
; -4.792 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|clk_counter[13] ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.368     ; 2.461      ;
; -4.792 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|clk_counter[8]  ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -2.368     ; 2.461      ;
+--------+-----------------------------------------+-----------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'AUD_BCLK'                                                                                                                                                                                                                                                       ;
+--------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                        ; To Node                                                                                          ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; -1.962 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[1]           ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.029     ; 2.969      ;
; -1.962 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[2]           ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.029     ; 2.969      ;
; -1.962 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[3]           ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.029     ; 2.969      ;
; -1.962 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[4]           ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.029     ; 2.969      ;
; -1.962 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[5]           ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.029     ; 2.969      ;
; -1.962 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[6]           ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.029     ; 2.969      ;
; -1.962 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[7]           ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.029     ; 2.969      ;
; -1.962 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[8]           ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.026     ; 2.972      ;
; -1.962 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[9]           ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.026     ; 2.972      ;
; -1.962 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[18]          ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.026     ; 2.972      ;
; -1.962 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[19]          ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.026     ; 2.972      ;
; -1.962 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[20]          ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.026     ; 2.972      ;
; -1.962 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[21]          ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.026     ; 2.972      ;
; -1.962 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[22]          ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.029     ; 2.969      ;
; -1.962 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[23]          ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.026     ; 2.972      ;
; -1.943 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[10]          ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.031     ; 2.948      ;
; -1.943 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[11]          ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.031     ; 2.948      ;
; -1.943 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[12]          ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.031     ; 2.948      ;
; -1.943 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[13]          ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.031     ; 2.948      ;
; -1.943 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[14]          ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.031     ; 2.948      ;
; -1.943 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[15]          ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.031     ; 2.948      ;
; -1.943 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[16]          ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.031     ; 2.948      ;
; -1.943 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[17]          ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.031     ; 2.948      ;
; -1.934 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[1]           ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.021     ; 2.949      ;
; -1.934 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[2]           ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.021     ; 2.949      ;
; -1.934 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[3]           ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.021     ; 2.949      ;
; -1.934 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[4]           ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.021     ; 2.949      ;
; -1.934 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[5]           ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.021     ; 2.949      ;
; -1.934 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[6]           ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.021     ; 2.949      ;
; -1.934 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[7]           ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.021     ; 2.949      ;
; -1.934 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[8]           ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.021     ; 2.949      ;
; -1.933 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[9]           ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.019     ; 2.950      ;
; -1.933 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[10]          ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.019     ; 2.950      ;
; -1.933 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[11]          ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.019     ; 2.950      ;
; -1.933 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[12]          ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.019     ; 2.950      ;
; -1.933 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[13]          ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.019     ; 2.950      ;
; -1.933 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[14]          ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.019     ; 2.950      ;
; -1.933 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[15]          ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.019     ; 2.950      ;
; -1.933 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[16]          ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.019     ; 2.950      ;
; -1.933 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[17]          ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.019     ; 2.950      ;
; -1.914 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[1]           ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.029     ; 2.921      ;
; -1.914 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[2]           ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.029     ; 2.921      ;
; -1.914 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[3]           ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.029     ; 2.921      ;
; -1.914 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[4]           ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.029     ; 2.921      ;
; -1.914 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[5]           ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.029     ; 2.921      ;
; -1.914 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[6]           ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.029     ; 2.921      ;
; -1.914 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[7]           ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.029     ; 2.921      ;
; -1.914 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[8]           ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.026     ; 2.924      ;
; -1.914 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[9]           ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.026     ; 2.924      ;
; -1.914 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[18]          ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.026     ; 2.924      ;
; -1.914 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[19]          ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.026     ; 2.924      ;
; -1.914 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[20]          ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.026     ; 2.924      ;
; -1.914 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[21]          ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.026     ; 2.924      ;
; -1.914 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[22]          ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.029     ; 2.921      ;
; -1.914 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[23]          ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.026     ; 2.924      ;
; -1.895 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[10]          ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.031     ; 2.900      ;
; -1.895 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[11]          ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.031     ; 2.900      ;
; -1.895 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[12]          ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.031     ; 2.900      ;
; -1.895 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[13]          ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.031     ; 2.900      ;
; -1.895 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[14]          ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.031     ; 2.900      ;
; -1.895 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[15]          ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.031     ; 2.900      ;
; -1.895 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[16]          ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.031     ; 2.900      ;
; -1.895 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[17]          ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.031     ; 2.900      ;
; -1.886 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[1]           ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.021     ; 2.901      ;
; -1.886 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[2]           ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.021     ; 2.901      ;
; -1.886 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[3]           ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.021     ; 2.901      ;
; -1.886 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[4]           ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.021     ; 2.901      ;
; -1.886 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[5]           ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.021     ; 2.901      ;
; -1.886 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[6]           ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.021     ; 2.901      ;
; -1.886 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[7]           ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.021     ; 2.901      ;
; -1.886 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[8]           ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.021     ; 2.901      ;
; -1.885 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[9]           ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.019     ; 2.902      ;
; -1.885 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[10]          ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.019     ; 2.902      ;
; -1.885 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[11]          ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.019     ; 2.902      ;
; -1.885 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[12]          ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.019     ; 2.902      ;
; -1.885 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[13]          ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.019     ; 2.902      ;
; -1.885 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[14]          ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.019     ; 2.902      ;
; -1.885 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[15]          ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.019     ; 2.902      ;
; -1.885 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[16]          ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.019     ; 2.902      ;
; -1.885 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[17]          ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.019     ; 2.902      ;
; -1.835 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[3] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.181     ; 2.690      ;
; -1.787 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[3] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.181     ; 2.642      ;
; -1.780 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[4]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[0]                      ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; 0.577      ; 3.393      ;
; -1.780 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[4]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[1]                      ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; 0.577      ; 3.393      ;
; -1.780 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[4]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[16]                     ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; 0.577      ; 3.393      ;
; -1.780 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[4]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[17]                     ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; 0.577      ; 3.393      ;
; -1.780 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[4]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[18]                     ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; 0.577      ; 3.393      ;
; -1.780 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[4]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[20]                     ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; 0.577      ; 3.393      ;
; -1.780 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[4]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[21]                     ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; 0.577      ; 3.393      ;
; -1.780 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[4]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[22]                     ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; 0.577      ; 3.393      ;
; -1.772 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[2] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[1]           ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.029     ; 2.779      ;
; -1.772 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[2] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[2]           ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.029     ; 2.779      ;
; -1.772 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[2] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[3]           ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.029     ; 2.779      ;
; -1.772 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[2] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[4]           ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.029     ; 2.779      ;
; -1.772 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[2] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[5]           ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.029     ; 2.779      ;
; -1.772 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[2] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[6]           ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.029     ; 2.779      ;
; -1.772 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[2] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[7]           ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.029     ; 2.779      ;
; -1.772 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[2] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[8]           ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.026     ; 2.782      ;
; -1.772 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[2] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[9]           ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.026     ; 2.782      ;
; -1.772 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[2] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[18]          ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.026     ; 2.782      ;
+--------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'clock_generator_1|pll_2|altpll_component|pll|clk[1]'                                                                                                                                                                                                                                              ;
+--------+----------------------------------------------------------------------------+---------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                  ; To Node                                                                   ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------+---------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -1.791 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[0]                ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.065     ; 1.763      ;
; -1.791 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[1]                ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.065     ; 1.763      ;
; -1.791 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[0]                   ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.065     ; 1.763      ;
; -1.791 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[3]                   ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.065     ; 1.763      ;
; -1.665 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stop_warten    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.064     ; 1.638      ;
; -1.665 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stopbedingung  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.064     ; 1.638      ;
; -1.627 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[1]                   ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.051     ; 1.613      ;
; -1.627 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[2]                   ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.051     ; 1.613      ;
; -1.438 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.065     ; 1.410      ;
; -1.438 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~en                   ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.065     ; 1.410      ;
; -1.438 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.anfangszustand ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.065     ; 1.410      ;
; -1.438 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.startbedingung ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.065     ; 1.410      ;
; -1.438 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n          ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.065     ; 1.410      ;
; -1.438 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.taktende       ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.065     ; 1.410      ;
; -1.438 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten     ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.065     ; 1.410      ;
; -1.438 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten2    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.065     ; 1.410      ;
; -1.438 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack            ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.065     ; 1.410      ;
; -1.438 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SCLK                      ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.065     ; 1.410      ;
; -1.367 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[1]             ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.064     ; 1.340      ;
; -1.366 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[0]             ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.064     ; 1.339      ;
; -1.364 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.error          ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.064     ; 1.337      ;
; -1.282 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[2]             ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.062     ; 1.257      ;
; -1.282 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ende           ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.062     ; 1.257      ;
; -1.282 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[3]             ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.062     ; 1.257      ;
; 2.424  ; clock_generator:clock_generator_1|reset                                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[0]                ; CLOCK_27                                            ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -2.423     ; 4.448      ;
; 2.424  ; clock_generator:clock_generator_1|reset                                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[1]                ; CLOCK_27                                            ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -2.423     ; 4.448      ;
; 2.424  ; clock_generator:clock_generator_1|reset                                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[0]                   ; CLOCK_27                                            ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -2.423     ; 4.448      ;
; 2.424  ; clock_generator:clock_generator_1|reset                                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[3]                   ; CLOCK_27                                            ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -2.423     ; 4.448      ;
; 2.592  ; clock_generator:clock_generator_1|reset                                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[1]                   ; CLOCK_27                                            ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -2.409     ; 4.294      ;
; 2.592  ; clock_generator:clock_generator_1|reset                                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[2]                   ; CLOCK_27                                            ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -2.409     ; 4.294      ;
; 77.118 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[0]                 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 6.251      ;
; 77.399 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[1]                 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 5.970      ;
; 77.437 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[1]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; -0.014     ; 5.918      ;
; 77.567 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[0]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 5.802      ;
; 77.662 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[2]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; -0.014     ; 5.693      ;
; 77.675 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[3]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 5.694      ;
; 79.443 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[1]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; -0.001     ; 3.925      ;
; 79.454 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[0]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; -0.001     ; 3.914      ;
; 80.172 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.taktende        ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[1]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.014      ; 3.211      ;
; 80.172 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.taktende        ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[2]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.014      ; 3.211      ;
; 80.351 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.startbedingung  ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[1]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.014      ; 3.032      ;
; 80.351 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.startbedingung  ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[2]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.014      ; 3.032      ;
; 80.360 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[1]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; -0.014     ; 2.995      ;
; 80.512 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[1]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[1]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 2.857      ;
; 80.518 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[0]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 2.851      ;
; 80.578 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[0]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[1]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.014      ; 2.805      ;
; 80.629 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack             ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[1]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.014      ; 2.754      ;
; 80.629 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack             ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[2]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.014      ; 2.754      ;
; 80.877 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[0]                 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n          ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 2.492      ;
; 80.939 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[2]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[3]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; -0.014     ; 2.416      ;
; 81.019 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.taktende        ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[3]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 2.350      ;
; 81.171 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[2]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n          ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; -0.014     ; 2.184      ;
; 81.182 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack             ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n          ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 2.187      ;
; 81.198 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.startbedingung  ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[3]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 2.171      ;
; 81.268 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[2]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; -0.003     ; 2.098      ;
; 81.313 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.taktende        ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 2.056      ;
; 81.349 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.anfangszustand  ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 2.020      ;
; 81.357 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[3]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 2.012      ;
; 81.378 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[1]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[3]             ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.002      ; 1.993      ;
; 81.379 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[1]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[2]             ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.002      ; 1.992      ;
; 81.398 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[2]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ende           ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 1.971      ;
; 81.412 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[0]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[3]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 1.957      ;
; 81.435 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[3]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n          ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 1.934      ;
; 81.455 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[1]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[3]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; -0.014     ; 1.900      ;
; 81.456 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[1]                 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n          ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 1.913      ;
; 81.464 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[1]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n          ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; -0.014     ; 1.891      ;
; 81.465 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[3]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; -0.003     ; 1.901      ;
; 81.471 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[2]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; -0.014     ; 1.884      ;
; 81.476 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack             ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[3]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 1.893      ;
; 81.506 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[2]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.anfangszustand ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; -0.003     ; 1.860      ;
; 81.586 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stopbedingung   ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.anfangszustand ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; -0.001     ; 1.782      ;
; 81.587 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stopbedingung   ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[3]             ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.002      ; 1.784      ;
; 81.588 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stopbedingung   ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[2]             ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.002      ; 1.783      ;
; 81.610 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stopbedingung   ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ende           ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.002      ; 1.761      ;
; 81.636 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[3]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.anfangszustand ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; -0.003     ; 1.730      ;
; 81.679 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.taktende        ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 1.690      ;
; 81.679 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[0]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[3]             ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.002      ; 1.692      ;
; 81.680 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[0]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[2]             ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.002      ; 1.691      ;
; 81.698 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ende            ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; -0.003     ; 1.668      ;
; 81.722 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack             ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[0]                ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 1.647      ;
; 81.746 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[1]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[2]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 1.623      ;
; 81.747 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[0]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n          ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 1.622      ;
; 81.801 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[0]                 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stop_warten    ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.001      ; 1.569      ;
; 81.804 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[0]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[2]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.014      ; 1.579      ;
; 81.847 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[0]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[1]             ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 1.522      ;
; 81.854 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n           ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 1.515      ;
; 81.924 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten      ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SCLK                      ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 1.445      ;
; 82.018 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[0]                 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[0]                ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 1.351      ;
; 82.072 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[2]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[3]             ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 1.297      ;
; 82.077 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack             ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.error          ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.001      ; 1.293      ;
; 82.082 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack             ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stop_warten    ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.001      ; 1.288      ;
; 82.083 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.taktende        ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[0]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 1.286      ;
; 82.098 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[0]                 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[1]                ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 1.271      ;
; 82.108 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stop_warten     ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SCLK                      ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; -0.001     ; 1.260      ;
; 82.138 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack             ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SCLK                      ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 1.231      ;
; 82.162 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.anfangszustand  ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[0]                ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 1.207      ;
; 82.173 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.error           ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SCLK                      ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; -0.001     ; 1.195      ;
; 82.223 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.taktende        ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n          ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 1.146      ;
; 82.234 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten2     ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack            ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 1.135      ;
; 82.262 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.startbedingung  ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[0]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 1.107      ;
+--------+----------------------------------------------------------------------------+---------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr'                                                                                                                                                                                                                                ;
+-------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-----------------------------------------------------+--------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                 ; To Node                                                                       ; Launch Clock                                        ; Latch Clock                                            ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-----------------------------------------------------+--------------------------------------------------------+--------------+------------+------------+
; 1.558 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[17] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[17] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 2.074      ; 1.552      ;
; 1.615 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[14] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[14] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 2.076      ; 1.497      ;
; 1.633 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[6]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[6]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 2.075      ; 1.478      ;
; 1.655 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[8]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[8]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 2.077      ; 1.458      ;
; 1.656 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[15] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[15] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 2.079      ; 1.459      ;
; 1.658 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[9]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[9]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 2.076      ; 1.454      ;
; 1.661 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[12] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[12] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 2.080      ; 1.455      ;
; 1.665 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[11] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[11] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 2.080      ; 1.451      ;
; 1.671 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[22] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[22] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 2.074      ; 1.439      ;
; 1.677 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[7]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[7]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 2.074      ; 1.433      ;
; 1.680 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[13] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[13] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 2.076      ; 1.432      ;
; 1.682 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[20] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[20] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 2.074      ; 1.428      ;
; 1.688 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[18] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[18] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 2.074      ; 1.422      ;
; 1.693 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[16] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[16] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 2.076      ; 1.419      ;
; 1.697 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[19] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[19] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 2.074      ; 1.413      ;
; 1.749 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[3]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[3]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 2.081      ; 1.368      ;
; 1.782 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[2]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[2]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 2.077      ; 1.331      ;
; 1.890 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[21] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[21] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 2.081      ; 1.227      ;
; 1.893 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[4]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[4]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 2.077      ; 1.220      ;
; 1.918 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[5]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[5]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 2.077      ; 1.195      ;
; 1.924 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[1]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[1]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 2.077      ; 1.189      ;
; 1.928 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[10] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[10] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 2.079      ; 1.187      ;
; 2.148 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[0]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[0]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 2.082      ; 0.970      ;
; 2.177 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[23] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[23] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 2.078      ; 0.937      ;
+-------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-----------------------------------------------------+--------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql'                                                                                                                                                                                                                                ;
+-------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-----------------------------------------------------+--------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                 ; To Node                                                                       ; Launch Clock                                        ; Latch Clock                                            ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-----------------------------------------------------+--------------------------------------------------------+--------------+------------+------------+
; 1.567 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[8]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[8]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.907      ; 1.376      ;
; 1.571 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[23] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[23] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.905      ; 1.370      ;
; 1.617 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[21] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[21] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.902      ; 1.321      ;
; 1.677 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[2]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[2]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.903      ; 1.262      ;
; 1.700 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[15] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[15] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.906      ; 1.242      ;
; 1.700 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[7]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[7]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.906      ; 1.242      ;
; 1.825 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[22] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[22] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.902      ; 1.113      ;
; 1.829 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[20] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[20] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.902      ; 1.109      ;
; 1.833 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[11] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[11] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.902      ; 1.105      ;
; 1.836 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[10] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[10] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.902      ; 1.102      ;
; 1.961 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[13] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[13] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.902      ; 0.977      ;
; 1.962 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[3]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[3]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.903      ; 0.977      ;
; 1.964 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[14] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[14] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.902      ; 0.974      ;
; 1.964 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[12] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[12] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.902      ; 0.974      ;
; 1.965 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[17] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[17] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.902      ; 0.973      ;
; 1.965 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[0]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[0]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.903      ; 0.974      ;
; 1.970 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[19] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[19] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.902      ; 0.968      ;
; 1.970 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[9]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[9]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.902      ; 0.968      ;
; 1.970 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[1]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[1]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.902      ; 0.968      ;
; 1.974 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[6]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[6]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.902      ; 0.964      ;
; 1.978 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[4]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[4]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.903      ; 0.961      ;
; 2.010 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[18] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[18] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.902      ; 0.928      ;
; 2.017 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[5]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[5]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.903      ; 0.922      ;
; 2.158 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[16] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[16] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.903      ; 0.781      ;
+-------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-----------------------------------------------------+--------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'CLOCK_27'                                                                                                                                                             ;
+--------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                           ; To Node                                             ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 30.205 ; clock_generator:clock_generator_1|start_counter[13] ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.001     ; 6.867      ;
; 30.235 ; clock_generator:clock_generator_1|start_counter[15] ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.001     ; 6.837      ;
; 30.249 ; clock_generator:clock_generator_1|start_counter[12] ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.004     ; 6.820      ;
; 30.377 ; clock_generator:clock_generator_1|start_counter[14] ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.001     ; 6.695      ;
; 30.487 ; clock_generator:clock_generator_1|start_counter[16] ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.001     ; 6.585      ;
; 30.506 ; clock_generator:clock_generator_1|start_counter[7]  ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.004     ; 6.563      ;
; 30.657 ; clock_generator:clock_generator_1|start_counter[24] ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.001     ; 6.415      ;
; 30.657 ; clock_generator:clock_generator_1|start_counter[11] ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.004     ; 6.412      ;
; 30.668 ; clock_generator:clock_generator_1|start_counter[19] ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.001     ; 6.404      ;
; 30.694 ; clock_generator:clock_generator_1|start_counter[10] ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.004     ; 6.375      ;
; 30.720 ; clock_generator:clock_generator_1|start_counter[6]  ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.004     ; 6.349      ;
; 30.728 ; clock_generator:clock_generator_1|start_counter[22] ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.001     ; 6.344      ;
; 30.757 ; clock_generator:clock_generator_1|start_counter[21] ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.001     ; 6.315      ;
; 30.795 ; clock_generator:clock_generator_1|start_counter[8]  ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.004     ; 6.274      ;
; 30.800 ; clock_generator:clock_generator_1|start_counter[25] ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.001     ; 6.272      ;
; 30.807 ; clock_generator:clock_generator_1|start_counter[17] ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.001     ; 6.265      ;
; 30.862 ; clock_generator:clock_generator_1|start_counter[5]  ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.004     ; 6.207      ;
; 30.904 ; clock_generator:clock_generator_1|start_counter[20] ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.001     ; 6.168      ;
; 30.930 ; clock_generator:clock_generator_1|start_counter[0]  ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.004     ; 6.139      ;
; 30.943 ; clock_generator:clock_generator_1|start_counter[18] ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.001     ; 6.129      ;
; 30.964 ; clock_generator:clock_generator_1|start_counter[9]  ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.004     ; 6.105      ;
; 30.970 ; clock_generator:clock_generator_1|start_counter[2]  ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.004     ; 6.099      ;
; 30.994 ; clock_generator:clock_generator_1|start_counter[4]  ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.004     ; 6.075      ;
; 31.001 ; clock_generator:clock_generator_1|start_counter[3]  ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.004     ; 6.068      ;
; 31.039 ; clock_generator:clock_generator_1|start_counter[23] ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.001     ; 6.033      ;
; 31.279 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.004     ; 5.790      ;
; 32.724 ; clock_generator:clock_generator_1|start_counter[0]  ; clock_generator:clock_generator_1|start_counter[23] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 4.346      ;
; 32.837 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|start_counter[23] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 4.233      ;
; 32.881 ; clock_generator:clock_generator_1|start_counter[0]  ; clock_generator:clock_generator_1|start_counter[25] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 4.189      ;
; 32.910 ; clock_generator:clock_generator_1|start_counter[3]  ; clock_generator:clock_generator_1|start_counter[23] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 4.160      ;
; 32.953 ; clock_generator:clock_generator_1|start_counter[0]  ; clock_generator:clock_generator_1|start_counter[24] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 4.117      ;
; 32.994 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|start_counter[25] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 4.076      ;
; 33.012 ; clock_generator:clock_generator_1|start_counter[4]  ; clock_generator:clock_generator_1|start_counter[23] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 4.058      ;
; 33.058 ; clock_generator:clock_generator_1|start_counter[2]  ; clock_generator:clock_generator_1|start_counter[23] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 4.012      ;
; 33.066 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|start_counter[24] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 4.004      ;
; 33.067 ; clock_generator:clock_generator_1|start_counter[3]  ; clock_generator:clock_generator_1|start_counter[25] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 4.003      ;
; 33.093 ; clock_generator:clock_generator_1|start_counter[0]  ; clock_generator:clock_generator_1|start_counter[22] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 3.977      ;
; 33.139 ; clock_generator:clock_generator_1|start_counter[3]  ; clock_generator:clock_generator_1|start_counter[24] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 3.931      ;
; 33.169 ; clock_generator:clock_generator_1|start_counter[4]  ; clock_generator:clock_generator_1|start_counter[25] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 3.901      ;
; 33.174 ; clock_generator:clock_generator_1|start_counter[0]  ; clock_generator:clock_generator_1|start_counter[21] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 3.896      ;
; 33.206 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|start_counter[22] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 3.864      ;
; 33.215 ; clock_generator:clock_generator_1|start_counter[5]  ; clock_generator:clock_generator_1|start_counter[23] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 3.855      ;
; 33.215 ; clock_generator:clock_generator_1|start_counter[2]  ; clock_generator:clock_generator_1|start_counter[25] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 3.855      ;
; 33.241 ; clock_generator:clock_generator_1|start_counter[4]  ; clock_generator:clock_generator_1|start_counter[24] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 3.829      ;
; 33.245 ; clock_generator:clock_generator_1|start_counter[6]  ; clock_generator:clock_generator_1|start_counter[23] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 3.825      ;
; 33.279 ; clock_generator:clock_generator_1|start_counter[3]  ; clock_generator:clock_generator_1|start_counter[22] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 3.791      ;
; 33.287 ; clock_generator:clock_generator_1|start_counter[2]  ; clock_generator:clock_generator_1|start_counter[24] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 3.783      ;
; 33.287 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|start_counter[21] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 3.783      ;
; 33.322 ; clock_generator:clock_generator_1|start_counter[0]  ; clock_generator:clock_generator_1|start_counter[13] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 3.748      ;
; 33.337 ; clock_generator:clock_generator_1|start_counter[0]  ; clock_generator:clock_generator_1|start_counter[16] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 3.733      ;
; 33.360 ; clock_generator:clock_generator_1|start_counter[3]  ; clock_generator:clock_generator_1|start_counter[21] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 3.710      ;
; 33.367 ; clock_generator:clock_generator_1|start_counter[0]  ; clock_generator:clock_generator_1|start_counter[20] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 3.703      ;
; 33.372 ; clock_generator:clock_generator_1|start_counter[5]  ; clock_generator:clock_generator_1|start_counter[25] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 3.698      ;
; 33.381 ; clock_generator:clock_generator_1|start_counter[4]  ; clock_generator:clock_generator_1|start_counter[22] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 3.689      ;
; 33.384 ; clock_generator:clock_generator_1|start_counter[8]  ; clock_generator:clock_generator_1|start_counter[23] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 3.686      ;
; 33.396 ; clock_generator:clock_generator_1|start_counter[0]  ; clock_generator:clock_generator_1|start_counter[19] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 3.674      ;
; 33.402 ; clock_generator:clock_generator_1|start_counter[6]  ; clock_generator:clock_generator_1|start_counter[25] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 3.668      ;
; 33.411 ; clock_generator:clock_generator_1|start_counter[0]  ; clock_generator:clock_generator_1|start_counter[15] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 3.659      ;
; 33.427 ; clock_generator:clock_generator_1|start_counter[2]  ; clock_generator:clock_generator_1|start_counter[22] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 3.643      ;
; 33.435 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|start_counter[13] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 3.635      ;
; 33.444 ; clock_generator:clock_generator_1|start_counter[5]  ; clock_generator:clock_generator_1|start_counter[24] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 3.626      ;
; 33.450 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|start_counter[16] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 3.620      ;
; 33.453 ; clock_generator:clock_generator_1|start_counter[9]  ; clock_generator:clock_generator_1|start_counter[23] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 3.617      ;
; 33.461 ; clock_generator:clock_generator_1|start_counter[0]  ; clock_generator:clock_generator_1|start_counter[18] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 3.609      ;
; 33.462 ; clock_generator:clock_generator_1|start_counter[4]  ; clock_generator:clock_generator_1|start_counter[21] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 3.608      ;
; 33.468 ; clock_generator:clock_generator_1|start_counter[13] ; clock_generator:clock_generator_1|start_counter[7]  ; CLOCK_27     ; CLOCK_27    ; 37.037       ; 0.003      ; 3.608      ;
; 33.474 ; clock_generator:clock_generator_1|start_counter[6]  ; clock_generator:clock_generator_1|start_counter[24] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 3.596      ;
; 33.480 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|start_counter[20] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 3.590      ;
; 33.498 ; clock_generator:clock_generator_1|start_counter[15] ; clock_generator:clock_generator_1|start_counter[7]  ; CLOCK_27     ; CLOCK_27    ; 37.037       ; 0.003      ; 3.578      ;
; 33.508 ; clock_generator:clock_generator_1|start_counter[2]  ; clock_generator:clock_generator_1|start_counter[21] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 3.562      ;
; 33.508 ; clock_generator:clock_generator_1|start_counter[3]  ; clock_generator:clock_generator_1|start_counter[13] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 3.562      ;
; 33.509 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|start_counter[19] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 3.561      ;
; 33.512 ; clock_generator:clock_generator_1|start_counter[7]  ; clock_generator:clock_generator_1|start_counter[23] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 3.558      ;
; 33.512 ; clock_generator:clock_generator_1|start_counter[12] ; clock_generator:clock_generator_1|start_counter[7]  ; CLOCK_27     ; CLOCK_27    ; 37.037       ; 0.000      ; 3.561      ;
; 33.523 ; clock_generator:clock_generator_1|start_counter[3]  ; clock_generator:clock_generator_1|start_counter[16] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 3.547      ;
; 33.524 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|start_counter[15] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 3.546      ;
; 33.526 ; clock_generator:clock_generator_1|start_counter[13] ; clock_generator:clock_generator_1|start_counter[13] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; 0.000      ; 3.547      ;
; 33.527 ; clock_generator:clock_generator_1|start_counter[13] ; clock_generator:clock_generator_1|start_counter[21] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; 0.000      ; 3.546      ;
; 33.528 ; clock_generator:clock_generator_1|start_counter[13] ; clock_generator:clock_generator_1|start_counter[15] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; 0.000      ; 3.545      ;
; 33.530 ; clock_generator:clock_generator_1|start_counter[13] ; clock_generator:clock_generator_1|start_counter[23] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; 0.000      ; 3.543      ;
; 33.530 ; clock_generator:clock_generator_1|start_counter[13] ; clock_generator:clock_generator_1|start_counter[20] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; 0.000      ; 3.543      ;
; 33.532 ; clock_generator:clock_generator_1|start_counter[13] ; clock_generator:clock_generator_1|start_counter[16] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; 0.000      ; 3.541      ;
; 33.533 ; clock_generator:clock_generator_1|start_counter[10] ; clock_generator:clock_generator_1|start_counter[23] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 3.537      ;
; 33.534 ; clock_generator:clock_generator_1|start_counter[13] ; clock_generator:clock_generator_1|start_counter[24] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; 0.000      ; 3.539      ;
; 33.535 ; clock_generator:clock_generator_1|start_counter[0]  ; clock_generator:clock_generator_1|start_counter[17] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 3.535      ;
; 33.536 ; clock_generator:clock_generator_1|start_counter[13] ; clock_generator:clock_generator_1|start_counter[22] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; 0.000      ; 3.537      ;
; 33.538 ; clock_generator:clock_generator_1|start_counter[13] ; clock_generator:clock_generator_1|start_counter[14] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; 0.000      ; 3.535      ;
; 33.540 ; clock_generator:clock_generator_1|start_counter[13] ; clock_generator:clock_generator_1|start_counter[17] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; 0.000      ; 3.533      ;
; 33.541 ; clock_generator:clock_generator_1|start_counter[8]  ; clock_generator:clock_generator_1|start_counter[25] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 3.529      ;
; 33.544 ; clock_generator:clock_generator_1|start_counter[13] ; clock_generator:clock_generator_1|start_counter[25] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; 0.000      ; 3.529      ;
; 33.546 ; clock_generator:clock_generator_1|start_counter[13] ; clock_generator:clock_generator_1|start_counter[18] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; 0.000      ; 3.527      ;
; 33.547 ; clock_generator:clock_generator_1|start_counter[13] ; clock_generator:clock_generator_1|start_counter[19] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; 0.000      ; 3.526      ;
; 33.553 ; clock_generator:clock_generator_1|start_counter[3]  ; clock_generator:clock_generator_1|start_counter[20] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 3.517      ;
; 33.556 ; clock_generator:clock_generator_1|start_counter[15] ; clock_generator:clock_generator_1|start_counter[13] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; 0.000      ; 3.517      ;
; 33.557 ; clock_generator:clock_generator_1|start_counter[15] ; clock_generator:clock_generator_1|start_counter[21] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; 0.000      ; 3.516      ;
; 33.558 ; clock_generator:clock_generator_1|start_counter[15] ; clock_generator:clock_generator_1|start_counter[15] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; 0.000      ; 3.515      ;
; 33.560 ; clock_generator:clock_generator_1|start_counter[15] ; clock_generator:clock_generator_1|start_counter[23] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; 0.000      ; 3.513      ;
; 33.560 ; clock_generator:clock_generator_1|start_counter[15] ; clock_generator:clock_generator_1|start_counter[20] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; 0.000      ; 3.513      ;
; 33.562 ; clock_generator:clock_generator_1|start_counter[15] ; clock_generator:clock_generator_1|start_counter[16] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; 0.000      ; 3.511      ;
; 33.564 ; clock_generator:clock_generator_1|start_counter[15] ; clock_generator:clock_generator_1|start_counter[24] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; 0.000      ; 3.509      ;
+--------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Setup: 'clock_generator_1|pll_1|altpll_component|pll|clk[1]'                                                                                                                                                                                                                                               ;
+--------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                  ; To Node                                                                    ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; 96.859 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.006      ; 3.183      ;
; 96.909 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.006      ; 3.133      ;
; 97.006 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.006      ; 3.036      ;
; 97.132 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.006      ; 2.910      ;
; 97.255 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 2.781      ;
; 97.536 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.006      ; 2.506      ;
; 97.601 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 2.435      ;
; 97.651 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 2.385      ;
; 97.671 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.006      ; 2.371      ;
; 97.748 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 2.288      ;
; 97.770 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 2.266      ;
; 97.812 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.006      ; 2.230      ;
; 97.830 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 2.206      ;
; 97.862 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 2.174      ;
; 97.874 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 2.162      ;
; 97.876 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 2.160      ;
; 97.898 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.006      ; 2.144      ;
; 97.926 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 2.110      ;
; 97.928 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.006      ; 2.114      ;
; 98.000 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 2.036      ;
; 98.060 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.976      ;
; 98.071 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.965      ;
; 98.092 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.944      ;
; 98.131 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.905      ;
; 98.142 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.894      ;
; 98.163 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.873      ;
; 98.192 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.844      ;
; 98.202 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.834      ;
; 98.213 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.823      ;
; 98.234 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.802      ;
; 98.263 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.773      ;
; 98.273 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.763      ;
; 98.278 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.758      ;
; 98.278 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.758      ;
; 98.284 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.752      ;
; 98.305 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.731      ;
; 98.327 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.709      ;
; 98.334 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.702      ;
; 98.344 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.692      ;
; 98.376 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.660      ;
; 98.398 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.638      ;
; 98.405 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.631      ;
; 98.413 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.623      ;
; 98.440 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.596      ;
; 98.468 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.568      ;
; 98.469 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.567      ;
; 98.476 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.560      ;
; 98.511 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.525      ;
; 98.514 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.522      ;
; 98.539 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.497      ;
; 98.540 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.496      ;
; 98.553 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.483      ;
; 98.554 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.482      ;
; 98.574 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.462      ;
; 98.582 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.454      ;
; 98.582 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.454      ;
; 98.688 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.348      ;
; 98.829 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.207      ;
; 98.921 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.115      ;
; 98.924 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.112      ;
; 98.925 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.111      ;
; 98.926 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.110      ;
; 98.926 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.110      ;
; 98.965 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.071      ;
; 98.965 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.071      ;
; 98.968 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.068      ;
; 99.226 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.810      ;
+--------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr'                                                                                                                                                                                                                                  ;
+--------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-----------------------------------------------------+--------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                 ; To Node                                                                       ; Launch Clock                                        ; Latch Clock                                            ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-----------------------------------------------------+--------------------------------------------------------+--------------+------------+------------+
; -1.407 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[23] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[23] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 2.078      ; 0.937      ;
; -1.378 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[0]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[0]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 2.082      ; 0.970      ;
; -1.158 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[10] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[10] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 2.079      ; 1.187      ;
; -1.154 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[1]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[1]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 2.077      ; 1.189      ;
; -1.148 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[5]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[5]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 2.077      ; 1.195      ;
; -1.123 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[4]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[4]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 2.077      ; 1.220      ;
; -1.120 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[21] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[21] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 2.081      ; 1.227      ;
; -1.012 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[2]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[2]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 2.077      ; 1.331      ;
; -0.979 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[3]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[3]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 2.081      ; 1.368      ;
; -0.927 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[19] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[19] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 2.074      ; 1.413      ;
; -0.923 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[16] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[16] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 2.076      ; 1.419      ;
; -0.918 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[18] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[18] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 2.074      ; 1.422      ;
; -0.912 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[20] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[20] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 2.074      ; 1.428      ;
; -0.910 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[13] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[13] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 2.076      ; 1.432      ;
; -0.907 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[7]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[7]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 2.074      ; 1.433      ;
; -0.901 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[22] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[22] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 2.074      ; 1.439      ;
; -0.895 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[11] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[11] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 2.080      ; 1.451      ;
; -0.891 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[12] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[12] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 2.080      ; 1.455      ;
; -0.888 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[9]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[9]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 2.076      ; 1.454      ;
; -0.886 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[15] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[15] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 2.079      ; 1.459      ;
; -0.885 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[8]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[8]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 2.077      ; 1.458      ;
; -0.863 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[6]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[6]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 2.075      ; 1.478      ;
; -0.845 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[14] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[14] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 2.076      ; 1.497      ;
; -0.788 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[17] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[17] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 2.074      ; 1.552      ;
+--------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-----------------------------------------------------+--------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql'                                                                                                                                                                                                                                  ;
+--------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-----------------------------------------------------+--------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                 ; To Node                                                                       ; Launch Clock                                        ; Latch Clock                                            ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-----------------------------------------------------+--------------------------------------------------------+--------------+------------+------------+
; -1.388 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[16] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[16] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.903      ; 0.781      ;
; -1.247 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[5]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[5]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.903      ; 0.922      ;
; -1.240 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[18] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[18] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.902      ; 0.928      ;
; -1.208 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[4]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[4]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.903      ; 0.961      ;
; -1.204 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[6]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[6]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.902      ; 0.964      ;
; -1.200 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[19] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[19] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.902      ; 0.968      ;
; -1.200 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[9]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[9]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.902      ; 0.968      ;
; -1.200 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[1]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[1]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.902      ; 0.968      ;
; -1.195 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[17] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[17] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.902      ; 0.973      ;
; -1.195 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[0]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[0]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.903      ; 0.974      ;
; -1.194 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[14] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[14] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.902      ; 0.974      ;
; -1.194 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[12] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[12] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.902      ; 0.974      ;
; -1.192 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[3]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[3]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.903      ; 0.977      ;
; -1.191 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[13] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[13] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.902      ; 0.977      ;
; -1.066 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[10] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[10] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.902      ; 1.102      ;
; -1.063 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[11] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[11] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.902      ; 1.105      ;
; -1.059 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[20] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[20] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.902      ; 1.109      ;
; -1.055 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[22] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[22] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.902      ; 1.113      ;
; -0.930 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[15] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[15] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.906      ; 1.242      ;
; -0.930 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[7]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[7]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.906      ; 1.242      ;
; -0.907 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[2]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[2]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.903      ; 1.262      ;
; -0.847 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[21] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[21] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.902      ; 1.321      ;
; -0.801 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[23] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[23] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.905      ; 1.370      ;
; -0.797 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[8]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[8]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.907      ; 1.376      ;
+--------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-----------------------------------------------------+--------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'clock_generator_1|pll_1|altpll_component|pll|clk[0]'                                                                                                                                                                                                                                             ;
+--------+-------------------------------------------------------------------------+-------------------------------------------------------------------------+--------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                               ; To Node                                                                 ; Launch Clock                                           ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-------------------------------------------------------------------------+-------------------------------------------------------------------------+--------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -0.166 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr                  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr                  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.307      ; 0.657      ;
; -0.151 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql                  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql                  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.292      ; 0.657      ;
; 0.334  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr                  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr                  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; -0.500       ; 0.307      ; 0.657      ;
; 0.349  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql                  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql                  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; -0.500       ; 0.292      ; 0.657      ;
; 0.391  ; MMI:MMI_1|lcd_controller:lcd_controller_1|index[0]                      ; MMI:MMI_1|lcd_controller:lcd_controller_1|index[0]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|lcd_controller:lcd_controller_1|delay[0]                      ; MMI:MMI_1|lcd_controller:lcd_controller_1|delay[0]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|lcd_controller:lcd_controller_1|index[2]                      ; MMI:MMI_1|lcd_controller:lcd_controller_1|index[2]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|lcd_controller:lcd_controller_1|start                         ; MMI:MMI_1|lcd_controller:lcd_controller_1|start                         ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|lcd_controller:lcd_controller_1|counter[2]                    ; MMI:MMI_1|lcd_controller:lcd_controller_1|counter[2]                    ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|lcd_controller:lcd_controller_1|counter[3]                    ; MMI:MMI_1|lcd_controller:lcd_controller_1|counter[3]                    ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|lcd_controller:lcd_controller_1|counter[0]                    ; MMI:MMI_1|lcd_controller:lcd_controller_1|counter[0]                    ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|lcd_controller:lcd_controller_1|counter[1]                    ; MMI:MMI_1|lcd_controller:lcd_controller_1|counter[1]                    ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|filter[3]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|filter[3]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|filter[0]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|filter[0]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f13_db[4]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f13_db[4]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f13_db[6]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f13_db[6]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f13_db[7]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f13_db[7]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f13_db[0]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f13_db[0]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f13_db[5]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f13_db[5]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f13_db[3]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f13_db[3]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f12_db[2]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f12_db[2]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f12_db[4]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f12_db[4]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f12_db[5]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f12_db[5]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f12_db[7]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f12_db[7]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f12_db[6]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f12_db[6]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f12_db[3]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f12_db[3]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f14_db[4]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f14_db[4]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f14_db[6]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f14_db[6]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f14_db[7]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f14_db[7]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f14_db[0]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f14_db[0]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f14_db[5]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f14_db[5]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f14_db[3]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f14_db[3]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f1_db[0]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f1_db[0]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f1_db[5]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f1_db[5]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f1_db[6]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f1_db[6]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f1_db[7]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f1_db[7]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f1_db[3]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f1_db[3]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f2_db[4]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f2_db[4]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f2_db[5]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f2_db[5]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f2_db[7]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f2_db[7]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f2_db[0]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f2_db[0]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f2_db[6]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f2_db[6]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f2_db[3]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f2_db[3]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f3_db[4]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f3_db[4]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f3_db[5]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f3_db[5]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f3_db[6]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f3_db[6]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f3_db[7]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f3_db[7]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f3_db[2]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f3_db[2]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f3_db[3]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f3_db[3]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f4_db[1]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f4_db[1]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f4_db[2]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f4_db[2]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f4_db[4]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f4_db[4]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f4_db[5]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f4_db[5]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f4_db[6]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f4_db[6]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f4_db[7]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f4_db[7]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f4_db[0]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f4_db[0]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f4_db[3]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f4_db[3]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[1]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[1]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[2]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[2]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[4]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[4]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[5]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[5]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[6]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[6]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[0]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[0]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[7]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[7]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[3]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[3]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f10_db[1]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f10_db[1]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f10_db[2]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f10_db[2]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f10_db[4]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f10_db[4]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f10_db[6]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f10_db[6]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f10_db[7]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f10_db[7]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f10_db[0]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f10_db[0]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f10_db[5]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f10_db[5]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; MMI:MMI_1|mmi_controller:mmi_controller_1|f10_db[3]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f10_db[3]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_right[0]      ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_right[0]      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_right[7]      ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_right[7]      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_right[8]      ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_right[8]      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_right[9]      ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_right[9]      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_right[10]     ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_right[10]     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_right[11]     ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_right[11]     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_left[8]       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_left[8]       ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_left[9]       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_left[9]       ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_left[10]      ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_left[10]      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_left[11]      ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_left[11]      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_left[0]       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_left[0]       ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_left[7]       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_left[7]       ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|section[1] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|section[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|section[2] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|section[2] ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|counter[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|counter[0] ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|counter[1] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|counter[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|counter[2] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|counter[2] ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|counter[4] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|counter[4] ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|counter[5] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|counter[5] ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|counter[7] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|counter[7] ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|counter[6] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|counter[6] ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|section[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|section[0] ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|section[3] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|section[3] ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[16]     ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[16]     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[11]     ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[11]     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[10]     ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[10]     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[8]      ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[8]      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.657      ;
+--------+-------------------------------------------------------------------------+-------------------------------------------------------------------------+--------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'AUD_BCLK'                                                                                                                                                                                                                                                                                                 ;
+-------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                                                        ; To Node                                                                                          ; Launch Clock                                           ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------+-------------+--------------+------------+------------+
; 0.154 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[0]                     ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[1]           ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; AUD_BCLK    ; -0.500       ; 0.865      ; 0.785      ;
; 0.155 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[10]                    ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[11]          ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; AUD_BCLK    ; -0.500       ; 0.868      ; 0.789      ;
; 0.155 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[14]                    ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[15]          ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; AUD_BCLK    ; -0.500       ; 0.868      ; 0.789      ;
; 0.156 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[3]                     ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[4]           ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; AUD_BCLK    ; -0.500       ; 0.865      ; 0.787      ;
; 0.156 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[9]                     ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[10]          ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; AUD_BCLK    ; -0.500       ; 0.868      ; 0.790      ;
; 0.157 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[12]                    ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[13]          ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; AUD_BCLK    ; -0.500       ; 0.868      ; 0.791      ;
; 0.157 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[15]                    ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[16]          ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; AUD_BCLK    ; -0.500       ; 0.868      ; 0.791      ;
; 0.159 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[11]                    ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[12]          ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; AUD_BCLK    ; -0.500       ; 0.868      ; 0.793      ;
; 0.160 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[7]                     ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[8]           ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; AUD_BCLK    ; -0.500       ; 0.865      ; 0.791      ;
; 0.160 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[20]                    ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[21]          ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; AUD_BCLK    ; -0.500       ; 0.863      ; 0.789      ;
; 0.161 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[17]                    ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[18]          ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; AUD_BCLK    ; -0.500       ; 0.863      ; 0.790      ;
; 0.162 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[18]                    ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[19]          ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; AUD_BCLK    ; -0.500       ; 0.863      ; 0.791      ;
; 0.163 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[19]                    ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[20]          ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; AUD_BCLK    ; -0.500       ; 0.863      ; 0.792      ;
; 0.164 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[21]                    ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[22]          ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; AUD_BCLK    ; -0.500       ; 0.863      ; 0.793      ;
; 0.185 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[1]                     ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[2]           ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; AUD_BCLK    ; -0.500       ; 0.865      ; 0.816      ;
; 0.206 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[5]                      ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.592      ; 1.064      ;
; 0.210 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[4]                      ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.592      ; 1.068      ;
; 0.212 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[7]                      ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.592      ; 1.070      ;
; 0.213 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[3]                      ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.592      ; 1.071      ;
; 0.214 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[8]                      ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.592      ; 1.072      ;
; 0.214 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[23]                     ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.592      ; 1.072      ;
; 0.284 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[5]                     ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[6]           ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; AUD_BCLK    ; -0.500       ; 0.865      ; 0.915      ;
; 0.288 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[6]                     ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[7]           ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; AUD_BCLK    ; -0.500       ; 0.865      ; 0.919      ;
; 0.289 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[2]                     ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[3]           ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; AUD_BCLK    ; -0.500       ; 0.865      ; 0.920      ;
; 0.289 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[22]                    ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[23]          ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; AUD_BCLK    ; -0.500       ; 0.863      ; 0.918      ;
; 0.290 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[4]                     ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[5]           ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; AUD_BCLK    ; -0.500       ; 0.865      ; 0.921      ;
; 0.291 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[13]                    ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[14]          ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; AUD_BCLK    ; -0.500       ; 0.868      ; 0.925      ;
; 0.319 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[23]                    ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|dacdat                     ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; AUD_BCLK    ; -0.500       ; 0.712      ; 0.797      ;
; 0.333 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[8]                     ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[9]           ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; AUD_BCLK    ; -0.500       ; 0.690      ; 0.789      ;
; 0.333 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[17]                    ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[18]          ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; AUD_BCLK    ; -0.500       ; 0.690      ; 0.789      ;
; 0.334 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[7]                     ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[8]           ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; AUD_BCLK    ; -0.500       ; 0.690      ; 0.790      ;
; 0.334 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[22]                    ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[23]          ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; AUD_BCLK    ; -0.500       ; 0.690      ; 0.790      ;
; 0.335 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[18]                    ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[19]          ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; AUD_BCLK    ; -0.500       ; 0.690      ; 0.791      ;
; 0.335 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[20]                    ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[21]          ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; AUD_BCLK    ; -0.500       ; 0.690      ; 0.791      ;
; 0.336 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[19]                    ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[20]          ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; AUD_BCLK    ; -0.500       ; 0.690      ; 0.792      ;
; 0.336 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[16]                    ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[17]          ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; AUD_BCLK    ; -0.500       ; 0.867      ; 0.969      ;
; 0.339 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[16]                    ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[17]          ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; AUD_BCLK    ; -0.500       ; 0.683      ; 0.788      ;
; 0.340 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[4]                     ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[5]           ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; AUD_BCLK    ; -0.500       ; 0.684      ; 0.790      ;
; 0.340 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[10]                    ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[11]          ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; AUD_BCLK    ; -0.500       ; 0.683      ; 0.789      ;
; 0.340 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[21]                    ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[22]          ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; AUD_BCLK    ; -0.500       ; 0.684      ; 0.790      ;
; 0.341 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[0]                     ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[1]           ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; AUD_BCLK    ; -0.500       ; 0.684      ; 0.791      ;
; 0.341 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[14]                    ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[15]          ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; AUD_BCLK    ; -0.500       ; 0.683      ; 0.790      ;
; 0.342 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[2]                     ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[3]           ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; AUD_BCLK    ; -0.500       ; 0.684      ; 0.792      ;
; 0.342 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[3]                     ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[4]           ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; AUD_BCLK    ; -0.500       ; 0.684      ; 0.792      ;
; 0.342 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[6]                     ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[7]           ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; AUD_BCLK    ; -0.500       ; 0.684      ; 0.792      ;
; 0.342 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[13]                    ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[14]          ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; AUD_BCLK    ; -0.500       ; 0.683      ; 0.791      ;
; 0.343 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[5]                     ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[6]           ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; AUD_BCLK    ; -0.500       ; 0.684      ; 0.793      ;
; 0.343 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[11]                    ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[12]          ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; AUD_BCLK    ; -0.500       ; 0.683      ; 0.792      ;
; 0.343 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[15]                    ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[16]          ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; AUD_BCLK    ; -0.500       ; 0.683      ; 0.792      ;
; 0.344 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[12]                    ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[13]          ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; AUD_BCLK    ; -0.500       ; 0.683      ; 0.793      ;
; 0.391 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|enr                          ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|enr                          ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.657      ;
; 0.391 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|enl                          ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|enl                          ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.657      ;
; 0.391 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_left[4]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_left[4]  ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.657      ;
; 0.391 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_left[0]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_left[0]  ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.657      ;
; 0.391 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_left[3]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_left[3]  ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.657      ;
; 0.391 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.657      ;
; 0.391 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[2] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[2] ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.657      ;
; 0.391 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[3] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[3] ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.657      ;
; 0.391 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[1] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[1] ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.657      ;
; 0.391 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.657      ;
; 0.472 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[1]                     ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[2]           ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; AUD_BCLK    ; -0.500       ; 0.684      ; 0.922      ;
; 0.474 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[9]                     ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[10]          ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; AUD_BCLK    ; -0.500       ; 0.683      ; 0.923      ;
; 0.477 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[2]                      ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.592      ; 1.335      ;
; 0.488 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[14]                     ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.592      ; 1.346      ;
; 0.498 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[3]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dr[4]                        ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.574      ; 1.338      ;
; 0.521 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[2]           ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[3]           ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.787      ;
; 0.521 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[6]           ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[7]           ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.787      ;
; 0.522 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[22]          ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[23]          ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.788      ;
; 0.526 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[5]           ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[6]           ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.792      ;
; 0.543 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[15]                     ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.592      ; 1.401      ;
; 0.544 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[13]                     ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.592      ; 1.402      ;
; 0.560 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[4]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[4]             ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.826      ;
; 0.570 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[8]                     ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[9]           ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; AUD_BCLK    ; -0.500       ; 0.867      ; 1.203      ;
; 0.603 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[3]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dr[19]                       ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.552      ; 1.421      ;
; 0.624 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[4]              ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[13]                       ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.466      ; 1.356      ;
; 0.626 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[4]              ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[12]                       ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.466      ; 1.358      ;
; 0.626 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[4]              ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[9]                        ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.466      ; 1.358      ;
; 0.627 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[4]              ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[14]                       ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.466      ; 1.359      ;
; 0.627 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[4]              ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[10]                       ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.466      ; 1.359      ;
; 0.630 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[4]              ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[15]                       ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.466      ; 1.362      ;
; 0.631 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[4]              ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[11]                       ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.466      ; 1.363      ;
; 0.640 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[4]              ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[5]                        ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.562      ; 1.468      ;
; 0.640 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[4]              ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[4]                        ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.562      ; 1.468      ;
; 0.641 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[4]              ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[21]                       ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.562      ; 1.469      ;
; 0.654 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[7]           ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[8]           ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.920      ;
; 0.717 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[6]                      ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.592      ; 1.575      ;
; 0.717 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[19]                     ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.592      ; 1.575      ;
; 0.717 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[23]                    ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|dacdat                     ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; AUD_BCLK    ; -0.500       ; 0.887      ; 1.370      ;
; 0.719 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[10]                     ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.592      ; 1.577      ;
; 0.720 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[11]                     ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.592      ; 1.578      ;
; 0.722 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[12]                     ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.592      ; 1.580      ;
; 0.723 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[9]                      ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.592      ; 1.581      ;
; 0.736 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[20]                     ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.577      ; 1.579      ;
; 0.737 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[18]                     ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.577      ; 1.580      ;
; 0.738 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[0]                      ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.577      ; 1.581      ;
; 0.740 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[4]              ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[4]              ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.000      ; 1.006      ;
; 0.740 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[17]                     ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.577      ; 1.583      ;
; 0.743 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[4]              ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[3]                        ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.564      ; 1.573      ;
; 0.744 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[16]                     ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.577      ; 1.587      ;
; 0.745 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[21]                     ; AUD_BCLK                                               ; AUD_BCLK    ; 0.000        ; 0.577      ; 1.588      ;
+-------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------+-------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'CLOCK_27'                                                                                                                                                             ;
+-------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                           ; To Node                                             ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.391 ; clock_generator:clock_generator_1|start_counter[0]  ; clock_generator:clock_generator_1|start_counter[0]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 0.657      ;
; 1.188 ; clock_generator:clock_generator_1|start_counter[12] ; clock_generator:clock_generator_1|start_counter[12] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.454      ;
; 1.303 ; clock_generator:clock_generator_1|start_counter[25] ; clock_generator:clock_generator_1|start_counter[25] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.569      ;
; 1.326 ; clock_generator:clock_generator_1|start_counter[7]  ; clock_generator:clock_generator_1|start_counter[7]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.592      ;
; 1.510 ; clock_generator:clock_generator_1|start_counter[2]  ; clock_generator:clock_generator_1|start_counter[2]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.776      ;
; 1.538 ; clock_generator:clock_generator_1|start_counter[5]  ; clock_generator:clock_generator_1|start_counter[5]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.804      ;
; 1.543 ; clock_generator:clock_generator_1|start_counter[24] ; clock_generator:clock_generator_1|start_counter[24] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.809      ;
; 1.546 ; clock_generator:clock_generator_1|start_counter[20] ; clock_generator:clock_generator_1|start_counter[20] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.812      ;
; 1.577 ; clock_generator:clock_generator_1|start_counter[22] ; clock_generator:clock_generator_1|start_counter[22] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.843      ;
; 1.578 ; clock_generator:clock_generator_1|start_counter[10] ; clock_generator:clock_generator_1|start_counter[10] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.844      ;
; 1.580 ; clock_generator:clock_generator_1|start_counter[21] ; clock_generator:clock_generator_1|start_counter[21] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.846      ;
; 1.585 ; clock_generator:clock_generator_1|start_counter[6]  ; clock_generator:clock_generator_1|start_counter[6]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.851      ;
; 1.585 ; clock_generator:clock_generator_1|start_counter[8]  ; clock_generator:clock_generator_1|start_counter[8]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.851      ;
; 1.587 ; clock_generator:clock_generator_1|start_counter[9]  ; clock_generator:clock_generator_1|start_counter[9]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.853      ;
; 1.588 ; clock_generator:clock_generator_1|start_counter[17] ; clock_generator:clock_generator_1|start_counter[17] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.854      ;
; 1.589 ; clock_generator:clock_generator_1|start_counter[14] ; clock_generator:clock_generator_1|start_counter[14] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.855      ;
; 1.589 ; clock_generator:clock_generator_1|start_counter[19] ; clock_generator:clock_generator_1|start_counter[19] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.855      ;
; 1.614 ; clock_generator:clock_generator_1|start_counter[11] ; clock_generator:clock_generator_1|start_counter[11] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.880      ;
; 1.614 ; clock_generator:clock_generator_1|start_counter[18] ; clock_generator:clock_generator_1|start_counter[18] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.880      ;
; 1.769 ; clock_generator:clock_generator_1|start_counter[7]  ; clock_generator:clock_generator_1|start_counter[8]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.035      ;
; 1.805 ; clock_generator:clock_generator_1|start_counter[11] ; clock_generator:clock_generator_1|start_counter[12] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.071      ;
; 1.806 ; clock_generator:clock_generator_1|start_counter[16] ; clock_generator:clock_generator_1|start_counter[16] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.072      ;
; 1.837 ; clock_generator:clock_generator_1|start_counter[10] ; clock_generator:clock_generator_1|start_counter[12] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.103      ;
; 1.840 ; clock_generator:clock_generator_1|start_counter[7]  ; clock_generator:clock_generator_1|start_counter[9]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.106      ;
; 1.842 ; clock_generator:clock_generator_1|start_counter[4]  ; clock_generator:clock_generator_1|start_counter[4]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.108      ;
; 1.849 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|start_counter[1]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.115      ;
; 1.855 ; clock_generator:clock_generator_1|start_counter[15] ; clock_generator:clock_generator_1|start_counter[15] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.121      ;
; 1.858 ; clock_generator:clock_generator_1|start_counter[7]  ; clock_generator:clock_generator_1|start_counter[12] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.124      ;
; 1.905 ; clock_generator:clock_generator_1|start_counter[6]  ; clock_generator:clock_generator_1|start_counter[7]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.171      ;
; 1.911 ; clock_generator:clock_generator_1|start_counter[7]  ; clock_generator:clock_generator_1|start_counter[10] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.177      ;
; 1.913 ; clock_generator:clock_generator_1|start_counter[23] ; clock_generator:clock_generator_1|start_counter[23] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.179      ;
; 1.916 ; clock_generator:clock_generator_1|start_counter[3]  ; clock_generator:clock_generator_1|start_counter[3]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.182      ;
; 1.917 ; clock_generator:clock_generator_1|start_counter[9]  ; clock_generator:clock_generator_1|start_counter[12] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.183      ;
; 1.920 ; clock_generator:clock_generator_1|start_counter[16] ; clock_generator:clock_generator_1|start_counter[17] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.186      ;
; 1.927 ; clock_generator:clock_generator_1|start_counter[24] ; clock_generator:clock_generator_1|start_counter[25] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.193      ;
; 1.927 ; clock_generator:clock_generator_1|start_counter[5]  ; clock_generator:clock_generator_1|start_counter[6]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.193      ;
; 1.930 ; clock_generator:clock_generator_1|start_counter[19] ; clock_generator:clock_generator_1|start_counter[20] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.196      ;
; 1.930 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|start_counter[8]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.196      ;
; 1.930 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|start_counter[9]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.196      ;
; 1.933 ; clock_generator:clock_generator_1|start_counter[12] ; clock_generator:clock_generator_1|start_counter[14] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; -0.003     ; 2.196      ;
; 1.935 ; clock_generator:clock_generator_1|start_counter[5]  ; clock_generator:clock_generator_1|start_counter[7]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.201      ;
; 1.938 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|start_counter[10] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.204      ;
; 1.943 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|start_counter[5]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.209      ;
; 1.945 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|start_counter[6]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.211      ;
; 1.946 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|start_counter[11] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.212      ;
; 1.946 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|start_counter[4]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.212      ;
; 1.946 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|start_counter[3]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.212      ;
; 1.961 ; clock_generator:clock_generator_1|start_counter[10] ; clock_generator:clock_generator_1|start_counter[11] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.227      ;
; 1.968 ; clock_generator:clock_generator_1|start_counter[8]  ; clock_generator:clock_generator_1|start_counter[9]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.234      ;
; 1.970 ; clock_generator:clock_generator_1|start_counter[9]  ; clock_generator:clock_generator_1|start_counter[10] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.236      ;
; 1.973 ; clock_generator:clock_generator_1|start_counter[21] ; clock_generator:clock_generator_1|start_counter[22] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.239      ;
; 1.974 ; clock_generator:clock_generator_1|start_counter[17] ; clock_generator:clock_generator_1|start_counter[18] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.240      ;
; 1.982 ; clock_generator:clock_generator_1|start_counter[7]  ; clock_generator:clock_generator_1|start_counter[11] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.248      ;
; 1.986 ; clock_generator:clock_generator_1|start_counter[8]  ; clock_generator:clock_generator_1|start_counter[12] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.252      ;
; 1.994 ; clock_generator:clock_generator_1|start_counter[18] ; clock_generator:clock_generator_1|start_counter[19] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.260      ;
; 1.994 ; clock_generator:clock_generator_1|start_counter[16] ; clock_generator:clock_generator_1|start_counter[18] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.260      ;
; 1.999 ; clock_generator:clock_generator_1|start_counter[23] ; clock_generator:clock_generator_1|start_counter[24] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.265      ;
; 2.007 ; clock_generator:clock_generator_1|start_counter[2]  ; clock_generator:clock_generator_1|start_counter[5]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.273      ;
; 2.008 ; clock_generator:clock_generator_1|start_counter[13] ; clock_generator:clock_generator_1|start_counter[14] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.274      ;
; 2.023 ; clock_generator:clock_generator_1|start_counter[18] ; clock_generator:clock_generator_1|start_counter[20] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.289      ;
; 2.029 ; clock_generator:clock_generator_1|start_counter[22] ; clock_generator:clock_generator_1|start_counter[24] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.295      ;
; 2.036 ; clock_generator:clock_generator_1|start_counter[6]  ; clock_generator:clock_generator_1|start_counter[8]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.302      ;
; 2.039 ; clock_generator:clock_generator_1|start_counter[8]  ; clock_generator:clock_generator_1|start_counter[10] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.305      ;
; 2.039 ; clock_generator:clock_generator_1|start_counter[17] ; clock_generator:clock_generator_1|start_counter[19] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.305      ;
; 2.041 ; clock_generator:clock_generator_1|start_counter[9]  ; clock_generator:clock_generator_1|start_counter[11] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.307      ;
; 2.043 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|start_counter[2]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.309      ;
; 2.043 ; clock_generator:clock_generator_1|start_counter[15] ; clock_generator:clock_generator_1|start_counter[17] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.309      ;
; 2.053 ; clock_generator:clock_generator_1|start_counter[4]  ; clock_generator:clock_generator_1|start_counter[5]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.319      ;
; 2.055 ; clock_generator:clock_generator_1|start_counter[20] ; clock_generator:clock_generator_1|start_counter[21] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.321      ;
; 2.059 ; clock_generator:clock_generator_1|start_counter[16] ; clock_generator:clock_generator_1|start_counter[19] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.325      ;
; 2.066 ; clock_generator:clock_generator_1|start_counter[5]  ; clock_generator:clock_generator_1|start_counter[8]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.332      ;
; 2.068 ; clock_generator:clock_generator_1|start_counter[17] ; clock_generator:clock_generator_1|start_counter[20] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.334      ;
; 2.071 ; clock_generator:clock_generator_1|start_counter[23] ; clock_generator:clock_generator_1|start_counter[25] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.337      ;
; 2.083 ; clock_generator:clock_generator_1|start_counter[2]  ; clock_generator:clock_generator_1|start_counter[3]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.349      ;
; 2.084 ; clock_generator:clock_generator_1|start_counter[2]  ; clock_generator:clock_generator_1|start_counter[6]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.350      ;
; 2.088 ; clock_generator:clock_generator_1|start_counter[16] ; clock_generator:clock_generator_1|start_counter[20] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.354      ;
; 2.089 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|start_counter[12] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.355      ;
; 2.092 ; clock_generator:clock_generator_1|start_counter[2]  ; clock_generator:clock_generator_1|start_counter[7]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.358      ;
; 2.101 ; clock_generator:clock_generator_1|start_counter[22] ; clock_generator:clock_generator_1|start_counter[25] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.367      ;
; 2.107 ; clock_generator:clock_generator_1|start_counter[6]  ; clock_generator:clock_generator_1|start_counter[9]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.373      ;
; 2.109 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|start_counter[0]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.375      ;
; 2.110 ; clock_generator:clock_generator_1|start_counter[8]  ; clock_generator:clock_generator_1|start_counter[11] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.376      ;
; 2.111 ; clock_generator:clock_generator_1|start_counter[14] ; clock_generator:clock_generator_1|start_counter[17] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.377      ;
; 2.112 ; clock_generator:clock_generator_1|start_counter[2]  ; clock_generator:clock_generator_1|start_counter[4]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.378      ;
; 2.113 ; clock_generator:clock_generator_1|start_counter[21] ; clock_generator:clock_generator_1|start_counter[24] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.379      ;
; 2.116 ; clock_generator:clock_generator_1|start_counter[13] ; clock_generator:clock_generator_1|start_counter[13] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.382      ;
; 2.117 ; clock_generator:clock_generator_1|start_counter[15] ; clock_generator:clock_generator_1|start_counter[18] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.383      ;
; 2.123 ; clock_generator:clock_generator_1|start_counter[19] ; clock_generator:clock_generator_1|start_counter[21] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.389      ;
; 2.125 ; clock_generator:clock_generator_1|start_counter[6]  ; clock_generator:clock_generator_1|start_counter[12] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.391      ;
; 2.130 ; clock_generator:clock_generator_1|start_counter[4]  ; clock_generator:clock_generator_1|start_counter[6]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.396      ;
; 2.136 ; clock_generator:clock_generator_1|start_counter[20] ; clock_generator:clock_generator_1|start_counter[22] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.402      ;
; 2.137 ; clock_generator:clock_generator_1|start_counter[5]  ; clock_generator:clock_generator_1|start_counter[9]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.403      ;
; 2.138 ; clock_generator:clock_generator_1|start_counter[4]  ; clock_generator:clock_generator_1|start_counter[7]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.404      ;
; 2.143 ; clock_generator:clock_generator_1|start_counter[12] ; clock_generator:clock_generator_1|start_counter[17] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; -0.003     ; 2.406      ;
; 2.155 ; clock_generator:clock_generator_1|start_counter[3]  ; clock_generator:clock_generator_1|start_counter[5]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.421      ;
; 2.155 ; clock_generator:clock_generator_1|start_counter[5]  ; clock_generator:clock_generator_1|start_counter[12] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.421      ;
; 2.156 ; clock_generator:clock_generator_1|start_counter[0]  ; clock_generator:clock_generator_1|start_counter[2]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.422      ;
; 2.170 ; clock_generator:clock_generator_1|start_counter[23] ; clock_generator:clock_generator_1|start_counter[8]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.003      ; 2.439      ;
; 2.170 ; clock_generator:clock_generator_1|start_counter[23] ; clock_generator:clock_generator_1|start_counter[9]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.003      ; 2.439      ;
; 2.178 ; clock_generator:clock_generator_1|start_counter[6]  ; clock_generator:clock_generator_1|start_counter[10] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 2.444      ;
+-------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'clock_generator_1|pll_1|altpll_component|pll|clk[1]'                                                                                                                                                                                                                                               ;
+-------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                  ; To Node                                                                    ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; 0.391 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.657      ;
; 0.544 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.810      ;
; 0.802 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.068      ;
; 0.805 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.071      ;
; 0.805 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.071      ;
; 0.844 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.110      ;
; 0.844 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.110      ;
; 0.845 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.111      ;
; 0.846 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.112      ;
; 0.849 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.115      ;
; 0.850 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.116      ;
; 0.941 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.207      ;
; 1.082 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.348      ;
; 1.188 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.454      ;
; 1.188 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.454      ;
; 1.196 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.462      ;
; 1.216 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.482      ;
; 1.217 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.483      ;
; 1.230 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.496      ;
; 1.231 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.497      ;
; 1.256 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.522      ;
; 1.259 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.525      ;
; 1.294 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.560      ;
; 1.301 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.567      ;
; 1.302 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.568      ;
; 1.330 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.596      ;
; 1.357 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.623      ;
; 1.365 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.631      ;
; 1.372 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.638      ;
; 1.394 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.660      ;
; 1.426 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.692      ;
; 1.436 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.702      ;
; 1.443 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.709      ;
; 1.465 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.731      ;
; 1.486 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.752      ;
; 1.492 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.758      ;
; 1.497 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.763      ;
; 1.507 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.773      ;
; 1.528 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.794      ;
; 1.536 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.802      ;
; 1.557 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.823      ;
; 1.568 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.834      ;
; 1.578 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.844      ;
; 1.607 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.873      ;
; 1.621 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.887      ;
; 1.628 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.894      ;
; 1.639 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.905      ;
; 1.678 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.944      ;
; 1.699 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.965      ;
; 1.710 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.976      ;
; 1.747 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 2.013      ;
; 1.770 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 2.036      ;
; 1.842 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.006      ; 2.114      ;
; 1.844 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 2.110      ;
; 1.872 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.006      ; 2.144      ;
; 1.894 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 2.160      ;
; 1.900 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 2.166      ;
; 1.958 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.006      ; 2.230      ;
; 2.099 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.006      ; 2.371      ;
; 2.119 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 2.385      ;
; 2.169 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 2.435      ;
; 2.234 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.006      ; 2.506      ;
; 2.515 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 2.781      ;
; 2.638 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.006      ; 2.910      ;
; 2.764 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.006      ; 3.036      ;
; 2.861 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.006      ; 3.133      ;
; 2.911 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.006      ; 3.183      ;
+-------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Hold: 'clock_generator_1|pll_2|altpll_component|pll|clk[1]'                                                                                                                                                                                                                                              ;
+-------+----------------------------------------------------------------------------+---------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                  ; To Node                                                                   ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------------------------------+---------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; 0.391 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[1]                 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[1]                ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[2]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[2]             ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ende            ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ende           ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[0]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[0]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[2]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[2]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[1]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[1]             ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[0]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[0]             ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[3]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[3]             ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[3]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[3]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.657      ;
; 0.391 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.error           ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.error          ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.657      ;
; 0.535 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.startbedingung  ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n          ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.801      ;
; 0.557 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack             ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~en                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.823      ;
; 0.563 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack             ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[0]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.829      ;
; 0.669 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stop_warten     ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stopbedingung  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.935      ;
; 0.678 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n           ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SCLK                      ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.944      ;
; 0.686 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n           ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.taktende       ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.952      ;
; 0.690 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten      ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten2    ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.956      ;
; 0.738 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.anfangszustand  ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[1]                ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.004      ;
; 0.740 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.taktende        ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[2]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.014      ; 1.020      ;
; 0.743 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.anfangszustand  ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.startbedingung ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.009      ;
; 0.751 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[1]                 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stop_warten    ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.001      ; 1.018      ;
; 0.822 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stopbedingung   ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[1]             ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.088      ;
; 0.822 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stopbedingung   ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[0]             ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.088      ;
; 0.827 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten      ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~en                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.093      ;
; 0.829 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten2     ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~en                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.095      ;
; 0.831 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack             ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[1]                ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.097      ;
; 0.832 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[3]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ende           ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.098      ;
; 0.841 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.startbedingung  ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[0]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.107      ;
; 0.869 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten2     ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack            ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.135      ;
; 0.880 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.taktende        ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n          ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.146      ;
; 0.930 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.error           ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SCLK                      ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.001     ; 1.195      ;
; 0.941 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.anfangszustand  ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[0]                ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.207      ;
; 0.965 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack             ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SCLK                      ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.231      ;
; 0.995 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stop_warten     ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SCLK                      ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.001     ; 1.260      ;
; 1.005 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[0]                 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[1]                ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.271      ;
; 1.020 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.taktende        ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[0]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.286      ;
; 1.021 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack             ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stop_warten    ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.001      ; 1.288      ;
; 1.025 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.taktende        ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[3]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.291      ;
; 1.026 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack             ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.error          ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.001      ; 1.293      ;
; 1.031 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[2]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[3]             ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.297      ;
; 1.053 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[2]             ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.062     ; 1.257      ;
; 1.053 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ende           ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.062     ; 1.257      ;
; 1.053 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[3]             ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.062     ; 1.257      ;
; 1.085 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[0]                 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[0]                ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.351      ;
; 1.135 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.error          ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.064     ; 1.337      ;
; 1.137 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[0]             ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.064     ; 1.339      ;
; 1.138 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[1]             ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.064     ; 1.340      ;
; 1.179 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten      ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SCLK                      ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.445      ;
; 1.209 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.065     ; 1.410      ;
; 1.209 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~en                   ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.065     ; 1.410      ;
; 1.209 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.anfangszustand ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.065     ; 1.410      ;
; 1.209 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.startbedingung ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.065     ; 1.410      ;
; 1.209 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n          ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.065     ; 1.410      ;
; 1.209 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.taktende       ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.065     ; 1.410      ;
; 1.209 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten     ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.065     ; 1.410      ;
; 1.209 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten2    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.065     ; 1.410      ;
; 1.209 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack            ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.065     ; 1.410      ;
; 1.209 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SCLK                      ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.065     ; 1.410      ;
; 1.249 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n           ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.515      ;
; 1.256 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[0]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[1]             ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.522      ;
; 1.299 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[0]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[2]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.014      ; 1.579      ;
; 1.302 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[0]                 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stop_warten    ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.001      ; 1.569      ;
; 1.356 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[0]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n          ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.622      ;
; 1.357 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[1]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[2]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.623      ;
; 1.381 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack             ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[0]                ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.647      ;
; 1.398 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[1]                   ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.051     ; 1.613      ;
; 1.398 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[2]                   ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.051     ; 1.613      ;
; 1.405 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ende            ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.003     ; 1.668      ;
; 1.423 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[0]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[2]             ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.002      ; 1.691      ;
; 1.424 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[0]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[3]             ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.002      ; 1.692      ;
; 1.424 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.taktende        ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.690      ;
; 1.436 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stop_warten    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.064     ; 1.638      ;
; 1.436 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stopbedingung  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.064     ; 1.638      ;
; 1.467 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[3]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.anfangszustand ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.003     ; 1.730      ;
; 1.493 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stopbedingung   ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ende           ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.002      ; 1.761      ;
; 1.515 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stopbedingung   ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[2]             ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.002      ; 1.783      ;
; 1.516 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stopbedingung   ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[3]             ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.002      ; 1.784      ;
; 1.517 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stopbedingung   ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.anfangszustand ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.001     ; 1.782      ;
; 1.562 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[0]                ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.065     ; 1.763      ;
; 1.562 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[1]                ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.065     ; 1.763      ;
; 1.562 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[0]                   ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.065     ; 1.763      ;
; 1.562 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[3]                   ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.065     ; 1.763      ;
; 1.567 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[3]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.003     ; 1.830      ;
; 1.597 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[2]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.anfangszustand ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.003     ; 1.860      ;
; 1.627 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack             ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[3]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.893      ;
; 1.632 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[2]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.014     ; 1.884      ;
; 1.639 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[1]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n          ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.014     ; 1.891      ;
; 1.647 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[1]                 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n          ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.913      ;
; 1.648 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[1]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[3]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.014     ; 1.900      ;
; 1.668 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[3]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n          ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.934      ;
; 1.691 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[0]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[3]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.957      ;
; 1.705 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[2]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ende           ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.971      ;
; 1.724 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[1]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[2]             ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.002      ; 1.992      ;
; 1.725 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[1]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[3]             ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.002      ; 1.993      ;
; 1.746 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[3]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 2.012      ;
; 1.754 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.anfangszustand  ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 2.020      ;
; 1.771 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[2]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.003     ; 2.034      ;
; 1.790 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.taktende        ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 2.056      ;
; 1.905 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.startbedingung  ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[3]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 2.171      ;
; 1.921 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack             ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n          ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 2.187      ;
+-------+----------------------------------------------------------------------------+---------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Recovery: 'clock_generator_1|pll_2|altpll_component|pll|clk[1]'                                                                                                                                                                ;
+-------+-----------------------------------------+---------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                               ; To Node                                                                   ; Launch Clock ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------+---------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
; 2.904 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[1]             ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -2.422     ; 3.969      ;
; 2.904 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stop_warten    ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -2.422     ; 3.969      ;
; 2.904 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stopbedingung  ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -2.422     ; 3.969      ;
; 2.904 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[0]             ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -2.422     ; 3.969      ;
; 2.904 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.error          ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -2.422     ; 3.969      ;
; 2.912 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[2]             ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -2.420     ; 3.963      ;
; 2.912 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ende           ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -2.420     ; 3.963      ;
; 2.912 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[3]             ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -2.420     ; 3.963      ;
; 2.913 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -2.423     ; 3.959      ;
; 2.913 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~en                   ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -2.423     ; 3.959      ;
; 2.913 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.anfangszustand ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -2.423     ; 3.959      ;
; 2.913 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.startbedingung ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -2.423     ; 3.959      ;
; 2.913 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n          ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -2.423     ; 3.959      ;
; 2.913 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.taktende       ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -2.423     ; 3.959      ;
; 2.913 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten     ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -2.423     ; 3.959      ;
; 2.913 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten2    ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -2.423     ; 3.959      ;
; 2.913 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack            ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -2.423     ; 3.959      ;
; 2.913 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SCLK                      ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -2.423     ; 3.959      ;
+-------+-----------------------------------------+---------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Removal: 'clock_generator_1|pll_2|altpll_component|pll|clk[1]'                                                                                                                                                                 ;
+-------+-----------------------------------------+---------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                               ; To Node                                                                   ; Launch Clock ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------+---------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
; 6.117 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; -0.001       ; -2.423     ; 3.959      ;
; 6.117 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~en                   ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; -0.001       ; -2.423     ; 3.959      ;
; 6.117 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.anfangszustand ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; -0.001       ; -2.423     ; 3.959      ;
; 6.117 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.startbedingung ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; -0.001       ; -2.423     ; 3.959      ;
; 6.117 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n          ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; -0.001       ; -2.423     ; 3.959      ;
; 6.117 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.taktende       ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; -0.001       ; -2.423     ; 3.959      ;
; 6.117 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten     ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; -0.001       ; -2.423     ; 3.959      ;
; 6.117 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten2    ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; -0.001       ; -2.423     ; 3.959      ;
; 6.117 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack            ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; -0.001       ; -2.423     ; 3.959      ;
; 6.117 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SCLK                      ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; -0.001       ; -2.423     ; 3.959      ;
; 6.118 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[2]             ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; -0.001       ; -2.420     ; 3.963      ;
; 6.118 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ende           ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; -0.001       ; -2.420     ; 3.963      ;
; 6.118 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[3]             ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; -0.001       ; -2.420     ; 3.963      ;
; 6.126 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[1]             ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; -0.001       ; -2.422     ; 3.969      ;
; 6.126 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stop_warten    ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; -0.001       ; -2.422     ; 3.969      ;
; 6.126 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stopbedingung  ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; -0.001       ; -2.422     ; 3.969      ;
; 6.126 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[0]             ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; -0.001       ; -2.422     ; 3.969      ;
; 6.126 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.error          ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; -0.001       ; -2.422     ; 3.969      ;
+-------+-----------------------------------------+---------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'AUD_BCLK'                                                                                                                               ;
+--------+--------------+----------------+------------------+----------+------------+--------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                               ;
+--------+--------------+----------------+------------------+----------+------------+--------------------------------------------------------------------------------------+
; -1.222 ; 1.000        ; 2.222          ; Port Rate        ; AUD_BCLK ; Rise       ; AUD_BCLK                                                                             ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[0]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[0]  ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[1]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[1]  ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[2]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[2]  ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[3]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[3]  ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[4]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[4]  ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[0] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[0] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[2] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[2] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[3] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[3] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[4] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[4] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[0]          ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[0]          ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[10]         ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[10]         ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[11]         ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[11]         ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[12]         ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[12]         ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[13]         ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[13]         ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[14]         ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[14]         ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[15]         ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[15]         ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[16]         ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[16]         ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[17]         ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[17]         ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[18]         ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[18]         ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[19]         ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[19]         ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[1]          ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[1]          ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[20]         ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[20]         ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[21]         ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[21]         ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[22]         ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[22]         ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[23]         ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[23]         ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[2]          ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[2]          ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[3]          ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[3]          ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[4]          ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[4]          ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[5]          ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[5]          ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[6]          ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[6]          ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[7]          ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[7]          ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[8]          ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[8]          ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[9]          ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[9]          ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[0]            ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[0]            ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[10]           ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[10]           ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[11]           ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[11]           ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[12]           ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[12]           ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[13]           ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[13]           ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[14]           ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[14]           ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[15]           ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[15]           ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[16]           ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[16]           ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[17]           ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[17]           ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[18]           ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[18]           ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[19]           ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[19]           ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[1]            ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[1]            ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[20]           ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[20]           ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[21]           ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[21]           ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[22]           ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[22]           ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[23]           ;
+--------+--------------+----------------+------------------+----------+------------+--------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql'                                                                                                                        ;
+--------+--------------+----------------+------------------+--------------------------------------------------------+------------+-------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                  ; Clock Edge ; Target                                                                        ;
+--------+--------------+----------------+------------------+--------------------------------------------------------+------------+-------------------------------------------------------------------------------+
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[0]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[0]  ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[10] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[10] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[11] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[11] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[12] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[12] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[13] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[13] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[14] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[14] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[15] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[15] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[16] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[16] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[17] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[17] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[18] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[18] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[19] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[19] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[1]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[1]  ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[20] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[20] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[21] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[21] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[22] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[22] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[23] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[23] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[2]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[2]  ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[3]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[3]  ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[4]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[4]  ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[5]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[5]  ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[6]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[6]  ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[7]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[7]  ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[8]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[8]  ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[9]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[9]  ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[0]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[0]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[10]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[10]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[11]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[11]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[12]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[12]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[13]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[13]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[14]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[14]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[15]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[15]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[16]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[16]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[17]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[17]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[18]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[18]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[19]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[19]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[1]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[1]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[20]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[20]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[21]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[21]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[22]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[22]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[23]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[23]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[2]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[2]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[3]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[3]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[4]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[4]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[5]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[5]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[6]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[6]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[7]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[7]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[8]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[8]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[9]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[9]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|filter_unit_1|enql|regout                                        ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|filter_unit_1|enql|regout                                        ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|filter_unit_1|enql~clkctrl|inclk[0]                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|filter_unit_1|enql~clkctrl|inclk[0]                              ;
+--------+--------------+----------------+------------------+--------------------------------------------------------+------------+-------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr'                                                                                                                        ;
+--------+--------------+----------------+------------------+--------------------------------------------------------+------------+-------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                  ; Clock Edge ; Target                                                                        ;
+--------+--------------+----------------+------------------+--------------------------------------------------------+------------+-------------------------------------------------------------------------------+
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[0]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[0]  ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[10] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[10] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[11] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[11] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[12] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[12] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[13] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[13] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[14] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[14] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[15] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[15] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[16] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[16] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[17] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[17] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[18] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[18] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[19] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[19] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[1]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[1]  ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[20] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[20] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[21] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[21] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[22] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[22] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[23] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[23] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[2]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[2]  ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[3]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[3]  ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[4]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[4]  ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[5]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[5]  ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[6]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[6]  ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[7]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[7]  ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[8]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[8]  ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[9]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[9]  ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[0]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[0]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[10]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[10]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[11]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[11]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[12]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[12]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[13]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[13]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[14]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[14]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[15]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[15]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[16]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[16]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[17]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[17]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[18]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[18]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[19]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[19]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[1]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[1]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[20]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[20]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[21]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[21]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[22]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[22]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[23]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[23]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[2]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[2]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[3]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[3]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[4]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[4]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[5]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[5]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[6]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[6]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[7]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[7]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[8]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[8]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[9]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[9]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|filter_unit_1|enqr|regout                                        ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|filter_unit_1|enqr|regout                                        ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|filter_unit_1|enqr~clkctrl|inclk[0]                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|filter_unit_1|enqr~clkctrl|inclk[0]                              ;
+--------+--------------+----------------+------------------+--------------------------------------------------------+------------+-------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'clock_generator_1|pll_1|altpll_component|pll|clk[0]'                                                                                                                                                                ;
+-------+--------------+----------------+------------------+-----------------------------------------------------+------------+------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                               ; Clock Edge ; Target                                                                                                                 ;
+-------+--------------+----------------+------------------+-----------------------------------------------------+------------+------------------------------------------------------------------------------------------------------------------------+
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_a[54]              ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_a[54]              ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_a[54]~_Duplicate_1 ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_a[54]~_Duplicate_1 ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_a[54]~_Duplicate_2 ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_a[54]~_Duplicate_2 ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_a[55]              ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_a[55]              ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_a[55]~_Duplicate_1 ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_a[55]~_Duplicate_1 ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_a[55]~_Duplicate_2 ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_a[55]~_Duplicate_2 ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_a[56]              ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_a[56]              ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_a[56]~_Duplicate_1 ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_a[56]~_Duplicate_1 ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_a[56]~_Duplicate_2 ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_a[56]~_Duplicate_2 ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[18]              ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[18]              ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[18]~_Duplicate_1 ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[18]~_Duplicate_1 ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[18]~_Duplicate_2 ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[18]~_Duplicate_2 ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[18]~_Duplicate_3 ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[18]~_Duplicate_3 ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[19]              ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[19]              ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[19]~_Duplicate_1 ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[19]~_Duplicate_1 ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[19]~_Duplicate_2 ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[19]~_Duplicate_2 ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[19]~_Duplicate_3 ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[19]~_Duplicate_3 ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[20]              ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[20]              ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[20]~_Duplicate_1 ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[20]~_Duplicate_1 ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[20]~_Duplicate_2 ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[20]~_Duplicate_2 ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[20]~_Duplicate_3 ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[20]~_Duplicate_3 ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[21]              ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[21]              ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[21]~_Duplicate_1 ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[21]~_Duplicate_1 ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[21]~_Duplicate_2 ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[21]~_Duplicate_2 ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[21]~_Duplicate_3 ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[21]~_Duplicate_3 ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[22]              ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[22]              ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[22]~_Duplicate_1 ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[22]~_Duplicate_1 ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[22]~_Duplicate_2 ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[22]~_Duplicate_2 ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[22]~_Duplicate_3 ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[22]~_Duplicate_3 ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[23]              ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[23]              ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[23]~_Duplicate_1 ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[23]~_Duplicate_1 ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[23]~_Duplicate_2 ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[23]~_Duplicate_2 ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[23]~_Duplicate_3 ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[23]~_Duplicate_3 ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[24]              ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[24]              ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[24]~_Duplicate_1 ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[24]~_Duplicate_1 ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[24]~_Duplicate_2 ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[24]~_Duplicate_2 ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[24]~_Duplicate_3 ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[24]~_Duplicate_3 ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[25]              ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[25]              ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[25]~_Duplicate_1 ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[25]~_Duplicate_1 ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[25]~_Duplicate_2 ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[25]~_Duplicate_2 ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[25]~_Duplicate_3 ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[25]~_Duplicate_3 ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[26]              ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[26]              ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[26]~_Duplicate_1 ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[26]~_Duplicate_1 ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[26]~_Duplicate_2 ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[26]~_Duplicate_2 ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[26]~_Duplicate_3 ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[26]~_Duplicate_3 ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[27]              ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[27]              ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[27]~_Duplicate_1 ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[27]~_Duplicate_1 ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[27]~_Duplicate_2 ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[27]~_Duplicate_2 ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[27]~_Duplicate_3 ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[27]~_Duplicate_3 ;
; 8.077 ; 10.000       ; 1.923          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[28]              ;
; 8.077 ; 10.000       ; 1.923          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[28]              ;
+-------+--------------+----------------+------------------+-----------------------------------------------------+------------+------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'CLOCK_50'                                                                                                ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------------------+
; 10.000 ; 10.000       ; 0.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; CLOCK_50|combout                                      ;
; 10.000 ; 10.000       ; 0.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; CLOCK_50|combout                                      ;
; 10.000 ; 10.000       ; 0.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0]   ;
; 10.000 ; 10.000       ; 0.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0]   ;
; 10.000 ; 10.000       ; 0.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[1]   ;
; 10.000 ; 10.000       ; 0.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[1]   ;
; 10.000 ; 10.000       ; 0.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|inclk[0] ;
; 10.000 ; 10.000       ; 0.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|inclk[0] ;
; 17.620 ; 20.000       ; 2.380          ; Port Rate        ; CLOCK_50 ; Rise       ; CLOCK_50                                              ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'CLOCK_27'                                                                                                ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------------------+
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|reset               ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[0]    ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[10]   ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[11]   ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[12]   ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[13]   ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[14]   ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[15]   ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[16]   ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[17]   ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[18]   ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[19]   ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[1]    ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[20]   ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[21]   ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[22]   ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[23]   ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[24]   ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[25]   ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[2]    ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[3]    ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[4]    ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[5]    ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[6]    ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[7]    ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[8]    ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[9]    ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|reset               ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[0]    ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[10]   ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[11]   ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[12]   ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[13]   ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[14]   ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[15]   ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[16]   ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[17]   ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[18]   ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[19]   ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[1]    ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[20]   ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[21]   ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[22]   ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[23]   ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[24]   ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[25]   ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[2]    ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[3]    ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[4]    ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[5]    ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[6]    ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[7]    ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[8]    ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[9]    ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; CLOCK_27|combout                                      ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; CLOCK_27~clkctrl|inclk[0]                             ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; CLOCK_27~clkctrl|outclk                               ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|pll_2|altpll_component|pll|clk[1]   ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|pll_2|altpll_component|pll|inclk[0] ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|reset|clk                           ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[0]|clk                ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[10]|clk               ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[11]|clk               ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[12]|clk               ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[13]|clk               ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[14]|clk               ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[15]|clk               ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[16]|clk               ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[17]|clk               ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[18]|clk               ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[19]|clk               ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[1]|clk                ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[20]|clk               ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[21]|clk               ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[22]|clk               ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[23]|clk               ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[24]|clk               ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[25]|clk               ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[2]|clk                ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[3]|clk                ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[4]|clk                ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[5]|clk                ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[6]|clk                ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[7]|clk                ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[8]|clk                ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[9]|clk                ;
; 18.519 ; 18.519       ; 0.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; CLOCK_27|combout                                      ;
; 18.519 ; 18.519       ; 0.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; CLOCK_27~clkctrl|inclk[0]                             ;
; 18.519 ; 18.519       ; 0.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; CLOCK_27~clkctrl|outclk                               ;
; 18.519 ; 18.519       ; 0.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator_1|pll_2|altpll_component|pll|clk[1]   ;
; 18.519 ; 18.519       ; 0.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator_1|pll_2|altpll_component|pll|inclk[0] ;
; 18.519 ; 18.519       ; 0.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator_1|reset|clk                           ;
; 18.519 ; 18.519       ; 0.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[0]|clk                ;
; 18.519 ; 18.519       ; 0.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[10]|clk               ;
; 18.519 ; 18.519       ; 0.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[11]|clk               ;
; 18.519 ; 18.519       ; 0.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[12]|clk               ;
; 18.519 ; 18.519       ; 0.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[13]|clk               ;
; 18.519 ; 18.519       ; 0.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[14]|clk               ;
; 18.519 ; 18.519       ; 0.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[15]|clk               ;
; 18.519 ; 18.519       ; 0.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[16]|clk               ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'clock_generator_1|pll_2|altpll_component|pll|clk[1]'                                                                                                                    ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                               ; Clock Edge ; Target                                                                    ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------+
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[0]             ;
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[1]             ;
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[2]             ;
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[3]             ;
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[0]                   ;
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[1]                   ;
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[2]                   ;
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[3]                   ;
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SCLK                      ;
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~en                   ;
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ;
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[0]                ;
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[1]                ;
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack            ;
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten     ;
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten2    ;
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.anfangszustand ;
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n          ;
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ende           ;
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.error          ;
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.startbedingung ;
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stop_warten    ;
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stopbedingung  ;
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.taktende       ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[0]             ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[1]             ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[2]             ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[3]             ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[0]                   ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[1]                   ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[2]                   ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[3]                   ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SCLK                      ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~en                   ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[0]                ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[1]                ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack            ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten     ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten2    ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.anfangszustand ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n          ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ende           ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.error          ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.startbedingung ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stop_warten    ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stopbedingung  ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.taktende       ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|Befehls_NR[0]|clk                               ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|Befehls_NR[1]|clk                               ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|Befehls_NR[2]|clk                               ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|Befehls_NR[3]|clk                               ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|Byte[0]|clk                                     ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|Byte[1]|clk                                     ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|Byte[2]|clk                                     ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|Byte[3]|clk                                     ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|SCLK|clk                                        ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|SDIN~en|clk                                     ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|SDIN~reg0|clk                                   ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|Sektion[0]|clk                                  ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|Sektion[1]|clk                                  ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|reg_fstate.ack_warten2|clk                      ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|reg_fstate.ack_warten|clk                       ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|reg_fstate.ack|clk                              ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|reg_fstate.anfangszustand|clk                   ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|reg_fstate.bit_n|clk                            ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|reg_fstate.ende|clk                             ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|reg_fstate.error|clk                            ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|reg_fstate.startbedingung|clk                   ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|reg_fstate.stop_warten|clk                      ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|reg_fstate.stopbedingung|clk                    ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|reg_fstate.taktende|clk                         ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|pll_2|altpll_component|_clk1~clkctrl|inclk[0]           ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|pll_2|altpll_component|_clk1~clkctrl|outclk             ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|Befehls_NR[0]|clk                               ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|Befehls_NR[1]|clk                               ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|Befehls_NR[2]|clk                               ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|Befehls_NR[3]|clk                               ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|Byte[0]|clk                                     ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|Byte[1]|clk                                     ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|Byte[2]|clk                                     ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|Byte[3]|clk                                     ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|SCLK|clk                                        ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|SDIN~en|clk                                     ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|SDIN~reg0|clk                                   ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|Sektion[0]|clk                                  ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|Sektion[1]|clk                                  ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|reg_fstate.ack_warten2|clk                      ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|reg_fstate.ack_warten|clk                       ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|reg_fstate.ack|clk                              ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|reg_fstate.anfangszustand|clk                   ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|reg_fstate.bit_n|clk                            ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|reg_fstate.ende|clk                             ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|reg_fstate.error|clk                            ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|reg_fstate.startbedingung|clk                   ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|reg_fstate.stop_warten|clk                      ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|reg_fstate.stopbedingung|clk                    ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|reg_fstate.taktende|clk                         ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|pll_2|altpll_component|_clk1~clkctrl|inclk[0]           ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|pll_2|altpll_component|_clk1~clkctrl|outclk             ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Model Minimum Pulse Width: 'clock_generator_1|pll_1|altpll_component|pll|clk[1]'                                                                                                                     ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+----------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                               ; Clock Edge ; Target                                                                     ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+----------------------------------------------------------------------------+
; 49.000 ; 50.000       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ;
; 49.000 ; 50.000       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ;
; 49.000 ; 50.000       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ;
; 49.000 ; 50.000       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ;
; 49.000 ; 50.000       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ;
; 49.000 ; 50.000       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ;
; 49.000 ; 50.000       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ;
; 49.000 ; 50.000       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ;
; 49.000 ; 50.000       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ;
; 49.000 ; 50.000       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ;
; 49.000 ; 50.000       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ;
; 49.000 ; 50.000       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ;
; 49.000 ; 50.000       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ;
; 49.000 ; 50.000       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ;
; 49.000 ; 50.000       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ;
; 49.000 ; 50.000       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ;
; 49.000 ; 50.000       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ;
; 49.000 ; 50.000       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ;
; 49.000 ; 50.000       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ;
; 49.000 ; 50.000       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ;
; 50.000 ; 50.000       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|clock_divider_1|c400[0]|clk                              ;
; 50.000 ; 50.000       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|clock_divider_1|c400[0]|clk                              ;
; 50.000 ; 50.000       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|clock_divider_1|c400[1]|clk                              ;
; 50.000 ; 50.000       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|clock_divider_1|c400[1]|clk                              ;
; 50.000 ; 50.000       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|clock_divider_1|c400[2]|clk                              ;
; 50.000 ; 50.000       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|clock_divider_1|c400[2]|clk                              ;
; 50.000 ; 50.000       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|clock_divider_1|c400[3]|clk                              ;
; 50.000 ; 50.000       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|clock_divider_1|c400[3]|clk                              ;
; 50.000 ; 50.000       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|clock_divider_1|c400[4]|clk                              ;
; 50.000 ; 50.000       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|clock_divider_1|c400[4]|clk                              ;
; 50.000 ; 50.000       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|clock_divider_1|c400[5]|clk                              ;
; 50.000 ; 50.000       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|clock_divider_1|c400[5]|clk                              ;
; 50.000 ; 50.000       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|clock_divider_1|c400[6]|clk                              ;
; 50.000 ; 50.000       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|clock_divider_1|c400[6]|clk                              ;
; 50.000 ; 50.000       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|clock_divider_1|c400[7]|clk                              ;
; 50.000 ; 50.000       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|clock_divider_1|c400[7]|clk                              ;
; 50.000 ; 50.000       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|clock_divider_1|c400[8]|clk                              ;
; 50.000 ; 50.000       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|clock_divider_1|c400[8]|clk                              ;
; 50.000 ; 50.000       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|clock_divider_1|clk_400kHz|clk                           ;
; 50.000 ; 50.000       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|clock_divider_1|clk_400kHz|clk                           ;
; 50.000 ; 50.000       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|pll_1|altpll_component|_clk1~clkctrl|inclk[0]            ;
; 50.000 ; 50.000       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|pll_1|altpll_component|_clk1~clkctrl|inclk[0]            ;
; 50.000 ; 50.000       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|pll_1|altpll_component|_clk1~clkctrl|outclk              ;
; 50.000 ; 50.000       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|pll_1|altpll_component|_clk1~clkctrl|outclk              ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+----------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                   ;
+-------------+------------+--------+--------+------------+-----------------------------------------------------+
; Data Port   ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
+-------------+------------+--------+--------+------------+-----------------------------------------------------+
; AUD_ADCDAT  ; AUD_BCLK   ; 4.249  ; 4.249  ; Rise       ; AUD_BCLK                                            ;
; AUD_ADCLRCK ; AUD_BCLK   ; 5.330  ; 5.330  ; Rise       ; AUD_BCLK                                            ;
; AUD_DACLRCK ; AUD_BCLK   ; 5.137  ; 5.137  ; Fall       ; AUD_BCLK                                            ;
; SW[*]       ; CLOCK_27   ; 4.062  ; 4.062  ; Rise       ; CLOCK_27                                            ;
;  SW[17]     ; CLOCK_27   ; 4.062  ; 4.062  ; Rise       ; CLOCK_27                                            ;
; KEY[*]      ; CLOCK_50   ; 10.815 ; 10.815 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  KEY[0]     ; CLOCK_50   ; 10.815 ; 10.815 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  KEY[1]     ; CLOCK_50   ; 10.486 ; 10.486 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  KEY[2]     ; CLOCK_50   ; 8.165  ; 8.165  ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  KEY[3]     ; CLOCK_50   ; 8.449  ; 8.449  ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; SW[*]       ; CLOCK_50   ; 6.119  ; 6.119  ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  SW[2]      ; CLOCK_50   ; 3.688  ; 3.688  ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  SW[3]      ; CLOCK_50   ; 6.119  ; 6.119  ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; SW[*]       ; CLOCK_50   ; 3.638  ; 3.638  ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  SW[1]      ; CLOCK_50   ; 3.638  ; 3.638  ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; I2C_SDAT    ; CLOCK_27   ; 8.026  ; 8.026  ; Rise       ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ;
+-------------+------------+--------+--------+------------+-----------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                    ;
+-------------+------------+--------+--------+------------+-----------------------------------------------------+
; Data Port   ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
+-------------+------------+--------+--------+------------+-----------------------------------------------------+
; AUD_ADCDAT  ; AUD_BCLK   ; -2.899 ; -2.899 ; Rise       ; AUD_BCLK                                            ;
; AUD_ADCLRCK ; AUD_BCLK   ; -3.438 ; -3.438 ; Rise       ; AUD_BCLK                                            ;
; AUD_DACLRCK ; AUD_BCLK   ; -2.994 ; -2.994 ; Fall       ; AUD_BCLK                                            ;
; SW[*]       ; CLOCK_27   ; -3.540 ; -3.540 ; Rise       ; CLOCK_27                                            ;
;  SW[17]     ; CLOCK_27   ; -3.540 ; -3.540 ; Rise       ; CLOCK_27                                            ;
; KEY[*]      ; CLOCK_50   ; -5.563 ; -5.563 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  KEY[0]     ; CLOCK_50   ; -6.869 ; -6.869 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  KEY[1]     ; CLOCK_50   ; -6.156 ; -6.156 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  KEY[2]     ; CLOCK_50   ; -5.563 ; -5.563 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  KEY[3]     ; CLOCK_50   ; -6.371 ; -6.371 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; SW[*]       ; CLOCK_50   ; -3.031 ; -3.031 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  SW[2]      ; CLOCK_50   ; -3.110 ; -3.110 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  SW[3]      ; CLOCK_50   ; -3.031 ; -3.031 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; SW[*]       ; CLOCK_50   ; -1.729 ; -1.729 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  SW[1]      ; CLOCK_50   ; -1.729 ; -1.729 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; I2C_SDAT    ; CLOCK_27   ; -6.898 ; -6.898 ; Rise       ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ;
+-------------+------------+--------+--------+------------+-----------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                        ;
+--------------+------------+-------+-------+------------+-----------------------------------------------------+
; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
+--------------+------------+-------+-------+------------+-----------------------------------------------------+
; AUD_DACDAT   ; AUD_BCLK   ; 7.930 ; 7.930 ; Fall       ; AUD_BCLK                                            ;
; LCD_DATA[*]  ; CLOCK_50   ; 7.681 ; 7.681 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[0] ; CLOCK_50   ; 6.767 ; 6.767 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[1] ; CLOCK_50   ; 7.457 ; 7.457 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[2] ; CLOCK_50   ; 5.693 ; 5.693 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[3] ; CLOCK_50   ; 7.335 ; 7.335 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[4] ; CLOCK_50   ; 5.843 ; 5.843 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[5] ; CLOCK_50   ; 7.681 ; 7.681 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[6] ; CLOCK_50   ; 5.666 ; 5.666 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[7] ; CLOCK_50   ; 5.981 ; 5.981 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; LCD_EN       ; CLOCK_50   ; 6.409 ; 6.409 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; LCD_RS       ; CLOCK_50   ; 5.639 ; 5.639 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; HEX0[*]      ; CLOCK_50   ; 4.281 ; 4.281 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX0[2]     ; CLOCK_50   ; 4.281 ; 4.281 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX0[3]     ; CLOCK_50   ; 4.047 ; 4.047 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX0[4]     ; CLOCK_50   ; 4.072 ; 4.072 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX0[5]     ; CLOCK_50   ; 4.035 ; 4.035 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX0[6]     ; CLOCK_50   ; 4.045 ; 4.045 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; HEX1[*]      ; CLOCK_50   ; 3.993 ; 3.993 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX1[1]     ; CLOCK_50   ; 3.993 ; 3.993 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX1[2]     ; CLOCK_50   ; 3.650 ; 3.650 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX1[3]     ; CLOCK_50   ; 3.690 ; 3.690 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX1[4]     ; CLOCK_50   ; 3.670 ; 3.670 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX1[6]     ; CLOCK_50   ; 3.961 ; 3.961 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; HEX2[*]      ; CLOCK_50   ; 5.008 ; 5.008 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX2[0]     ; CLOCK_50   ; 5.008 ; 5.008 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX2[1]     ; CLOCK_50   ; 4.948 ; 4.948 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX2[2]     ; CLOCK_50   ; 4.759 ; 4.759 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX2[3]     ; CLOCK_50   ; 4.958 ; 4.958 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX2[4]     ; CLOCK_50   ; 4.724 ; 4.724 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX2[5]     ; CLOCK_50   ; 4.740 ; 4.740 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX2[6]     ; CLOCK_50   ; 4.578 ; 4.578 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; HEX3[*]      ; CLOCK_50   ; 5.261 ; 5.261 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX3[0]     ; CLOCK_50   ; 4.957 ; 4.957 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX3[1]     ; CLOCK_50   ; 4.772 ; 4.772 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX3[2]     ; CLOCK_50   ; 4.745 ; 4.745 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX3[3]     ; CLOCK_50   ; 5.261 ; 5.261 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX3[4]     ; CLOCK_50   ; 4.740 ; 4.740 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX3[5]     ; CLOCK_50   ; 4.638 ; 4.638 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX3[6]     ; CLOCK_50   ; 4.699 ; 4.699 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; HEX4[*]      ; CLOCK_50   ; 5.238 ; 5.238 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX4[6]     ; CLOCK_50   ; 5.238 ; 5.238 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; HEX6[*]      ; CLOCK_50   ; 8.301 ; 8.301 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX6[0]     ; CLOCK_50   ; 6.113 ; 6.113 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX6[1]     ; CLOCK_50   ; 6.187 ; 6.187 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX6[2]     ; CLOCK_50   ; 6.634 ; 6.634 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX6[3]     ; CLOCK_50   ; 7.719 ; 7.719 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX6[4]     ; CLOCK_50   ; 6.507 ; 6.507 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX6[5]     ; CLOCK_50   ; 8.301 ; 8.301 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX6[6]     ; CLOCK_50   ; 6.169 ; 6.169 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; HEX7[*]      ; CLOCK_50   ; 7.768 ; 7.768 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX7[0]     ; CLOCK_50   ; 7.768 ; 7.768 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX7[1]     ; CLOCK_50   ; 6.385 ; 6.385 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX7[2]     ; CLOCK_50   ; 6.355 ; 6.355 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX7[3]     ; CLOCK_50   ; 7.738 ; 7.738 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX7[4]     ; CLOCK_50   ; 7.738 ; 7.738 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX7[5]     ; CLOCK_50   ; 7.758 ; 7.758 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; AUD_XCK      ; CLOCK_27   ; 2.917 ;       ; Rise       ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ;
; I2C_SCLK     ; CLOCK_27   ; 6.103 ; 6.103 ; Rise       ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ;
; I2C_SDAT     ; CLOCK_27   ; 6.296 ; 6.296 ; Rise       ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ;
; AUD_XCK      ; CLOCK_27   ;       ; 2.917 ; Fall       ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ;
+--------------+------------+-------+-------+------------+-----------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                ;
+--------------+------------+-------+-------+------------+-----------------------------------------------------+
; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
+--------------+------------+-------+-------+------------+-----------------------------------------------------+
; AUD_DACDAT   ; AUD_BCLK   ; 7.930 ; 7.930 ; Fall       ; AUD_BCLK                                            ;
; LCD_DATA[*]  ; CLOCK_50   ; 5.666 ; 5.666 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[0] ; CLOCK_50   ; 6.767 ; 6.767 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[1] ; CLOCK_50   ; 7.457 ; 7.457 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[2] ; CLOCK_50   ; 5.693 ; 5.693 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[3] ; CLOCK_50   ; 7.335 ; 7.335 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[4] ; CLOCK_50   ; 5.843 ; 5.843 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[5] ; CLOCK_50   ; 7.681 ; 7.681 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[6] ; CLOCK_50   ; 5.666 ; 5.666 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[7] ; CLOCK_50   ; 5.981 ; 5.981 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; LCD_EN       ; CLOCK_50   ; 6.409 ; 6.409 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; LCD_RS       ; CLOCK_50   ; 5.639 ; 5.639 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; HEX0[*]      ; CLOCK_50   ; 4.035 ; 4.035 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX0[2]     ; CLOCK_50   ; 4.281 ; 4.281 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX0[3]     ; CLOCK_50   ; 4.047 ; 4.047 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX0[4]     ; CLOCK_50   ; 4.072 ; 4.072 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX0[5]     ; CLOCK_50   ; 4.035 ; 4.035 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX0[6]     ; CLOCK_50   ; 4.045 ; 4.045 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; HEX1[*]      ; CLOCK_50   ; 3.650 ; 3.650 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX1[1]     ; CLOCK_50   ; 3.993 ; 3.993 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX1[2]     ; CLOCK_50   ; 3.650 ; 3.650 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX1[3]     ; CLOCK_50   ; 3.690 ; 3.690 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX1[4]     ; CLOCK_50   ; 3.670 ; 3.670 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX1[6]     ; CLOCK_50   ; 3.961 ; 3.961 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; HEX2[*]      ; CLOCK_50   ; 4.578 ; 4.578 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX2[0]     ; CLOCK_50   ; 5.008 ; 5.008 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX2[1]     ; CLOCK_50   ; 4.948 ; 4.948 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX2[2]     ; CLOCK_50   ; 4.759 ; 4.759 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX2[3]     ; CLOCK_50   ; 4.958 ; 4.958 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX2[4]     ; CLOCK_50   ; 4.724 ; 4.724 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX2[5]     ; CLOCK_50   ; 4.740 ; 4.740 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX2[6]     ; CLOCK_50   ; 4.578 ; 4.578 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; HEX3[*]      ; CLOCK_50   ; 4.638 ; 4.638 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX3[0]     ; CLOCK_50   ; 4.957 ; 4.957 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX3[1]     ; CLOCK_50   ; 4.772 ; 4.772 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX3[2]     ; CLOCK_50   ; 4.745 ; 4.745 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX3[3]     ; CLOCK_50   ; 5.261 ; 5.261 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX3[4]     ; CLOCK_50   ; 4.740 ; 4.740 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX3[5]     ; CLOCK_50   ; 4.638 ; 4.638 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX3[6]     ; CLOCK_50   ; 4.699 ; 4.699 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; HEX4[*]      ; CLOCK_50   ; 5.238 ; 5.238 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX4[6]     ; CLOCK_50   ; 5.238 ; 5.238 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; HEX6[*]      ; CLOCK_50   ; 6.113 ; 6.113 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX6[0]     ; CLOCK_50   ; 6.113 ; 6.113 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX6[1]     ; CLOCK_50   ; 6.187 ; 6.187 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX6[2]     ; CLOCK_50   ; 6.634 ; 6.634 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX6[3]     ; CLOCK_50   ; 7.719 ; 7.719 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX6[4]     ; CLOCK_50   ; 6.507 ; 6.507 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX6[5]     ; CLOCK_50   ; 8.301 ; 8.301 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX6[6]     ; CLOCK_50   ; 6.169 ; 6.169 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; HEX7[*]      ; CLOCK_50   ; 6.355 ; 6.355 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX7[0]     ; CLOCK_50   ; 7.768 ; 7.768 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX7[1]     ; CLOCK_50   ; 6.385 ; 6.385 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX7[2]     ; CLOCK_50   ; 6.355 ; 6.355 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX7[3]     ; CLOCK_50   ; 7.738 ; 7.738 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX7[4]     ; CLOCK_50   ; 7.738 ; 7.738 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX7[5]     ; CLOCK_50   ; 7.758 ; 7.758 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; AUD_XCK      ; CLOCK_27   ; 2.917 ;       ; Rise       ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ;
; I2C_SCLK     ; CLOCK_27   ; 6.103 ; 6.103 ; Rise       ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ;
; I2C_SDAT     ; CLOCK_27   ; 6.296 ; 6.296 ; Rise       ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ;
; AUD_XCK      ; CLOCK_27   ;       ; 2.917 ; Fall       ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ;
+--------------+------------+-------+-------+------------+-----------------------------------------------------+


+----------------------------------------------------+
; Propagation Delay                                  ;
+------------+-------------+----+-------+-------+----+
; Input Port ; Output Port ; RR ; RF    ; FR    ; FF ;
+------------+-------------+----+-------+-------+----+
; SW[0]      ; AUD_DACDAT  ;    ; 7.501 ; 7.501 ;    ;
+------------+-------------+----+-------+-------+----+


+----------------------------------------------------+
; Minimum Propagation Delay                          ;
+------------+-------------+----+-------+-------+----+
; Input Port ; Output Port ; RR ; RF    ; FR    ; FF ;
+------------+-------------+----+-------+-------+----+
; SW[0]      ; AUD_DACDAT  ;    ; 7.501 ; 7.501 ;    ;
+------------+-------------+----+-------+-------+----+


+----------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                      ;
+-----------+------------+-------+------+------------+-----------------------------------------------------+
; Data Port ; Clock Port ; Rise  ; Fall ; Clock Edge ; Clock Reference                                     ;
+-----------+------------+-------+------+------------+-----------------------------------------------------+
; I2C_SDAT  ; CLOCK_27   ; 6.205 ;      ; Rise       ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ;
+-----------+------------+-------+------+------------+-----------------------------------------------------+


+----------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                              ;
+-----------+------------+-------+------+------------+-----------------------------------------------------+
; Data Port ; Clock Port ; Rise  ; Fall ; Clock Edge ; Clock Reference                                     ;
+-----------+------------+-------+------+------------+-----------------------------------------------------+
; I2C_SDAT  ; CLOCK_27   ; 6.205 ;      ; Rise       ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ;
+-----------+------------+-------+------+------------+-----------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                              ;
+-----------+------------+-----------+-----------+------------+-----------------------------------------------------+
; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                     ;
+-----------+------------+-----------+-----------+------------+-----------------------------------------------------+
; I2C_SDAT  ; CLOCK_27   ; 6.205     ;           ; Rise       ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ;
+-----------+------------+-----------+-----------+------------+-----------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                      ;
+-----------+------------+-----------+-----------+------------+-----------------------------------------------------+
; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                     ;
+-----------+------------+-----------+-----------+------------+-----------------------------------------------------+
; I2C_SDAT  ; CLOCK_27   ; 6.205     ;           ; Rise       ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ;
+-----------+------------+-----------+-----------+------------+-----------------------------------------------------+


+---------------------------------------------------------------------------------+
; Fast Model Setup Summary                                                        ;
+--------------------------------------------------------+--------+---------------+
; Clock                                                  ; Slack  ; End Point TNS ;
+--------------------------------------------------------+--------+---------------+
; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; -2.966 ; -606.223      ;
; clock_generator_1|pll_2|altpll_component|pll|clk[1]    ; -0.934 ; -18.945       ;
; AUD_BCLK                                               ; -0.428 ; -31.065       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.665  ; 0.000         ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.674  ; 0.000         ;
; CLOCK_27                                               ; 33.762 ; 0.000         ;
; clock_generator_1|pll_1|altpll_component|pll|clk[1]    ; 98.561 ; 0.000         ;
+--------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------+
; Fast Model Hold Summary                                                         ;
+--------------------------------------------------------+--------+---------------+
; Clock                                                  ; Slack  ; End Point TNS ;
+--------------------------------------------------------+--------+---------------+
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; -1.082 ; -22.735       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; -1.080 ; -21.545       ;
; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; 0.013  ; 0.000         ;
; AUD_BCLK                                               ; 0.085  ; 0.000         ;
; CLOCK_27                                               ; 0.215  ; 0.000         ;
; clock_generator_1|pll_1|altpll_component|pll|clk[1]    ; 0.215  ; 0.000         ;
; clock_generator_1|pll_2|altpll_component|pll|clk[1]    ; 0.215  ; 0.000         ;
+--------------------------------------------------------+--------+---------------+


+-----------------------------------------------------------------------------+
; Fast Model Recovery Summary                                                 ;
+-----------------------------------------------------+-------+---------------+
; Clock                                               ; Slack ; End Point TNS ;
+-----------------------------------------------------+-------+---------------+
; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 5.604 ; 0.000         ;
+-----------------------------------------------------+-------+---------------+


+-----------------------------------------------------------------------------+
; Fast Model Removal Summary                                                  ;
+-----------------------------------------------------+-------+---------------+
; Clock                                               ; Slack ; End Point TNS ;
+-----------------------------------------------------+-------+---------------+
; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 3.531 ; 0.000         ;
+-----------------------------------------------------+-------+---------------+


+---------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width Summary                                          ;
+--------------------------------------------------------+--------+---------------+
; Clock                                                  ; Slack  ; End Point TNS ;
+--------------------------------------------------------+--------+---------------+
; AUD_BCLK                                               ; -1.222 ; -142.222      ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; -0.500 ; -24.000       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; -0.500 ; -24.000       ;
; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; 7.981  ; 0.000         ;
; CLOCK_50                                               ; 10.000 ; 0.000         ;
; CLOCK_27                                               ; 17.518 ; 0.000         ;
; clock_generator_1|pll_2|altpll_component|pll|clk[1]    ; 40.666 ; 0.000         ;
; clock_generator_1|pll_1|altpll_component|pll|clk[1]    ; 49.000 ; 0.000         ;
+--------------------------------------------------------+--------+---------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'clock_generator_1|pll_1|altpll_component|pll|clk[0]'                                                                                                                                                    ;
+--------+-----------------------------------------+-----------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                               ; To Node                                                   ; Launch Clock ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------+-----------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
; -2.966 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f12_db[1]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.583     ; 1.416      ;
; -2.966 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f12_db[2]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.583     ; 1.416      ;
; -2.966 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f12_db[4]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.583     ; 1.416      ;
; -2.966 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f12_db[5]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.583     ; 1.416      ;
; -2.966 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f12_db[7]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.583     ; 1.416      ;
; -2.966 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f12_db[0]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.583     ; 1.416      ;
; -2.966 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f12_db[6]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.583     ; 1.416      ;
; -2.966 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f12_db[3]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.583     ; 1.416      ;
; -2.956 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f6_db[0]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.589     ; 1.400      ;
; -2.956 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f6_db[4]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.589     ; 1.400      ;
; -2.956 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f6_db[5]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.589     ; 1.400      ;
; -2.956 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f6_db[6]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.589     ; 1.400      ;
; -2.956 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f6_db[7]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.589     ; 1.400      ;
; -2.956 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f6_db[1]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.589     ; 1.400      ;
; -2.956 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f6_db[3]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.589     ; 1.400      ;
; -2.914 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[1]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.579     ; 1.368      ;
; -2.914 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[2]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.579     ; 1.368      ;
; -2.914 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[4]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.579     ; 1.368      ;
; -2.914 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[5]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.579     ; 1.368      ;
; -2.914 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[6]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.579     ; 1.368      ;
; -2.914 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[0]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.579     ; 1.368      ;
; -2.914 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[7]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.579     ; 1.368      ;
; -2.914 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[3]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.579     ; 1.368      ;
; -2.907 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f9_db[0]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.580     ; 1.360      ;
; -2.907 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f9_db[1]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.580     ; 1.360      ;
; -2.907 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f9_db[4]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.580     ; 1.360      ;
; -2.907 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f9_db[5]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.580     ; 1.360      ;
; -2.907 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f9_db[6]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.580     ; 1.360      ;
; -2.907 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f9_db[7]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.580     ; 1.360      ;
; -2.907 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f9_db[2]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.580     ; 1.360      ;
; -2.907 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f9_db[3]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.580     ; 1.360      ;
; -2.900 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f14_db[1]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.578     ; 1.355      ;
; -2.900 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f14_db[2]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.578     ; 1.355      ;
; -2.900 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f14_db[4]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.578     ; 1.355      ;
; -2.900 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f14_db[6]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.578     ; 1.355      ;
; -2.900 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f14_db[7]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.578     ; 1.355      ;
; -2.900 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f14_db[0]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.578     ; 1.355      ;
; -2.900 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f14_db[5]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.578     ; 1.355      ;
; -2.900 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f14_db[3]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.578     ; 1.355      ;
; -2.883 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f11_db[1]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.577     ; 1.339      ;
; -2.883 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f11_db[2]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.577     ; 1.339      ;
; -2.883 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f11_db[4]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.577     ; 1.339      ;
; -2.883 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f11_db[6]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.577     ; 1.339      ;
; -2.883 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f11_db[7]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.577     ; 1.339      ;
; -2.883 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f11_db[0]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.577     ; 1.339      ;
; -2.883 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f11_db[5]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.577     ; 1.339      ;
; -2.883 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f11_db[3]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.577     ; 1.339      ;
; -2.880 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f8_db[1]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.588     ; 1.325      ;
; -2.880 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f8_db[2]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.588     ; 1.325      ;
; -2.880 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f8_db[5]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.588     ; 1.325      ;
; -2.880 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f8_db[6]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.588     ; 1.325      ;
; -2.880 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f8_db[7]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.588     ; 1.325      ;
; -2.880 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f8_db[0]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.588     ; 1.325      ;
; -2.880 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f8_db[4]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.588     ; 1.325      ;
; -2.880 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f8_db[3]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.588     ; 1.325      ;
; -2.860 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f3_db[4]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.577     ; 1.316      ;
; -2.860 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f3_db[6]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.577     ; 1.316      ;
; -2.860 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f3_db[7]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.577     ; 1.316      ;
; -2.860 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f3_db[2]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.577     ; 1.316      ;
; -2.827 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f1_db[4]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.577     ; 1.283      ;
; -2.822 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f13_db[1]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.581     ; 1.274      ;
; -2.822 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f13_db[2]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.581     ; 1.274      ;
; -2.822 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f13_db[4]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.581     ; 1.274      ;
; -2.822 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f13_db[6]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.581     ; 1.274      ;
; -2.822 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f13_db[7]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.581     ; 1.274      ;
; -2.822 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f13_db[0]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.581     ; 1.274      ;
; -2.822 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f13_db[5]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.581     ; 1.274      ;
; -2.822 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|f13_db[3]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.581     ; 1.274      ;
; -2.815 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|clk_counter[21] ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.595     ; 1.253      ;
; -2.815 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|clk_counter[15] ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.595     ; 1.253      ;
; -2.815 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|clk_counter[14] ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.595     ; 1.253      ;
; -2.815 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|clk_counter[17] ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.595     ; 1.253      ;
; -2.815 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|clk_counter[16] ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.595     ; 1.253      ;
; -2.815 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|clk_counter[18] ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.595     ; 1.253      ;
; -2.815 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|clk_counter[19] ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.595     ; 1.253      ;
; -2.815 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|clk_counter[20] ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.595     ; 1.253      ;
; -2.815 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|clk_counter[22] ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.595     ; 1.253      ;
; -2.815 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|clk_counter[24] ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.595     ; 1.253      ;
; -2.815 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|clk_counter[25] ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.595     ; 1.253      ;
; -2.815 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|clk_counter[26] ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.595     ; 1.253      ;
; -2.815 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|clk_counter[27] ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.595     ; 1.253      ;
; -2.815 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|clk_counter[23] ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.595     ; 1.253      ;
; -2.806 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|filter[3]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.578     ; 1.261      ;
; -2.806 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|filter[2]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.578     ; 1.261      ;
; -2.796 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|lcd_controller:lcd_controller_1|output[0]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.587     ; 1.242      ;
; -2.796 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|lcd_controller:lcd_controller_1|output[1]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.587     ; 1.242      ;
; -2.796 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|lcd_controller:lcd_controller_1|output[3]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.587     ; 1.242      ;
; -2.795 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|lcd_controller:lcd_controller_1|delay[9]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.574     ; 1.254      ;
; -2.795 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|lcd_controller:lcd_controller_1|delay[6]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.574     ; 1.254      ;
; -2.795 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|lcd_controller:lcd_controller_1|delay[7]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.574     ; 1.254      ;
; -2.795 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|lcd_controller:lcd_controller_1|delay[4]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.574     ; 1.254      ;
; -2.795 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|lcd_controller:lcd_controller_1|delay[5]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.574     ; 1.254      ;
; -2.795 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|lcd_controller:lcd_controller_1|delay[8]        ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.574     ; 1.254      ;
; -2.795 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|clk_counter[9]  ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.593     ; 1.235      ;
; -2.795 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|clk_counter[10] ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.593     ; 1.235      ;
; -2.795 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|clk_counter[11] ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.593     ; 1.235      ;
; -2.795 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|clk_counter[12] ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.593     ; 1.235      ;
; -2.795 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|clk_counter[13] ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.593     ; 1.235      ;
; -2.795 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|clk_counter[8]  ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.593     ; 1.235      ;
; -2.791 ; clock_generator:clock_generator_1|reset ; MMI:MMI_1|mmi_controller:mmi_controller_1|vol_db[0]       ; CLOCK_27     ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.001        ; -1.583     ; 1.241      ;
+--------+-----------------------------------------+-----------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'clock_generator_1|pll_2|altpll_component|pll|clk[1]'                                                                                                                                                                                                                                              ;
+--------+----------------------------------------------------------------------------+---------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                  ; To Node                                                                   ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------+---------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; -0.934 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[0]                ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.058     ; 0.909      ;
; -0.934 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[1]                ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.058     ; 0.909      ;
; -0.934 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[0]                   ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.058     ; 0.909      ;
; -0.934 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[3]                   ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.058     ; 0.909      ;
; -0.884 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stop_warten    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.056     ; 0.861      ;
; -0.884 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stopbedingung  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.056     ; 0.861      ;
; -0.845 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[1]                   ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.042     ; 0.836      ;
; -0.845 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[2]                   ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.042     ; 0.836      ;
; -0.782 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.058     ; 0.757      ;
; -0.782 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~en                   ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.058     ; 0.757      ;
; -0.782 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.anfangszustand ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.058     ; 0.757      ;
; -0.782 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.startbedingung ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.058     ; 0.757      ;
; -0.782 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n          ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.058     ; 0.757      ;
; -0.782 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.taktende       ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.058     ; 0.757      ;
; -0.782 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten     ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.058     ; 0.757      ;
; -0.782 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten2    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.058     ; 0.757      ;
; -0.782 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack            ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.058     ; 0.757      ;
; -0.782 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SCLK                      ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.058     ; 0.757      ;
; -0.682 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[1]             ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.056     ; 0.659      ;
; -0.682 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[0]             ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.056     ; 0.659      ;
; -0.680 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.error          ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.056     ; 0.657      ;
; -0.629 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[2]             ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.054     ; 0.608      ;
; -0.629 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ende           ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.054     ; 0.608      ;
; -0.629 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[3]             ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.001        ; -0.054     ; 0.608      ;
; 5.406  ; clock_generator:clock_generator_1|reset                                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[0]                ; CLOCK_27                                            ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -1.640     ; 2.245      ;
; 5.406  ; clock_generator:clock_generator_1|reset                                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[1]                ; CLOCK_27                                            ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -1.640     ; 2.245      ;
; 5.406  ; clock_generator:clock_generator_1|reset                                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[0]                   ; CLOCK_27                                            ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -1.640     ; 2.245      ;
; 5.406  ; clock_generator:clock_generator_1|reset                                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[3]                   ; CLOCK_27                                            ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -1.640     ; 2.245      ;
; 5.496  ; clock_generator:clock_generator_1|reset                                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[1]                   ; CLOCK_27                                            ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -1.624     ; 2.171      ;
; 5.496  ; clock_generator:clock_generator_1|reset                                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[2]                   ; CLOCK_27                                            ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -1.624     ; 2.171      ;
; 80.624 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[0]                 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 2.741      ;
; 80.698 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[1]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; -0.016     ; 2.651      ;
; 80.726 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[1]                 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 2.639      ;
; 80.792 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[0]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 2.573      ;
; 80.830 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[2]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; -0.016     ; 2.519      ;
; 80.837 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[3]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 2.528      ;
; 81.602 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[1]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; -0.002     ; 1.761      ;
; 81.622 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[0]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; -0.002     ; 1.741      ;
; 81.820 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.taktende        ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[1]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.016      ; 1.561      ;
; 81.820 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.taktende        ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[2]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.016      ; 1.561      ;
; 81.909 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.startbedingung  ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[1]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.016      ; 1.472      ;
; 81.909 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.startbedingung  ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[2]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.016      ; 1.472      ;
; 81.944 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[1]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; -0.016     ; 1.405      ;
; 82.020 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack             ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[1]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.016      ; 1.361      ;
; 82.020 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack             ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[2]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.016      ; 1.361      ;
; 82.032 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[1]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[1]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 1.333      ;
; 82.045 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[0]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 1.320      ;
; 82.066 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[0]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[1]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.016      ; 1.315      ;
; 82.231 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[0]                 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n          ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 1.134      ;
; 82.233 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[2]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[3]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; -0.016     ; 1.116      ;
; 82.286 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.taktende        ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[3]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 1.079      ;
; 82.330 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[2]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n          ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; -0.016     ; 1.019      ;
; 82.364 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack             ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n          ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 1.001      ;
; 82.375 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.startbedingung  ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[3]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 0.990      ;
; 82.377 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[2]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; -0.004     ; 0.984      ;
; 82.389 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.taktende        ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 0.976      ;
; 82.402 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[3]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 0.963      ;
; 82.438 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.anfangszustand  ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 0.927      ;
; 82.444 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[0]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[3]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 0.921      ;
; 82.448 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[1]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[3]             ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.002      ; 0.919      ;
; 82.449 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[1]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[2]             ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.002      ; 0.918      ;
; 82.455 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[2]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; -0.016     ; 0.894      ;
; 82.455 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[1]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n          ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; -0.016     ; 0.894      ;
; 82.456 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[2]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ende           ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 0.909      ;
; 82.471 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[3]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n          ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 0.894      ;
; 82.479 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[2]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.anfangszustand ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; -0.004     ; 0.882      ;
; 82.479 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[1]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[3]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; -0.016     ; 0.870      ;
; 82.486 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack             ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[3]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 0.879      ;
; 82.487 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[1]                 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n          ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 0.878      ;
; 82.491 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[3]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; -0.004     ; 0.870      ;
; 82.508 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stopbedingung   ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.anfangszustand ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; -0.002     ; 0.855      ;
; 82.527 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stopbedingung   ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ende           ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.002      ; 0.840      ;
; 82.532 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[3]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.anfangszustand ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; -0.004     ; 0.829      ;
; 82.539 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stopbedingung   ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[3]             ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.002      ; 0.828      ;
; 82.540 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stopbedingung   ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[2]             ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.002      ; 0.827      ;
; 82.558 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[0]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[3]             ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.002      ; 0.809      ;
; 82.559 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[0]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[2]             ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.002      ; 0.808      ;
; 82.574 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.taktende        ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 0.791      ;
; 82.578 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack             ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[0]                ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 0.787      ;
; 82.582 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ende            ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; -0.004     ; 0.779      ;
; 82.596 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[1]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[2]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 0.769      ;
; 82.597 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[0]                 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stop_warten    ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.002      ; 0.770      ;
; 82.621 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[0]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n          ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 0.744      ;
; 82.624 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[0]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[2]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.016      ; 0.757      ;
; 82.655 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[0]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[1]             ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 0.710      ;
; 82.664 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n           ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 0.701      ;
; 82.669 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten      ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SCLK                      ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 0.696      ;
; 82.707 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[0]                 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[0]                ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 0.658      ;
; 82.738 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.anfangszustand  ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[0]                ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 0.627      ;
; 82.747 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.taktende        ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[0]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 0.618      ;
; 82.748 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack             ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stop_warten    ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.002      ; 0.619      ;
; 82.749 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stop_warten     ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SCLK                      ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; -0.002     ; 0.614      ;
; 82.750 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack             ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.error          ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.002      ; 0.617      ;
; 82.750 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[2]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[3]             ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 0.615      ;
; 82.755 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[0]                 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[1]                ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 0.610      ;
; 82.772 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.error           ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SCLK                      ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; -0.002     ; 0.591      ;
; 82.780 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack             ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SCLK                      ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 0.585      ;
; 82.789 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten2     ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack            ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 0.576      ;
; 82.813 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.taktende        ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n          ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 0.552      ;
; 82.826 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten2     ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~en                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 83.333       ; 0.000      ; 0.539      ;
+--------+----------------------------------------------------------------------------+---------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'AUD_BCLK'                                                                                                                                                                                                                                              ;
+--------+--------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                                                                        ; To Node                                                                                 ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+--------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; -0.428 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[8]  ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.015     ; 1.445      ;
; -0.428 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[9]  ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.015     ; 1.445      ;
; -0.428 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[18] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.015     ; 1.445      ;
; -0.428 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[19] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.015     ; 1.445      ;
; -0.428 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[20] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.015     ; 1.445      ;
; -0.428 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[21] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.015     ; 1.445      ;
; -0.428 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[23] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.015     ; 1.445      ;
; -0.422 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[1]  ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.013     ; 1.441      ;
; -0.422 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[2]  ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.013     ; 1.441      ;
; -0.422 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[3]  ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.013     ; 1.441      ;
; -0.422 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[4]  ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.013     ; 1.441      ;
; -0.422 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[5]  ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.013     ; 1.441      ;
; -0.422 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[6]  ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.013     ; 1.441      ;
; -0.422 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[7]  ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.013     ; 1.441      ;
; -0.422 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[22] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.013     ; 1.441      ;
; -0.410 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[10] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.015     ; 1.427      ;
; -0.410 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[11] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.015     ; 1.427      ;
; -0.410 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[12] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.015     ; 1.427      ;
; -0.410 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[13] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.015     ; 1.427      ;
; -0.410 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[14] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.015     ; 1.427      ;
; -0.410 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[15] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.015     ; 1.427      ;
; -0.410 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[16] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.015     ; 1.427      ;
; -0.410 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[17] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.015     ; 1.427      ;
; -0.403 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[8]  ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.015     ; 1.420      ;
; -0.403 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[9]  ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.015     ; 1.420      ;
; -0.403 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[18] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.015     ; 1.420      ;
; -0.403 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[19] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.015     ; 1.420      ;
; -0.403 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[20] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.015     ; 1.420      ;
; -0.403 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[21] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.015     ; 1.420      ;
; -0.403 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[23] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.015     ; 1.420      ;
; -0.402 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[9]  ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.012     ; 1.422      ;
; -0.402 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[10] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.012     ; 1.422      ;
; -0.402 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[11] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.012     ; 1.422      ;
; -0.402 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[12] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.012     ; 1.422      ;
; -0.402 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[13] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.012     ; 1.422      ;
; -0.402 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[14] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.012     ; 1.422      ;
; -0.402 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[15] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.012     ; 1.422      ;
; -0.402 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[16] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.012     ; 1.422      ;
; -0.402 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[17] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.012     ; 1.422      ;
; -0.400 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[1]  ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.010     ; 1.422      ;
; -0.400 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[2]  ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.010     ; 1.422      ;
; -0.400 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[3]  ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.010     ; 1.422      ;
; -0.400 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[4]  ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.010     ; 1.422      ;
; -0.400 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[5]  ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.010     ; 1.422      ;
; -0.400 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[6]  ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.010     ; 1.422      ;
; -0.400 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[7]  ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.010     ; 1.422      ;
; -0.400 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[8]  ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.010     ; 1.422      ;
; -0.397 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[1]  ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.013     ; 1.416      ;
; -0.397 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[2]  ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.013     ; 1.416      ;
; -0.397 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[3]  ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.013     ; 1.416      ;
; -0.397 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[4]  ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.013     ; 1.416      ;
; -0.397 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[5]  ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.013     ; 1.416      ;
; -0.397 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[6]  ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.013     ; 1.416      ;
; -0.397 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[7]  ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.013     ; 1.416      ;
; -0.397 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[22] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.013     ; 1.416      ;
; -0.385 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[10] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.015     ; 1.402      ;
; -0.385 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[11] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.015     ; 1.402      ;
; -0.385 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[12] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.015     ; 1.402      ;
; -0.385 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[13] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.015     ; 1.402      ;
; -0.385 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[14] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.015     ; 1.402      ;
; -0.385 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[15] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.015     ; 1.402      ;
; -0.385 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[16] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.015     ; 1.402      ;
; -0.385 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[17] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.015     ; 1.402      ;
; -0.377 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[9]  ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.012     ; 1.397      ;
; -0.377 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[10] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.012     ; 1.397      ;
; -0.377 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[11] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.012     ; 1.397      ;
; -0.377 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[12] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.012     ; 1.397      ;
; -0.377 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[13] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.012     ; 1.397      ;
; -0.377 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[14] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.012     ; 1.397      ;
; -0.377 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[15] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.012     ; 1.397      ;
; -0.377 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[16] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.012     ; 1.397      ;
; -0.377 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[17] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.012     ; 1.397      ;
; -0.375 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[1]  ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.010     ; 1.397      ;
; -0.375 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[2]  ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.010     ; 1.397      ;
; -0.375 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[3]  ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.010     ; 1.397      ;
; -0.375 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[4]  ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.010     ; 1.397      ;
; -0.375 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[5]  ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.010     ; 1.397      ;
; -0.375 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[6]  ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.010     ; 1.397      ;
; -0.375 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[7]  ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.010     ; 1.397      ;
; -0.375 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[8]  ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.010     ; 1.397      ;
; -0.331 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[2] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[8]  ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.015     ; 1.348      ;
; -0.331 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[2] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[9]  ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.015     ; 1.348      ;
; -0.331 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[2] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[18] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.015     ; 1.348      ;
; -0.331 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[2] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[19] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.015     ; 1.348      ;
; -0.331 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[2] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[20] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.015     ; 1.348      ;
; -0.331 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[2] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[21] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.015     ; 1.348      ;
; -0.331 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[2] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[23] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.015     ; 1.348      ;
; -0.325 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[2] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[1]  ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.013     ; 1.344      ;
; -0.325 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[2] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[2]  ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.013     ; 1.344      ;
; -0.325 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[2] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[3]  ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.013     ; 1.344      ;
; -0.325 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[2] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[4]  ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.013     ; 1.344      ;
; -0.325 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[2] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[5]  ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.013     ; 1.344      ;
; -0.325 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[2] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[6]  ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.013     ; 1.344      ;
; -0.325 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[2] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[7]  ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.013     ; 1.344      ;
; -0.325 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[2] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[22] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.013     ; 1.344      ;
; -0.313 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[2] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[10] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.015     ; 1.330      ;
; -0.313 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[2] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[11] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.015     ; 1.330      ;
; -0.313 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[2] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[12] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.015     ; 1.330      ;
; -0.313 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[2] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[13] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.015     ; 1.330      ;
; -0.313 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[2] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[14] ; AUD_BCLK     ; AUD_BCLK    ; 1.000        ; -0.015     ; 1.330      ;
+--------+--------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr'                                                                                                                                                                                                                                ;
+-------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-----------------------------------------------------+--------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                 ; To Node                                                                       ; Launch Clock                                        ; Latch Clock                                            ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-----------------------------------------------------+--------------------------------------------------------+--------------+------------+------------+
; 1.665 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[17] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[17] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 1.389      ; 0.756      ;
; 1.702 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[14] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[14] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 1.391      ; 0.721      ;
; 1.723 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[6]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[6]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 1.391      ; 0.700      ;
; 1.729 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[9]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[9]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 1.391      ; 0.694      ;
; 1.735 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[15] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[15] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 1.394      ; 0.691      ;
; 1.736 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[8]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[8]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 1.392      ; 0.688      ;
; 1.738 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[22] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[22] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 1.389      ; 0.683      ;
; 1.738 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[7]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[7]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 1.389      ; 0.683      ;
; 1.740 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[12] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[12] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 1.395      ; 0.687      ;
; 1.742 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[20] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[20] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 1.389      ; 0.679      ;
; 1.743 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[13] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[13] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 1.391      ; 0.680      ;
; 1.743 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[11] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[11] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 1.395      ; 0.684      ;
; 1.746 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[18] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[18] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 1.389      ; 0.675      ;
; 1.752 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[16] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[16] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 1.391      ; 0.671      ;
; 1.753 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[19] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[19] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 1.389      ; 0.668      ;
; 1.757 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[3]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[3]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 1.396      ; 0.671      ;
; 1.766 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[2]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[2]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 1.392      ; 0.658      ;
; 1.836 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[4]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[4]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 1.392      ; 0.588      ;
; 1.843 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[21] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[21] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 1.396      ; 0.585      ;
; 1.852 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[5]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[5]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 1.392      ; 0.572      ;
; 1.853 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[1]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[1]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 1.392      ; 0.571      ;
; 1.857 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[10] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[10] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 1.394      ; 0.569      ;
; 1.956 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[0]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[0]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 1.397      ; 0.473      ;
; 1.960 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[23] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[23] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.000        ; 1.394      ; 0.466      ;
+-------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-----------------------------------------------------+--------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql'                                                                                                                                                                                                                                ;
+-------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-----------------------------------------------------+--------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                 ; To Node                                                                       ; Launch Clock                                        ; Latch Clock                                            ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-----------------------------------------------------+--------------------------------------------------------+--------------+------------+------------+
; 1.674 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[8]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[8]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.322      ; 0.680      ;
; 1.679 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[23] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[23] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.321      ; 0.674      ;
; 1.699 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[21] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[21] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.318      ; 0.651      ;
; 1.742 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[2]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[2]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.320      ; 0.610      ;
; 1.756 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[15] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[15] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.321      ; 0.597      ;
; 1.758 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[7]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[7]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.322      ; 0.596      ;
; 1.788 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[22] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[22] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.318      ; 0.562      ;
; 1.790 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[20] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[20] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.318      ; 0.560      ;
; 1.794 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[11] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[11] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.318      ; 0.556      ;
; 1.795 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[10] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[10] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.318      ; 0.555      ;
; 1.871 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[13] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[13] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.318      ; 0.479      ;
; 1.872 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[14] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[14] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.318      ; 0.478      ;
; 1.873 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[12] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[12] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.318      ; 0.477      ;
; 1.873 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[3]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[3]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.320      ; 0.479      ;
; 1.874 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[0]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[0]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.320      ; 0.478      ;
; 1.875 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[17] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[17] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.318      ; 0.475      ;
; 1.878 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[19] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[19] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.318      ; 0.472      ;
; 1.878 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[9]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[9]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.318      ; 0.472      ;
; 1.879 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[1]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[1]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.319      ; 0.472      ;
; 1.880 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[6]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[6]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.319      ; 0.471      ;
; 1.885 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[4]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[4]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.320      ; 0.467      ;
; 1.888 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[18] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[18] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.318      ; 0.462      ;
; 1.892 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[5]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[5]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.320      ; 0.460      ;
; 1.962 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[16] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[16] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.000        ; 1.319      ; 0.389      ;
+-------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-----------------------------------------------------+--------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'CLOCK_27'                                                                                                                                                             ;
+--------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack  ; From Node                                           ; To Node                                             ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 33.762 ; clock_generator:clock_generator_1|start_counter[12] ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 3.304      ;
; 33.768 ; clock_generator:clock_generator_1|start_counter[13] ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; 0.000      ; 3.301      ;
; 33.777 ; clock_generator:clock_generator_1|start_counter[15] ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; 0.000      ; 3.292      ;
; 33.844 ; clock_generator:clock_generator_1|start_counter[14] ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; 0.000      ; 3.225      ;
; 33.868 ; clock_generator:clock_generator_1|start_counter[16] ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; 0.000      ; 3.201      ;
; 33.912 ; clock_generator:clock_generator_1|start_counter[7]  ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 3.154      ;
; 33.933 ; clock_generator:clock_generator_1|start_counter[24] ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; 0.000      ; 3.136      ;
; 33.954 ; clock_generator:clock_generator_1|start_counter[19] ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; 0.000      ; 3.115      ;
; 33.984 ; clock_generator:clock_generator_1|start_counter[11] ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 3.082      ;
; 33.998 ; clock_generator:clock_generator_1|start_counter[10] ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 3.068      ;
; 34.000 ; clock_generator:clock_generator_1|start_counter[22] ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; 0.000      ; 3.069      ;
; 34.003 ; clock_generator:clock_generator_1|start_counter[6]  ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 3.063      ;
; 34.003 ; clock_generator:clock_generator_1|start_counter[25] ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; 0.000      ; 3.066      ;
; 34.009 ; clock_generator:clock_generator_1|start_counter[21] ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; 0.000      ; 3.060      ;
; 34.020 ; clock_generator:clock_generator_1|start_counter[17] ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; 0.000      ; 3.049      ;
; 34.038 ; clock_generator:clock_generator_1|start_counter[8]  ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 3.028      ;
; 34.050 ; clock_generator:clock_generator_1|start_counter[18] ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; 0.000      ; 3.019      ;
; 34.071 ; clock_generator:clock_generator_1|start_counter[5]  ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 2.995      ;
; 34.079 ; clock_generator:clock_generator_1|start_counter[20] ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; 0.000      ; 2.990      ;
; 34.088 ; clock_generator:clock_generator_1|start_counter[0]  ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 2.978      ;
; 34.092 ; clock_generator:clock_generator_1|start_counter[9]  ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 2.974      ;
; 34.099 ; clock_generator:clock_generator_1|start_counter[4]  ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 2.967      ;
; 34.110 ; clock_generator:clock_generator_1|start_counter[23] ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; 0.000      ; 2.959      ;
; 34.118 ; clock_generator:clock_generator_1|start_counter[2]  ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 2.948      ;
; 34.125 ; clock_generator:clock_generator_1|start_counter[3]  ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 2.941      ;
; 34.224 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|reset             ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 2.842      ;
; 35.015 ; clock_generator:clock_generator_1|start_counter[0]  ; clock_generator:clock_generator_1|start_counter[23] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 2.051      ;
; 35.061 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|start_counter[23] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 2.005      ;
; 35.069 ; clock_generator:clock_generator_1|start_counter[0]  ; clock_generator:clock_generator_1|start_counter[25] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.997      ;
; 35.105 ; clock_generator:clock_generator_1|start_counter[0]  ; clock_generator:clock_generator_1|start_counter[24] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.961      ;
; 35.111 ; clock_generator:clock_generator_1|start_counter[3]  ; clock_generator:clock_generator_1|start_counter[23] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.955      ;
; 35.115 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|start_counter[25] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.951      ;
; 35.151 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|start_counter[24] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.915      ;
; 35.162 ; clock_generator:clock_generator_1|start_counter[4]  ; clock_generator:clock_generator_1|start_counter[23] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.904      ;
; 35.165 ; clock_generator:clock_generator_1|start_counter[3]  ; clock_generator:clock_generator_1|start_counter[25] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.901      ;
; 35.170 ; clock_generator:clock_generator_1|start_counter[2]  ; clock_generator:clock_generator_1|start_counter[23] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.896      ;
; 35.175 ; clock_generator:clock_generator_1|start_counter[0]  ; clock_generator:clock_generator_1|start_counter[22] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.891      ;
; 35.201 ; clock_generator:clock_generator_1|start_counter[3]  ; clock_generator:clock_generator_1|start_counter[24] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.865      ;
; 35.216 ; clock_generator:clock_generator_1|start_counter[4]  ; clock_generator:clock_generator_1|start_counter[25] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.850      ;
; 35.217 ; clock_generator:clock_generator_1|start_counter[0]  ; clock_generator:clock_generator_1|start_counter[21] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.849      ;
; 35.221 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|start_counter[22] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.845      ;
; 35.224 ; clock_generator:clock_generator_1|start_counter[2]  ; clock_generator:clock_generator_1|start_counter[25] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.842      ;
; 35.252 ; clock_generator:clock_generator_1|start_counter[4]  ; clock_generator:clock_generator_1|start_counter[24] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.814      ;
; 35.260 ; clock_generator:clock_generator_1|start_counter[2]  ; clock_generator:clock_generator_1|start_counter[24] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.806      ;
; 35.263 ; clock_generator:clock_generator_1|start_counter[5]  ; clock_generator:clock_generator_1|start_counter[23] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.803      ;
; 35.263 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|start_counter[21] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.803      ;
; 35.271 ; clock_generator:clock_generator_1|start_counter[3]  ; clock_generator:clock_generator_1|start_counter[22] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.795      ;
; 35.286 ; clock_generator:clock_generator_1|start_counter[6]  ; clock_generator:clock_generator_1|start_counter[23] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.780      ;
; 35.313 ; clock_generator:clock_generator_1|start_counter[3]  ; clock_generator:clock_generator_1|start_counter[21] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.753      ;
; 35.315 ; clock_generator:clock_generator_1|start_counter[0]  ; clock_generator:clock_generator_1|start_counter[20] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.751      ;
; 35.317 ; clock_generator:clock_generator_1|start_counter[5]  ; clock_generator:clock_generator_1|start_counter[25] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.749      ;
; 35.322 ; clock_generator:clock_generator_1|start_counter[4]  ; clock_generator:clock_generator_1|start_counter[22] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.744      ;
; 35.327 ; clock_generator:clock_generator_1|start_counter[0]  ; clock_generator:clock_generator_1|start_counter[16] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.739      ;
; 35.330 ; clock_generator:clock_generator_1|start_counter[2]  ; clock_generator:clock_generator_1|start_counter[22] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.736      ;
; 35.331 ; clock_generator:clock_generator_1|start_counter[0]  ; clock_generator:clock_generator_1|start_counter[13] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.735      ;
; 35.340 ; clock_generator:clock_generator_1|start_counter[0]  ; clock_generator:clock_generator_1|start_counter[19] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.726      ;
; 35.340 ; clock_generator:clock_generator_1|start_counter[6]  ; clock_generator:clock_generator_1|start_counter[25] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.726      ;
; 35.353 ; clock_generator:clock_generator_1|start_counter[5]  ; clock_generator:clock_generator_1|start_counter[24] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.713      ;
; 35.355 ; clock_generator:clock_generator_1|start_counter[8]  ; clock_generator:clock_generator_1|start_counter[23] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.711      ;
; 35.361 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|start_counter[20] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.705      ;
; 35.364 ; clock_generator:clock_generator_1|start_counter[0]  ; clock_generator:clock_generator_1|start_counter[15] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.702      ;
; 35.364 ; clock_generator:clock_generator_1|start_counter[4]  ; clock_generator:clock_generator_1|start_counter[21] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.702      ;
; 35.371 ; clock_generator:clock_generator_1|start_counter[0]  ; clock_generator:clock_generator_1|start_counter[18] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.695      ;
; 35.372 ; clock_generator:clock_generator_1|start_counter[2]  ; clock_generator:clock_generator_1|start_counter[21] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.694      ;
; 35.373 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|start_counter[16] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.693      ;
; 35.376 ; clock_generator:clock_generator_1|start_counter[6]  ; clock_generator:clock_generator_1|start_counter[24] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.690      ;
; 35.377 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|start_counter[13] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.689      ;
; 35.386 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|start_counter[19] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.680      ;
; 35.389 ; clock_generator:clock_generator_1|start_counter[9]  ; clock_generator:clock_generator_1|start_counter[23] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.677      ;
; 35.407 ; clock_generator:clock_generator_1|start_counter[0]  ; clock_generator:clock_generator_1|start_counter[17] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.659      ;
; 35.409 ; clock_generator:clock_generator_1|start_counter[8]  ; clock_generator:clock_generator_1|start_counter[25] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.657      ;
; 35.410 ; clock_generator:clock_generator_1|start_counter[7]  ; clock_generator:clock_generator_1|start_counter[23] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.656      ;
; 35.410 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|start_counter[15] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.656      ;
; 35.411 ; clock_generator:clock_generator_1|start_counter[3]  ; clock_generator:clock_generator_1|start_counter[20] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.655      ;
; 35.417 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|start_counter[18] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.649      ;
; 35.423 ; clock_generator:clock_generator_1|start_counter[5]  ; clock_generator:clock_generator_1|start_counter[22] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.643      ;
; 35.423 ; clock_generator:clock_generator_1|start_counter[3]  ; clock_generator:clock_generator_1|start_counter[16] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.643      ;
; 35.427 ; clock_generator:clock_generator_1|start_counter[3]  ; clock_generator:clock_generator_1|start_counter[13] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.639      ;
; 35.429 ; clock_generator:clock_generator_1|start_counter[10] ; clock_generator:clock_generator_1|start_counter[23] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.637      ;
; 35.436 ; clock_generator:clock_generator_1|start_counter[3]  ; clock_generator:clock_generator_1|start_counter[19] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.630      ;
; 35.443 ; clock_generator:clock_generator_1|start_counter[9]  ; clock_generator:clock_generator_1|start_counter[25] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.623      ;
; 35.445 ; clock_generator:clock_generator_1|start_counter[8]  ; clock_generator:clock_generator_1|start_counter[24] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.621      ;
; 35.446 ; clock_generator:clock_generator_1|start_counter[6]  ; clock_generator:clock_generator_1|start_counter[22] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.620      ;
; 35.448 ; clock_generator:clock_generator_1|start_counter[12] ; clock_generator:clock_generator_1|start_counter[21] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.618      ;
; 35.449 ; clock_generator:clock_generator_1|start_counter[11] ; clock_generator:clock_generator_1|start_counter[23] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.617      ;
; 35.449 ; clock_generator:clock_generator_1|start_counter[12] ; clock_generator:clock_generator_1|start_counter[20] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.617      ;
; 35.450 ; clock_generator:clock_generator_1|start_counter[12] ; clock_generator:clock_generator_1|start_counter[13] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.616      ;
; 35.451 ; clock_generator:clock_generator_1|start_counter[12] ; clock_generator:clock_generator_1|start_counter[15] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.615      ;
; 35.453 ; clock_generator:clock_generator_1|start_counter[12] ; clock_generator:clock_generator_1|start_counter[7]  ; CLOCK_27     ; CLOCK_27    ; 37.037       ; 0.000      ; 1.616      ;
; 35.453 ; clock_generator:clock_generator_1|start_counter[12] ; clock_generator:clock_generator_1|start_counter[23] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.613      ;
; 35.453 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|start_counter[17] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.613      ;
; 35.454 ; clock_generator:clock_generator_1|start_counter[13] ; clock_generator:clock_generator_1|start_counter[21] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; 0.000      ; 1.615      ;
; 35.455 ; clock_generator:clock_generator_1|start_counter[12] ; clock_generator:clock_generator_1|start_counter[24] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.611      ;
; 35.455 ; clock_generator:clock_generator_1|start_counter[12] ; clock_generator:clock_generator_1|start_counter[22] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.611      ;
; 35.455 ; clock_generator:clock_generator_1|start_counter[12] ; clock_generator:clock_generator_1|start_counter[16] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.611      ;
; 35.455 ; clock_generator:clock_generator_1|start_counter[13] ; clock_generator:clock_generator_1|start_counter[20] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; 0.000      ; 1.614      ;
; 35.456 ; clock_generator:clock_generator_1|start_counter[13] ; clock_generator:clock_generator_1|start_counter[13] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; 0.000      ; 1.613      ;
; 35.457 ; clock_generator:clock_generator_1|start_counter[12] ; clock_generator:clock_generator_1|start_counter[14] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.609      ;
; 35.457 ; clock_generator:clock_generator_1|start_counter[12] ; clock_generator:clock_generator_1|start_counter[17] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; -0.003     ; 1.609      ;
; 35.457 ; clock_generator:clock_generator_1|start_counter[13] ; clock_generator:clock_generator_1|start_counter[15] ; CLOCK_27     ; CLOCK_27    ; 37.037       ; 0.000      ; 1.612      ;
+--------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Setup: 'clock_generator_1|pll_1|altpll_component|pll|clk[1]'                                                                                                                                                                                                                                               ;
+--------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                                  ; To Node                                                                    ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+--------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; 98.561 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.006      ; 1.477      ;
; 98.580 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.006      ; 1.458      ;
; 98.628 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.006      ; 1.410      ;
; 98.702 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.006      ; 1.336      ;
; 98.724 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.308      ;
; 98.854 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.006      ; 1.184      ;
; 98.902 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.130      ;
; 98.921 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.111      ;
; 98.938 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.006      ; 1.100      ;
; 98.969 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.063      ;
; 98.996 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.006      ; 1.042      ;
; 99.022 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.010      ;
; 99.023 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 1.009      ;
; 99.030 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.006      ; 1.008      ;
; 99.040 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.006      ; 0.998      ;
; 99.042 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.990      ;
; 99.043 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.989      ;
; 99.050 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.982      ;
; 99.071 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.961      ;
; 99.077 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.955      ;
; 99.105 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.927      ;
; 99.112 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.920      ;
; 99.126 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.906      ;
; 99.140 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.892      ;
; 99.147 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.885      ;
; 99.161 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.871      ;
; 99.175 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.857      ;
; 99.178 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.854      ;
; 99.182 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.850      ;
; 99.195 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.837      ;
; 99.196 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.836      ;
; 99.210 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.822      ;
; 99.213 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.819      ;
; 99.217 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.815      ;
; 99.222 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.810      ;
; 99.231 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.801      ;
; 99.245 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.787      ;
; 99.248 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.784      ;
; 99.258 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.774      ;
; 99.266 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.766      ;
; 99.279 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.753      ;
; 99.283 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.749      ;
; 99.293 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.739      ;
; 99.310 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.722      ;
; 99.316 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.716      ;
; 99.318 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.714      ;
; 99.328 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.704      ;
; 99.328 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.704      ;
; 99.337 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.695      ;
; 99.345 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.687      ;
; 99.346 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.686      ;
; 99.363 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.669      ;
; 99.363 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.669      ;
; 99.374 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.658      ;
; 99.380 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.652      ;
; 99.380 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.652      ;
; 99.400 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.632      ;
; 99.458 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.574      ;
; 99.500 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.532      ;
; 99.502 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.530      ;
; 99.503 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.529      ;
; 99.503 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.529      ;
; 99.505 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.527      ;
; 99.518 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.514      ;
; 99.518 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.514      ;
; 99.519 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.513      ;
; 99.627 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 100.000      ; 0.000      ; 0.405      ;
+--------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql'                                                                                                                                                                                                                                  ;
+--------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-----------------------------------------------------+--------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                 ; To Node                                                                       ; Launch Clock                                        ; Latch Clock                                            ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-----------------------------------------------------+--------------------------------------------------------+--------------+------------+------------+
; -1.082 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[16] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[16] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.319      ; 0.389      ;
; -1.012 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[5]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[5]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.320      ; 0.460      ;
; -1.008 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[18] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[18] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.318      ; 0.462      ;
; -1.005 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[4]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[4]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.320      ; 0.467      ;
; -1.000 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[6]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[6]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.319      ; 0.471      ;
; -0.999 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[1]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[1]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.319      ; 0.472      ;
; -0.998 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[19] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[19] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.318      ; 0.472      ;
; -0.998 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[9]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[9]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.318      ; 0.472      ;
; -0.995 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[17] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[17] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.318      ; 0.475      ;
; -0.994 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[0]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[0]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.320      ; 0.478      ;
; -0.993 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[12] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[12] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.318      ; 0.477      ;
; -0.993 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[3]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[3]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.320      ; 0.479      ;
; -0.992 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[14] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[14] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.318      ; 0.478      ;
; -0.991 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[13] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[13] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.318      ; 0.479      ;
; -0.915 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[10] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[10] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.318      ; 0.555      ;
; -0.914 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[11] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[11] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.318      ; 0.556      ;
; -0.910 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[20] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[20] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.318      ; 0.560      ;
; -0.908 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[22] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[22] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.318      ; 0.562      ;
; -0.878 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[7]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[7]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.322      ; 0.596      ;
; -0.876 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[15] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[15] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.321      ; 0.597      ;
; -0.862 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[2]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[2]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.320      ; 0.610      ;
; -0.819 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[21] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[21] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.318      ; 0.651      ;
; -0.799 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[23] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[23] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.321      ; 0.674      ;
; -0.794 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdl[8]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[8]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000        ; 1.322      ; 0.680      ;
+--------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-----------------------------------------------------+--------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr'                                                                                                                                                                                                                                  ;
+--------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-----------------------------------------------------+--------------------------------------------------------+--------------+------------+------------+
; Slack  ; From Node                                                 ; To Node                                                                       ; Launch Clock                                        ; Latch Clock                                            ; Relationship ; Clock Skew ; Data Delay ;
+--------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-----------------------------------------------------+--------------------------------------------------------+--------------+------------+------------+
; -1.080 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[23] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[23] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 1.394      ; 0.466      ;
; -1.076 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[0]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[0]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 1.397      ; 0.473      ;
; -0.977 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[10] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[10] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 1.394      ; 0.569      ;
; -0.973 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[1]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[1]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 1.392      ; 0.571      ;
; -0.972 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[5]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[5]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 1.392      ; 0.572      ;
; -0.963 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[21] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[21] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 1.396      ; 0.585      ;
; -0.956 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[4]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[4]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 1.392      ; 0.588      ;
; -0.886 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[2]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[2]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 1.392      ; 0.658      ;
; -0.877 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[3]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[3]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 1.396      ; 0.671      ;
; -0.873 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[19] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[19] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 1.389      ; 0.668      ;
; -0.872 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[16] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[16] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 1.391      ; 0.671      ;
; -0.866 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[18] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[18] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 1.389      ; 0.675      ;
; -0.863 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[13] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[13] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 1.391      ; 0.680      ;
; -0.863 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[11] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[11] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 1.395      ; 0.684      ;
; -0.862 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[20] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[20] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 1.389      ; 0.679      ;
; -0.860 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[12] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[12] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 1.395      ; 0.687      ;
; -0.858 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[22] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[22] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 1.389      ; 0.683      ;
; -0.858 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[7]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[7]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 1.389      ; 0.683      ;
; -0.856 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[8]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[8]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 1.392      ; 0.688      ;
; -0.855 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[15] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[15] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 1.394      ; 0.691      ;
; -0.849 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[9]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[9]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 1.391      ; 0.694      ;
; -0.843 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[6]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[6]  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 1.391      ; 0.700      ;
; -0.822 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[14] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[14] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 1.391      ; 0.721      ;
; -0.785 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|qdr[17] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[17] ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000        ; 1.389      ; 0.756      ;
+--------+-----------------------------------------------------------+-------------------------------------------------------------------------------+-----------------------------------------------------+--------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'clock_generator_1|pll_1|altpll_component|pll|clk[0]'                                                                                                                                                                                                                                            ;
+-------+-------------------------------------------------------------------------+-------------------------------------------------------------------------+--------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                               ; To Node                                                                 ; Launch Clock                                           ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-------------------------------------------------------------------------+-------------------------------------------------------------------------+--------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; 0.013 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr                  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr                  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.061      ; 0.367      ;
; 0.025 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql                  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql                  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.049      ; 0.367      ;
; 0.215 ; MMI:MMI_1|lcd_controller:lcd_controller_1|index[0]                      ; MMI:MMI_1|lcd_controller:lcd_controller_1|index[0]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|lcd_controller:lcd_controller_1|delay[0]                      ; MMI:MMI_1|lcd_controller:lcd_controller_1|delay[0]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|lcd_controller:lcd_controller_1|index[2]                      ; MMI:MMI_1|lcd_controller:lcd_controller_1|index[2]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|lcd_controller:lcd_controller_1|start                         ; MMI:MMI_1|lcd_controller:lcd_controller_1|start                         ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|lcd_controller:lcd_controller_1|counter[2]                    ; MMI:MMI_1|lcd_controller:lcd_controller_1|counter[2]                    ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|lcd_controller:lcd_controller_1|counter[3]                    ; MMI:MMI_1|lcd_controller:lcd_controller_1|counter[3]                    ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|lcd_controller:lcd_controller_1|counter[0]                    ; MMI:MMI_1|lcd_controller:lcd_controller_1|counter[0]                    ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|lcd_controller:lcd_controller_1|counter[1]                    ; MMI:MMI_1|lcd_controller:lcd_controller_1|counter[1]                    ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|filter[3]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|filter[3]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|filter[0]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|filter[0]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f13_db[4]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f13_db[4]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f13_db[6]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f13_db[6]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f13_db[7]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f13_db[7]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f13_db[0]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f13_db[0]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f13_db[5]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f13_db[5]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f13_db[3]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f13_db[3]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f12_db[2]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f12_db[2]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f12_db[4]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f12_db[4]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f12_db[5]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f12_db[5]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f12_db[7]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f12_db[7]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f12_db[6]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f12_db[6]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f12_db[3]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f12_db[3]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f14_db[4]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f14_db[4]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f14_db[6]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f14_db[6]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f14_db[7]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f14_db[7]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f14_db[0]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f14_db[0]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f14_db[5]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f14_db[5]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f14_db[3]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f14_db[3]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f1_db[0]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f1_db[0]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f1_db[5]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f1_db[5]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f1_db[6]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f1_db[6]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f1_db[7]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f1_db[7]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f1_db[3]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f1_db[3]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f2_db[4]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f2_db[4]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f2_db[5]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f2_db[5]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f2_db[7]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f2_db[7]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f2_db[0]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f2_db[0]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f2_db[6]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f2_db[6]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f2_db[3]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f2_db[3]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f3_db[4]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f3_db[4]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f3_db[5]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f3_db[5]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f3_db[6]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f3_db[6]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f3_db[7]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f3_db[7]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f3_db[2]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f3_db[2]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f3_db[3]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f3_db[3]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f4_db[1]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f4_db[1]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f4_db[2]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f4_db[2]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f4_db[4]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f4_db[4]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f4_db[5]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f4_db[5]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f4_db[6]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f4_db[6]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f4_db[7]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f4_db[7]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f4_db[0]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f4_db[0]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f4_db[3]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f4_db[3]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[1]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[1]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[2]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[2]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[4]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[4]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[5]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[5]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[6]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[6]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[0]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[0]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[7]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[7]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[3]                      ; MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[3]                      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f10_db[1]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f10_db[1]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f10_db[2]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f10_db[2]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f10_db[4]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f10_db[4]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f10_db[6]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f10_db[6]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f10_db[7]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f10_db[7]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f10_db[0]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f10_db[0]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f10_db[5]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f10_db[5]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; MMI:MMI_1|mmi_controller:mmi_controller_1|f10_db[3]                     ; MMI:MMI_1|mmi_controller:mmi_controller_1|f10_db[3]                     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_right[0]      ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_right[0]      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_right[7]      ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_right[7]      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_right[8]      ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_right[8]      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_right[9]      ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_right[9]      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_right[10]     ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_right[10]     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_right[11]     ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_right[11]     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_left[8]       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_left[8]       ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_left[9]       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_left[9]       ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_left[10]      ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_left[10]      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_left[11]      ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_left[11]      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_left[0]       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_left[0]       ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_left[7]       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_left[7]       ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|section[1] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|section[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|section[2] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|section[2] ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|counter[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|counter[0] ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|counter[1] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|counter[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|counter[2] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|counter[2] ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|counter[4] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|counter[4] ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|counter[5] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|counter[5] ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|counter[7] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|counter[7] ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|counter[6] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|counter[6] ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|section[0] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|section[0] ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|section[3] ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|section[3] ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[16]     ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[16]     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[11]     ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[11]     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[10]     ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[10]     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[8]      ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[8]      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[1]      ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[1]      ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[24]     ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[24]     ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; 0.000        ; 0.000      ; 0.367      ;
+-------+-------------------------------------------------------------------------+-------------------------------------------------------------------------+--------------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'AUD_BCLK'                                                                                                                                                                                                                                                       ;
+-------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                                                                        ; To Node                                                                                          ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.085 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[5]                      ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.289      ; 0.526      ;
; 0.089 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[4]                      ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.289      ; 0.530      ;
; 0.089 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[7]                      ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.289      ; 0.530      ;
; 0.090 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[3]                      ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.289      ; 0.531      ;
; 0.091 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[8]                      ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.289      ; 0.532      ;
; 0.091 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[23]                     ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.289      ; 0.532      ;
; 0.201 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[2]                      ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.289      ; 0.642      ;
; 0.212 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[14]                     ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.289      ; 0.653      ;
; 0.215 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|enr                          ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|enr                          ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|enl                          ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|enl                          ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_left[4]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_left[4]  ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_left[0]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_left[0]  ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_left[3]  ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_left[3]  ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[0] ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[2] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[2] ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[3] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[3] ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[1] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[1] ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4] ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.367      ;
; 0.221 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[13]                     ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.289      ; 0.662      ;
; 0.222 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[15]                     ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.289      ; 0.663      ;
; 0.224 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[3]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dr[4]                        ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.281      ; 0.657      ;
; 0.240 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[6]           ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[7]           ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.392      ;
; 0.240 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[22]          ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[23]          ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.392      ;
; 0.241 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[2]           ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[3]           ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.393      ;
; 0.243 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[5]           ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[6]           ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.395      ;
; 0.256 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[3]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dr[19]                       ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.264      ; 0.672      ;
; 0.259 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[4]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[4]             ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.411      ;
; 0.283 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[4]              ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[5]                        ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.269      ; 0.704      ;
; 0.283 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[4]              ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[4]                        ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.269      ; 0.704      ;
; 0.283 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[4]              ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[21]                       ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.269      ; 0.704      ;
; 0.293 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[7]           ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[8]           ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.445      ;
; 0.297 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[4]              ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[12]                       ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.209      ; 0.658      ;
; 0.297 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[4]              ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[9]                        ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.209      ; 0.658      ;
; 0.298 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[4]              ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[14]                       ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.209      ; 0.659      ;
; 0.298 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[4]              ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[13]                       ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.209      ; 0.659      ;
; 0.299 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[4]              ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[10]                       ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.209      ; 0.660      ;
; 0.300 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[4]              ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[15]                       ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.209      ; 0.661      ;
; 0.300 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[4]              ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[11]                       ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.209      ; 0.661      ;
; 0.301 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[6]                      ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.289      ; 0.742      ;
; 0.303 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[19]                     ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.289      ; 0.744      ;
; 0.304 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[10]                     ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.289      ; 0.745      ;
; 0.304 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[11]                     ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.289      ; 0.745      ;
; 0.305 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[9]                      ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.289      ; 0.746      ;
; 0.306 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[12]                     ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.289      ; 0.747      ;
; 0.310 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[20]                     ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.281      ; 0.743      ;
; 0.311 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[18]                     ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.281      ; 0.744      ;
; 0.312 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[0]                      ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.281      ; 0.745      ;
; 0.313 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[17]                     ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.281      ; 0.746      ;
; 0.316 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[16]                     ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.281      ; 0.749      ;
; 0.317 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[21]                     ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.281      ; 0.750      ;
; 0.318 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[22]                     ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.281      ; 0.751      ;
; 0.319 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[1]                      ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.281      ; 0.752      ;
; 0.333 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[4]              ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[3]                        ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.269      ; 0.754      ;
; 0.336 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[4]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dr[18]                       ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.281      ; 0.769      ;
; 0.337 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[4]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dr[4]                        ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.281      ; 0.770      ;
; 0.339 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[4]              ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[4]              ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.491      ;
; 0.340 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[3]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dr[18]                       ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.281      ; 0.773      ;
; 0.349 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[3]              ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[21]                       ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.269      ; 0.770      ;
; 0.351 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[3]              ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[4]                        ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.269      ; 0.772      ;
; 0.352 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[3]              ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[5]                        ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.269      ; 0.773      ;
; 0.355 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[18]          ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[19]          ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.507      ;
; 0.356 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[18]          ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[19]          ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.508      ;
; 0.356 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[21]          ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[22]          ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.508      ;
; 0.358 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[9]           ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[10]          ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.510      ;
; 0.358 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[19]          ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[20]          ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.510      ;
; 0.359 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[4]           ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[5]           ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.511      ;
; 0.359 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[10]          ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[11]          ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.511      ;
; 0.359 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[11]          ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[12]          ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.511      ;
; 0.360 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[8]           ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[9]           ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.512      ;
; 0.360 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[15]          ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[16]          ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.512      ;
; 0.360 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[16]          ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[17]          ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.512      ;
; 0.361 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[3]           ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[4]           ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.513      ;
; 0.361 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[6]           ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[7]           ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.513      ;
; 0.361 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[15]          ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[16]          ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.513      ;
; 0.361 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[13]          ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[14]          ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.513      ;
; 0.362 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[0]              ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[0]              ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.514      ;
; 0.362 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[16]                     ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[17]                     ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.514      ;
; 0.362 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[1]           ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[2]           ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.514      ;
; 0.362 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[16]          ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[17]          ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.514      ;
; 0.363 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[4]              ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[6]                        ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.267      ; 0.782      ;
; 0.363 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[11]          ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[12]          ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.515      ;
; 0.364 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[3]           ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[4]           ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.516      ;
; 0.365 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[20]          ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[21]          ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.517      ;
; 0.366 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[10]                     ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[11]                     ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.518      ;
; 0.366 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[17]                     ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[18]                     ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.518      ;
; 0.366 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[2]           ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[3]           ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.518      ;
; 0.367 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[5]                      ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[6]                      ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.519      ;
; 0.367 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[9]                      ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[10]                     ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.519      ;
; 0.367 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[8]                      ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[9]                      ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.519      ;
; 0.367 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[11]                     ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[12]                     ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.519      ;
; 0.367 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[12]          ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[13]          ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.519      ;
; 0.369 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1]             ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.521      ;
; 0.369 ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[12]                     ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[13]                     ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.521      ;
; 0.369 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[4]           ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[5]           ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.521      ;
; 0.370 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[13]          ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[14]          ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.522      ;
; 0.370 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[1]           ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[2]           ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.522      ;
; 0.370 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[12]          ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[13]          ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.522      ;
; 0.370 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[14]          ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[15]          ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.522      ;
; 0.370 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[20]          ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[21]          ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.522      ;
; 0.371 ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[5]           ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[6]           ; AUD_BCLK     ; AUD_BCLK    ; 0.000        ; 0.000      ; 0.523      ;
+-------+--------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'CLOCK_27'                                                                                                                                                             ;
+-------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------+
; Slack ; From Node                                           ; To Node                                             ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------+
; 0.215 ; clock_generator:clock_generator_1|start_counter[0]  ; clock_generator:clock_generator_1|start_counter[0]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 0.367      ;
; 0.518 ; clock_generator:clock_generator_1|start_counter[12] ; clock_generator:clock_generator_1|start_counter[12] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 0.670      ;
; 0.572 ; clock_generator:clock_generator_1|start_counter[7]  ; clock_generator:clock_generator_1|start_counter[7]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 0.724      ;
; 0.576 ; clock_generator:clock_generator_1|start_counter[25] ; clock_generator:clock_generator_1|start_counter[25] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 0.728      ;
; 0.655 ; clock_generator:clock_generator_1|start_counter[2]  ; clock_generator:clock_generator_1|start_counter[2]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 0.807      ;
; 0.681 ; clock_generator:clock_generator_1|start_counter[5]  ; clock_generator:clock_generator_1|start_counter[5]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 0.833      ;
; 0.686 ; clock_generator:clock_generator_1|start_counter[24] ; clock_generator:clock_generator_1|start_counter[24] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 0.838      ;
; 0.689 ; clock_generator:clock_generator_1|start_counter[20] ; clock_generator:clock_generator_1|start_counter[20] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 0.841      ;
; 0.691 ; clock_generator:clock_generator_1|start_counter[21] ; clock_generator:clock_generator_1|start_counter[21] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 0.843      ;
; 0.693 ; clock_generator:clock_generator_1|start_counter[22] ; clock_generator:clock_generator_1|start_counter[22] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 0.845      ;
; 0.694 ; clock_generator:clock_generator_1|start_counter[10] ; clock_generator:clock_generator_1|start_counter[10] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 0.846      ;
; 0.697 ; clock_generator:clock_generator_1|start_counter[8]  ; clock_generator:clock_generator_1|start_counter[8]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 0.849      ;
; 0.699 ; clock_generator:clock_generator_1|start_counter[6]  ; clock_generator:clock_generator_1|start_counter[6]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 0.851      ;
; 0.699 ; clock_generator:clock_generator_1|start_counter[9]  ; clock_generator:clock_generator_1|start_counter[9]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 0.851      ;
; 0.699 ; clock_generator:clock_generator_1|start_counter[19] ; clock_generator:clock_generator_1|start_counter[19] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 0.851      ;
; 0.700 ; clock_generator:clock_generator_1|start_counter[17] ; clock_generator:clock_generator_1|start_counter[17] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 0.852      ;
; 0.703 ; clock_generator:clock_generator_1|start_counter[14] ; clock_generator:clock_generator_1|start_counter[14] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 0.855      ;
; 0.706 ; clock_generator:clock_generator_1|start_counter[18] ; clock_generator:clock_generator_1|start_counter[18] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 0.858      ;
; 0.707 ; clock_generator:clock_generator_1|start_counter[11] ; clock_generator:clock_generator_1|start_counter[11] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 0.859      ;
; 0.745 ; clock_generator:clock_generator_1|start_counter[7]  ; clock_generator:clock_generator_1|start_counter[8]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 0.897      ;
; 0.759 ; clock_generator:clock_generator_1|start_counter[11] ; clock_generator:clock_generator_1|start_counter[12] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 0.911      ;
; 0.779 ; clock_generator:clock_generator_1|start_counter[10] ; clock_generator:clock_generator_1|start_counter[12] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 0.931      ;
; 0.781 ; clock_generator:clock_generator_1|start_counter[7]  ; clock_generator:clock_generator_1|start_counter[9]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 0.933      ;
; 0.798 ; clock_generator:clock_generator_1|start_counter[7]  ; clock_generator:clock_generator_1|start_counter[12] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 0.950      ;
; 0.799 ; clock_generator:clock_generator_1|start_counter[6]  ; clock_generator:clock_generator_1|start_counter[7]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 0.951      ;
; 0.800 ; clock_generator:clock_generator_1|start_counter[16] ; clock_generator:clock_generator_1|start_counter[16] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 0.952      ;
; 0.810 ; clock_generator:clock_generator_1|start_counter[4]  ; clock_generator:clock_generator_1|start_counter[4]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 0.962      ;
; 0.814 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|start_counter[1]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 0.966      ;
; 0.816 ; clock_generator:clock_generator_1|start_counter[7]  ; clock_generator:clock_generator_1|start_counter[10] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 0.968      ;
; 0.817 ; clock_generator:clock_generator_1|start_counter[15] ; clock_generator:clock_generator_1|start_counter[15] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 0.969      ;
; 0.819 ; clock_generator:clock_generator_1|start_counter[9]  ; clock_generator:clock_generator_1|start_counter[12] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 0.971      ;
; 0.822 ; clock_generator:clock_generator_1|start_counter[5]  ; clock_generator:clock_generator_1|start_counter[7]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 0.974      ;
; 0.823 ; clock_generator:clock_generator_1|start_counter[16] ; clock_generator:clock_generator_1|start_counter[17] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 0.975      ;
; 0.825 ; clock_generator:clock_generator_1|start_counter[24] ; clock_generator:clock_generator_1|start_counter[25] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 0.977      ;
; 0.825 ; clock_generator:clock_generator_1|start_counter[5]  ; clock_generator:clock_generator_1|start_counter[6]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 0.977      ;
; 0.827 ; clock_generator:clock_generator_1|start_counter[19] ; clock_generator:clock_generator_1|start_counter[20] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 0.979      ;
; 0.829 ; clock_generator:clock_generator_1|start_counter[12] ; clock_generator:clock_generator_1|start_counter[14] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; -0.003     ; 0.978      ;
; 0.831 ; clock_generator:clock_generator_1|start_counter[3]  ; clock_generator:clock_generator_1|start_counter[3]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 0.983      ;
; 0.831 ; clock_generator:clock_generator_1|start_counter[23] ; clock_generator:clock_generator_1|start_counter[23] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 0.983      ;
; 0.832 ; clock_generator:clock_generator_1|start_counter[10] ; clock_generator:clock_generator_1|start_counter[11] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 0.984      ;
; 0.836 ; clock_generator:clock_generator_1|start_counter[21] ; clock_generator:clock_generator_1|start_counter[22] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 0.988      ;
; 0.836 ; clock_generator:clock_generator_1|start_counter[8]  ; clock_generator:clock_generator_1|start_counter[9]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 0.988      ;
; 0.837 ; clock_generator:clock_generator_1|start_counter[9]  ; clock_generator:clock_generator_1|start_counter[10] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 0.989      ;
; 0.839 ; clock_generator:clock_generator_1|start_counter[17] ; clock_generator:clock_generator_1|start_counter[18] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 0.991      ;
; 0.842 ; clock_generator:clock_generator_1|start_counter[18] ; clock_generator:clock_generator_1|start_counter[19] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 0.994      ;
; 0.846 ; clock_generator:clock_generator_1|start_counter[23] ; clock_generator:clock_generator_1|start_counter[24] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 0.998      ;
; 0.851 ; clock_generator:clock_generator_1|start_counter[7]  ; clock_generator:clock_generator_1|start_counter[11] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.003      ;
; 0.853 ; clock_generator:clock_generator_1|start_counter[8]  ; clock_generator:clock_generator_1|start_counter[12] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.005      ;
; 0.853 ; clock_generator:clock_generator_1|start_counter[13] ; clock_generator:clock_generator_1|start_counter[14] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.005      ;
; 0.859 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|start_counter[8]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.011      ;
; 0.859 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|start_counter[9]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.011      ;
; 0.859 ; clock_generator:clock_generator_1|start_counter[16] ; clock_generator:clock_generator_1|start_counter[18] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.011      ;
; 0.865 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|start_counter[10] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.017      ;
; 0.866 ; clock_generator:clock_generator_1|start_counter[22] ; clock_generator:clock_generator_1|start_counter[24] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.018      ;
; 0.867 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|start_counter[2]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.019      ;
; 0.867 ; clock_generator:clock_generator_1|start_counter[18] ; clock_generator:clock_generator_1|start_counter[20] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.019      ;
; 0.869 ; clock_generator:clock_generator_1|start_counter[6]  ; clock_generator:clock_generator_1|start_counter[8]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.021      ;
; 0.870 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|start_counter[3]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.022      ;
; 0.870 ; clock_generator:clock_generator_1|start_counter[17] ; clock_generator:clock_generator_1|start_counter[19] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.022      ;
; 0.871 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|start_counter[5]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.023      ;
; 0.871 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|start_counter[4]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.023      ;
; 0.871 ; clock_generator:clock_generator_1|start_counter[8]  ; clock_generator:clock_generator_1|start_counter[10] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.023      ;
; 0.872 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|start_counter[6]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.024      ;
; 0.872 ; clock_generator:clock_generator_1|start_counter[9]  ; clock_generator:clock_generator_1|start_counter[11] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.024      ;
; 0.873 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|start_counter[11] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.025      ;
; 0.877 ; clock_generator:clock_generator_1|start_counter[2]  ; clock_generator:clock_generator_1|start_counter[5]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.029      ;
; 0.877 ; clock_generator:clock_generator_1|start_counter[15] ; clock_generator:clock_generator_1|start_counter[17] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.029      ;
; 0.877 ; clock_generator:clock_generator_1|start_counter[2]  ; clock_generator:clock_generator_1|start_counter[3]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.029      ;
; 0.882 ; clock_generator:clock_generator_1|start_counter[23] ; clock_generator:clock_generator_1|start_counter[25] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.034      ;
; 0.885 ; clock_generator:clock_generator_1|start_counter[4]  ; clock_generator:clock_generator_1|start_counter[5]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.037      ;
; 0.886 ; clock_generator:clock_generator_1|start_counter[20] ; clock_generator:clock_generator_1|start_counter[21] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.038      ;
; 0.890 ; clock_generator:clock_generator_1|start_counter[16] ; clock_generator:clock_generator_1|start_counter[19] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.042      ;
; 0.892 ; clock_generator:clock_generator_1|start_counter[5]  ; clock_generator:clock_generator_1|start_counter[8]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.044      ;
; 0.895 ; clock_generator:clock_generator_1|start_counter[17] ; clock_generator:clock_generator_1|start_counter[20] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.047      ;
; 0.901 ; clock_generator:clock_generator_1|start_counter[2]  ; clock_generator:clock_generator_1|start_counter[4]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.053      ;
; 0.902 ; clock_generator:clock_generator_1|start_counter[22] ; clock_generator:clock_generator_1|start_counter[25] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.054      ;
; 0.905 ; clock_generator:clock_generator_1|start_counter[6]  ; clock_generator:clock_generator_1|start_counter[9]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.057      ;
; 0.906 ; clock_generator:clock_generator_1|start_counter[8]  ; clock_generator:clock_generator_1|start_counter[11] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.058      ;
; 0.906 ; clock_generator:clock_generator_1|start_counter[21] ; clock_generator:clock_generator_1|start_counter[24] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.058      ;
; 0.910 ; clock_generator:clock_generator_1|start_counter[14] ; clock_generator:clock_generator_1|start_counter[17] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.062      ;
; 0.913 ; clock_generator:clock_generator_1|start_counter[15] ; clock_generator:clock_generator_1|start_counter[18] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.065      ;
; 0.913 ; clock_generator:clock_generator_1|start_counter[0]  ; clock_generator:clock_generator_1|start_counter[2]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.065      ;
; 0.915 ; clock_generator:clock_generator_1|start_counter[2]  ; clock_generator:clock_generator_1|start_counter[7]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.067      ;
; 0.915 ; clock_generator:clock_generator_1|start_counter[16] ; clock_generator:clock_generator_1|start_counter[20] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.067      ;
; 0.918 ; clock_generator:clock_generator_1|start_counter[2]  ; clock_generator:clock_generator_1|start_counter[6]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.070      ;
; 0.922 ; clock_generator:clock_generator_1|start_counter[6]  ; clock_generator:clock_generator_1|start_counter[12] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.074      ;
; 0.923 ; clock_generator:clock_generator_1|start_counter[4]  ; clock_generator:clock_generator_1|start_counter[7]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.075      ;
; 0.924 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|start_counter[12] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.076      ;
; 0.925 ; clock_generator:clock_generator_1|start_counter[19] ; clock_generator:clock_generator_1|start_counter[21] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.077      ;
; 0.926 ; clock_generator:clock_generator_1|start_counter[4]  ; clock_generator:clock_generator_1|start_counter[6]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.078      ;
; 0.928 ; clock_generator:clock_generator_1|start_counter[13] ; clock_generator:clock_generator_1|start_counter[13] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.080      ;
; 0.928 ; clock_generator:clock_generator_1|start_counter[20] ; clock_generator:clock_generator_1|start_counter[22] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.080      ;
; 0.928 ; clock_generator:clock_generator_1|start_counter[5]  ; clock_generator:clock_generator_1|start_counter[9]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.080      ;
; 0.933 ; clock_generator:clock_generator_1|start_counter[12] ; clock_generator:clock_generator_1|start_counter[17] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; -0.003     ; 1.082      ;
; 0.936 ; clock_generator:clock_generator_1|start_counter[3]  ; clock_generator:clock_generator_1|start_counter[5]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.088      ;
; 0.939 ; clock_generator:clock_generator_1|start_counter[1]  ; clock_generator:clock_generator_1|start_counter[0]  ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.091      ;
; 0.940 ; clock_generator:clock_generator_1|start_counter[6]  ; clock_generator:clock_generator_1|start_counter[10] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.092      ;
; 0.942 ; clock_generator:clock_generator_1|start_counter[21] ; clock_generator:clock_generator_1|start_counter[25] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.094      ;
; 0.944 ; clock_generator:clock_generator_1|start_counter[15] ; clock_generator:clock_generator_1|start_counter[19] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.096      ;
; 0.945 ; clock_generator:clock_generator_1|start_counter[5]  ; clock_generator:clock_generator_1|start_counter[12] ; CLOCK_27     ; CLOCK_27    ; 0.000        ; 0.000      ; 1.097      ;
+-------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'clock_generator_1|pll_1|altpll_component|pll|clk[1]'                                                                                                                                                                                                                                               ;
+-------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                  ; To Node                                                                    ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; 0.215 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.367      ;
; 0.253 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.405      ;
; 0.361 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.513      ;
; 0.362 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.514      ;
; 0.362 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.514      ;
; 0.375 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.527      ;
; 0.377 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.529      ;
; 0.377 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.529      ;
; 0.378 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.530      ;
; 0.380 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.532      ;
; 0.382 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.534      ;
; 0.422 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.574      ;
; 0.480 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.632      ;
; 0.500 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.652      ;
; 0.500 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.652      ;
; 0.506 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.658      ;
; 0.517 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.669      ;
; 0.517 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.669      ;
; 0.534 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.686      ;
; 0.535 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.687      ;
; 0.543 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.695      ;
; 0.552 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.704      ;
; 0.552 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.704      ;
; 0.562 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.714      ;
; 0.564 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.716      ;
; 0.570 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.722      ;
; 0.587 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.739      ;
; 0.597 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.749      ;
; 0.601 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.753      ;
; 0.614 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.766      ;
; 0.622 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.774      ;
; 0.632 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.784      ;
; 0.635 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.787      ;
; 0.649 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.801      ;
; 0.663 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.815      ;
; 0.667 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.819      ;
; 0.670 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.822      ;
; 0.676 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.828      ;
; 0.684 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.836      ;
; 0.685 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.837      ;
; 0.698 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.850      ;
; 0.702 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.854      ;
; 0.705 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.857      ;
; 0.716 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.868      ;
; 0.719 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.871      ;
; 0.733 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.885      ;
; 0.740 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.892      ;
; 0.754 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.906      ;
; 0.768 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.920      ;
; 0.775 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.927      ;
; 0.790 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.942      ;
; 0.803 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.955      ;
; 0.807 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.959      ;
; 0.838 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.990      ;
; 0.840 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.006      ; 0.998      ;
; 0.850 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.006      ; 1.008      ;
; 0.857 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.009      ;
; 0.884 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.006      ; 1.042      ;
; 0.942 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.006      ; 1.100      ;
; 0.959 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.111      ;
; 0.978 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.130      ;
; 1.026 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.006      ; 1.184      ;
; 1.156 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.308      ;
; 1.178 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.006      ; 1.336      ;
; 1.252 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.006      ; 1.410      ;
; 1.300 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.006      ; 1.458      ;
; 1.319 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; 0.000        ; 0.006      ; 1.477      ;
+-------+----------------------------------------------------------------------------+----------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Hold: 'clock_generator_1|pll_2|altpll_component|pll|clk[1]'                                                                                                                                                                                                                                              ;
+-------+----------------------------------------------------------------------------+---------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                  ; To Node                                                                   ; Launch Clock                                        ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------------------------------+---------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+
; 0.215 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[1]                 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[1]                ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[2]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[2]             ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ende            ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ende           ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[0]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[0]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[2]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[2]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[1]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[1]             ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[0]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[0]             ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[3]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[3]             ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[3]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[3]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.367      ;
; 0.215 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.error           ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.error          ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.367      ;
; 0.250 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.startbedingung  ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n          ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.402      ;
; 0.259 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack             ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~en                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.411      ;
; 0.264 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack             ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[0]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.416      ;
; 0.306 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n           ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SCLK                      ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.458      ;
; 0.328 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stop_warten     ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stopbedingung  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.480      ;
; 0.340 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.anfangszustand  ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[1]                ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.492      ;
; 0.342 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[1]                 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stop_warten    ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.002      ; 0.496      ;
; 0.343 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n           ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.taktende       ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.495      ;
; 0.344 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten      ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten2    ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.496      ;
; 0.355 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.taktende        ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[2]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.016      ; 0.523      ;
; 0.364 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.anfangszustand  ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.startbedingung ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.516      ;
; 0.368 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[3]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ende           ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.520      ;
; 0.371 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stopbedingung   ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[1]             ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.523      ;
; 0.371 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stopbedingung   ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[0]             ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.523      ;
; 0.375 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.startbedingung  ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[0]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.527      ;
; 0.376 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack             ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[1]                ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.528      ;
; 0.377 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten      ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~en                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.529      ;
; 0.387 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten2     ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~en                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.539      ;
; 0.400 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.taktende        ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n          ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.552      ;
; 0.424 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten2     ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack            ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.576      ;
; 0.433 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack             ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SCLK                      ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.585      ;
; 0.441 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.error           ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SCLK                      ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.002     ; 0.591      ;
; 0.458 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[0]                 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[1]                ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.610      ;
; 0.463 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[2]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[3]             ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.615      ;
; 0.463 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack             ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.error          ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.002      ; 0.617      ;
; 0.464 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stop_warten     ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SCLK                      ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.002     ; 0.614      ;
; 0.465 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack             ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stop_warten    ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.002      ; 0.619      ;
; 0.466 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.taktende        ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[0]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.618      ;
; 0.474 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.taktende        ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[3]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.626      ;
; 0.475 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.anfangszustand  ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[0]                ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.627      ;
; 0.506 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[0]                 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[0]                ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.658      ;
; 0.510 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[2]             ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.054     ; 0.608      ;
; 0.510 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ende           ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.054     ; 0.608      ;
; 0.510 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[3]             ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.054     ; 0.608      ;
; 0.544 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten      ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SCLK                      ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.696      ;
; 0.549 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n           ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.701      ;
; 0.558 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[0]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[1]             ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.710      ;
; 0.561 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.error          ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.056     ; 0.657      ;
; 0.563 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[1]             ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.056     ; 0.659      ;
; 0.563 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[0]             ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.056     ; 0.659      ;
; 0.589 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[0]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[2]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.016      ; 0.757      ;
; 0.592 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[0]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n          ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.744      ;
; 0.616 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[0]                 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stop_warten    ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.002      ; 0.770      ;
; 0.617 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[1]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[2]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.769      ;
; 0.631 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ende            ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.004     ; 0.779      ;
; 0.635 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack             ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[0]                ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.787      ;
; 0.639 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.taktende        ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.791      ;
; 0.654 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[0]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[2]             ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.002      ; 0.808      ;
; 0.655 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[0]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[3]             ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.002      ; 0.809      ;
; 0.663 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.058     ; 0.757      ;
; 0.663 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~en                   ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.058     ; 0.757      ;
; 0.663 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.anfangszustand ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.058     ; 0.757      ;
; 0.663 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.startbedingung ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.058     ; 0.757      ;
; 0.663 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n          ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.058     ; 0.757      ;
; 0.663 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.taktende       ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.058     ; 0.757      ;
; 0.663 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten     ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.058     ; 0.757      ;
; 0.663 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten2    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.058     ; 0.757      ;
; 0.663 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack            ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.058     ; 0.757      ;
; 0.663 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SCLK                      ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.058     ; 0.757      ;
; 0.673 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stopbedingung   ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[2]             ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.002      ; 0.827      ;
; 0.674 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stopbedingung   ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[3]             ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.002      ; 0.828      ;
; 0.681 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[3]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.anfangszustand ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.004     ; 0.829      ;
; 0.686 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stopbedingung   ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ende           ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.002      ; 0.840      ;
; 0.703 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[3]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.004     ; 0.851      ;
; 0.705 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stopbedingung   ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.anfangszustand ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.002     ; 0.855      ;
; 0.726 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[1]                   ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.042     ; 0.836      ;
; 0.726 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[2]                   ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.042     ; 0.836      ;
; 0.726 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[1]                 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n          ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.878      ;
; 0.727 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack             ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[3]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.879      ;
; 0.734 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[1]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[3]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.016     ; 0.870      ;
; 0.734 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[2]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.anfangszustand ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.004     ; 0.882      ;
; 0.742 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[3]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n          ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.894      ;
; 0.757 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[2]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ende           ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.909      ;
; 0.758 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[2]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.016     ; 0.894      ;
; 0.758 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[1]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n          ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.016     ; 0.894      ;
; 0.764 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[1]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[2]             ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.002      ; 0.918      ;
; 0.765 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stop_warten    ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.056     ; 0.861      ;
; 0.765 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stopbedingung  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.056     ; 0.861      ;
; 0.765 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[1]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[3]             ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.002      ; 0.919      ;
; 0.769 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[0]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[3]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.921      ;
; 0.775 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.anfangszustand  ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.927      ;
; 0.778 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[2]              ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.004     ; 0.926      ;
; 0.811 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[3]                    ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.963      ;
; 0.815 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[0]                ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.058     ; 0.909      ;
; 0.815 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[1]                ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.058     ; 0.909      ;
; 0.815 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[0]                   ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.058     ; 0.909      ;
; 0.815 ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[3]                   ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; -0.058     ; 0.909      ;
; 0.824 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.taktende        ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.976      ;
; 0.838 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.startbedingung  ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[3]                   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 0.990      ;
; 0.849 ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack             ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n          ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 0.000        ; 0.000      ; 1.001      ;
+-------+----------------------------------------------------------------------------+---------------------------------------------------------------------------+-----------------------------------------------------+-----------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Recovery: 'clock_generator_1|pll_2|altpll_component|pll|clk[1]'                                                                                                                                                                ;
+-------+-----------------------------------------+---------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                               ; To Node                                                                   ; Launch Clock ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------+---------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
; 5.604 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[1]             ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -1.638     ; 2.049      ;
; 5.604 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stop_warten    ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -1.638     ; 2.049      ;
; 5.604 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stopbedingung  ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -1.638     ; 2.049      ;
; 5.604 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[0]             ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -1.638     ; 2.049      ;
; 5.604 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.error          ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -1.638     ; 2.049      ;
; 5.608 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -1.640     ; 2.043      ;
; 5.608 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~en                   ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -1.640     ; 2.043      ;
; 5.608 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.anfangszustand ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -1.640     ; 2.043      ;
; 5.608 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.startbedingung ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -1.640     ; 2.043      ;
; 5.608 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n          ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -1.640     ; 2.043      ;
; 5.608 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.taktende       ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -1.640     ; 2.043      ;
; 5.608 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten     ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -1.640     ; 2.043      ;
; 5.608 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten2    ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -1.640     ; 2.043      ;
; 5.608 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack            ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -1.640     ; 2.043      ;
; 5.608 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SCLK                      ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -1.640     ; 2.043      ;
; 5.609 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[2]             ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -1.636     ; 2.046      ;
; 5.609 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ende           ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -1.636     ; 2.046      ;
; 5.609 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[3]             ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 9.259        ; -1.636     ; 2.046      ;
+-------+-----------------------------------------+---------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Removal: 'clock_generator_1|pll_2|altpll_component|pll|clk[1]'                                                                                                                                                                 ;
+-------+-----------------------------------------+---------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                               ; To Node                                                                   ; Launch Clock ; Latch Clock                                         ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------+---------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+
; 3.531 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[2]             ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; -0.001       ; -1.636     ; 2.046      ;
; 3.531 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ende           ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; -0.001       ; -1.636     ; 2.046      ;
; 3.531 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[3]             ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; -0.001       ; -1.636     ; 2.046      ;
; 3.532 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; -0.001       ; -1.640     ; 2.043      ;
; 3.532 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~en                   ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; -0.001       ; -1.640     ; 2.043      ;
; 3.532 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.anfangszustand ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; -0.001       ; -1.640     ; 2.043      ;
; 3.532 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.startbedingung ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; -0.001       ; -1.640     ; 2.043      ;
; 3.532 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n          ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; -0.001       ; -1.640     ; 2.043      ;
; 3.532 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.taktende       ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; -0.001       ; -1.640     ; 2.043      ;
; 3.532 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten     ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; -0.001       ; -1.640     ; 2.043      ;
; 3.532 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten2    ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; -0.001       ; -1.640     ; 2.043      ;
; 3.532 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack            ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; -0.001       ; -1.640     ; 2.043      ;
; 3.532 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SCLK                      ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; -0.001       ; -1.640     ; 2.043      ;
; 3.536 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[1]             ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; -0.001       ; -1.638     ; 2.049      ;
; 3.536 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stop_warten    ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; -0.001       ; -1.638     ; 2.049      ;
; 3.536 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stopbedingung  ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; -0.001       ; -1.638     ; 2.049      ;
; 3.536 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[0]             ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; -0.001       ; -1.638     ; 2.049      ;
; 3.536 ; clock_generator:clock_generator_1|reset ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.error          ; CLOCK_27     ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; -0.001       ; -1.638     ; 2.049      ;
+-------+-----------------------------------------+---------------------------------------------------------------------------+--------------+-----------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'AUD_BCLK'                                                                                                                               ;
+--------+--------------+----------------+------------------+----------+------------+--------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                               ;
+--------+--------------+----------------+------------------+----------+------------+--------------------------------------------------------------------------------------+
; -1.222 ; 1.000        ; 2.222          ; Port Rate        ; AUD_BCLK ; Rise       ; AUD_BCLK                                                                             ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[0]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[0]  ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[1]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[1]  ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[2]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[2]  ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[3]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[3]  ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[4]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[4]  ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[0] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[0] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[1] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[2] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[2] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[3] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[3] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[4] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[4] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[0]          ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[0]          ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[10]         ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[10]         ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[11]         ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[11]         ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[12]         ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[12]         ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[13]         ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[13]         ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[14]         ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[14]         ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[15]         ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[15]         ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[16]         ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[16]         ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[17]         ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[17]         ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[18]         ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[18]         ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[19]         ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[19]         ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[1]          ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[1]          ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[20]         ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[20]         ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[21]         ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[21]         ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[22]         ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[22]         ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[23]         ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[23]         ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[2]          ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[2]          ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[3]          ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[3]          ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[4]          ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[4]          ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[5]          ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[5]          ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[6]          ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[6]          ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[7]          ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[7]          ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[8]          ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[8]          ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[9]          ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[9]          ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[0]            ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[0]            ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[10]           ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[10]           ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[11]           ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[11]           ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[12]           ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[12]           ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[13]           ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[13]           ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[14]           ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[14]           ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[15]           ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[15]           ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[16]           ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[16]           ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[17]           ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[17]           ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[18]           ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[18]           ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[19]           ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[19]           ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[1]            ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[1]            ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[20]           ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[20]           ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[21]           ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[21]           ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[22]           ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[22]           ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; AUD_BCLK ; Rise       ; audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|dl[23]           ;
+--------+--------------+----------------+------------------+----------+------------+--------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql'                                                                                                                        ;
+--------+--------------+----------------+------------------+--------------------------------------------------------+------------+-------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                  ; Clock Edge ; Target                                                                        ;
+--------+--------------+----------------+------------------+--------------------------------------------------------+------------+-------------------------------------------------------------------------------+
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[0]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[0]  ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[10] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[10] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[11] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[11] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[12] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[12] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[13] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[13] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[14] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[14] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[15] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[15] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[16] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[16] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[17] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[17] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[18] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[18] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[19] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[19] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[1]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[1]  ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[20] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[20] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[21] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[21] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[22] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[22] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[23] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[23] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[2]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[2]  ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[3]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[3]  ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[4]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[4]  ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[5]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[5]  ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[6]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[6]  ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[7]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[7]  ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[8]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[8]  ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[9]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idl[9]  ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[0]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[0]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[10]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[10]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[11]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[11]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[12]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[12]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[13]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[13]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[14]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[14]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[15]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[15]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[16]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[16]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[17]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[17]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[18]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[18]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[19]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[19]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[1]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[1]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[20]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[20]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[21]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[21]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[22]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[22]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[23]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[23]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[2]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[2]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[3]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[3]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[4]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[4]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[5]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[5]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[6]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[6]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[7]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[7]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[8]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[8]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[9]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|audio_output_register_1|idl[9]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|filter_unit_1|enql|regout                                        ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|filter_unit_1|enql|regout                                        ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|filter_unit_1|enql~clkctrl|inclk[0]                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; Rise       ; audio_unit_1|filter_unit_1|enql~clkctrl|inclk[0]                              ;
+--------+--------------+----------------+------------------+--------------------------------------------------------+------------+-------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr'                                                                                                                        ;
+--------+--------------+----------------+------------------+--------------------------------------------------------+------------+-------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                  ; Clock Edge ; Target                                                                        ;
+--------+--------------+----------------+------------------+--------------------------------------------------------+------------+-------------------------------------------------------------------------------+
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[0]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[0]  ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[10] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[10] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[11] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[11] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[12] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[12] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[13] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[13] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[14] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[14] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[15] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[15] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[16] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[16] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[17] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[17] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[18] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[18] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[19] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[19] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[1]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[1]  ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[20] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[20] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[21] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[21] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[22] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[22] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[23] ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[23] ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[2]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[2]  ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[3]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[3]  ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[4]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[4]  ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[5]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[5]  ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[6]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[6]  ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[7]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[7]  ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[8]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[8]  ;
; -0.500 ; 0.500        ; 1.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[9]  ;
; -0.500 ; 0.500        ; 1.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|idr[9]  ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[0]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[0]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[10]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[10]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[11]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[11]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[12]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[12]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[13]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[13]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[14]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[14]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[15]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[15]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[16]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[16]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[17]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[17]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[18]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[18]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[19]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[19]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[1]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[1]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[20]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[20]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[21]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[21]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[22]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[22]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[23]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[23]|clk                              ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[2]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[2]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[3]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[3]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[4]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[4]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[5]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[5]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[6]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[6]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[7]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[7]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[8]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[8]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[9]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|audio_output_register_1|idr[9]|clk                               ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|filter_unit_1|enqr|regout                                        ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|filter_unit_1|enqr|regout                                        ;
; 0.500  ; 0.500        ; 0.000          ; High Pulse Width ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|filter_unit_1|enqr~clkctrl|inclk[0]                              ;
; 0.500  ; 0.500        ; 0.000          ; Low Pulse Width  ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; Rise       ; audio_unit_1|filter_unit_1|enqr~clkctrl|inclk[0]                              ;
+--------+--------------+----------------+------------------+--------------------------------------------------------+------------+-------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'clock_generator_1|pll_1|altpll_component|pll|clk[0]'                                                                                                                                                                ;
+-------+--------------+----------------+------------------+-----------------------------------------------------+------------+------------------------------------------------------------------------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                               ; Clock Edge ; Target                                                                                                                 ;
+-------+--------------+----------------+------------------+-----------------------------------------------------+------------+------------------------------------------------------------------------------------------------------------------------+
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_a[54]              ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_a[54]              ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_a[54]~_Duplicate_1 ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_a[54]~_Duplicate_1 ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_a[54]~_Duplicate_2 ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_a[54]~_Duplicate_2 ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_a[55]              ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_a[55]              ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_a[55]~_Duplicate_1 ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_a[55]~_Duplicate_1 ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_a[55]~_Duplicate_2 ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_a[55]~_Duplicate_2 ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_a[56]              ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_a[56]              ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_a[56]~_Duplicate_1 ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_a[56]~_Duplicate_1 ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_a[56]~_Duplicate_2 ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_a[56]~_Duplicate_2 ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[18]              ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[18]              ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[18]~_Duplicate_1 ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[18]~_Duplicate_1 ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[18]~_Duplicate_2 ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[18]~_Duplicate_2 ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[18]~_Duplicate_3 ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[18]~_Duplicate_3 ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[19]              ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[19]              ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[19]~_Duplicate_1 ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[19]~_Duplicate_1 ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[19]~_Duplicate_2 ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[19]~_Duplicate_2 ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[19]~_Duplicate_3 ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[19]~_Duplicate_3 ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[20]              ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[20]              ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[20]~_Duplicate_1 ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[20]~_Duplicate_1 ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[20]~_Duplicate_2 ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[20]~_Duplicate_2 ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[20]~_Duplicate_3 ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[20]~_Duplicate_3 ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[21]              ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[21]              ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[21]~_Duplicate_1 ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[21]~_Duplicate_1 ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[21]~_Duplicate_2 ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[21]~_Duplicate_2 ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[21]~_Duplicate_3 ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[21]~_Duplicate_3 ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[22]              ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[22]              ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[22]~_Duplicate_1 ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[22]~_Duplicate_1 ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[22]~_Duplicate_2 ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[22]~_Duplicate_2 ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[22]~_Duplicate_3 ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[22]~_Duplicate_3 ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[23]              ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[23]              ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[23]~_Duplicate_1 ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[23]~_Duplicate_1 ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[23]~_Duplicate_2 ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[23]~_Duplicate_2 ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[23]~_Duplicate_3 ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[23]~_Duplicate_3 ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[24]              ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[24]              ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[24]~_Duplicate_1 ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[24]~_Duplicate_1 ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[24]~_Duplicate_2 ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[24]~_Duplicate_2 ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[24]~_Duplicate_3 ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[24]~_Duplicate_3 ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[25]              ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[25]              ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[25]~_Duplicate_1 ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[25]~_Duplicate_1 ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[25]~_Duplicate_2 ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[25]~_Duplicate_2 ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[25]~_Duplicate_3 ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[25]~_Duplicate_3 ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[26]              ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[26]              ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[26]~_Duplicate_1 ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[26]~_Duplicate_1 ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[26]~_Duplicate_2 ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[26]~_Duplicate_2 ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[26]~_Duplicate_3 ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[26]~_Duplicate_3 ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[27]              ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[27]              ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[27]~_Duplicate_1 ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[27]~_Duplicate_1 ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[27]~_Duplicate_2 ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[27]~_Duplicate_2 ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[27]~_Duplicate_3 ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[27]~_Duplicate_3 ;
; 7.981 ; 10.000       ; 2.019          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[28]              ;
; 7.981 ; 10.000       ; 2.019          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ; Rise       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[28]              ;
+-------+--------------+----------------+------------------+-----------------------------------------------------+------------+------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'CLOCK_50'                                                                                                ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------------------+
; 10.000 ; 10.000       ; 0.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; CLOCK_50|combout                                      ;
; 10.000 ; 10.000       ; 0.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; CLOCK_50|combout                                      ;
; 10.000 ; 10.000       ; 0.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0]   ;
; 10.000 ; 10.000       ; 0.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0]   ;
; 10.000 ; 10.000       ; 0.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[1]   ;
; 10.000 ; 10.000       ; 0.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[1]   ;
; 10.000 ; 10.000       ; 0.000          ; High Pulse Width ; CLOCK_50 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|inclk[0] ;
; 10.000 ; 10.000       ; 0.000          ; Low Pulse Width  ; CLOCK_50 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|inclk[0] ;
; 17.620 ; 20.000       ; 2.380          ; Port Rate        ; CLOCK_50 ; Rise       ; CLOCK_50                                              ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'CLOCK_27'                                                                                                ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------------------+
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|reset               ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[0]    ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[10]   ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[11]   ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[12]   ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[13]   ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[14]   ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[15]   ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[16]   ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[17]   ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[18]   ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[19]   ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[1]    ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[20]   ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[21]   ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[22]   ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[23]   ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[24]   ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[25]   ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[2]    ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[3]    ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[4]    ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[5]    ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[6]    ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[7]    ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[8]    ;
; 17.518 ; 18.518       ; 1.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[9]    ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|reset               ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[0]    ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[10]   ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[11]   ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[12]   ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[13]   ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[14]   ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[15]   ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[16]   ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[17]   ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[18]   ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[19]   ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[1]    ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[20]   ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[21]   ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[22]   ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[23]   ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[24]   ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[25]   ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[2]    ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[3]    ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[4]    ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[5]    ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[6]    ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[7]    ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[8]    ;
; 17.519 ; 18.519       ; 1.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator:clock_generator_1|start_counter[9]    ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; CLOCK_27|combout                                      ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; CLOCK_27~clkctrl|inclk[0]                             ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; CLOCK_27~clkctrl|outclk                               ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|pll_2|altpll_component|pll|clk[1]   ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|pll_2|altpll_component|pll|inclk[0] ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|reset|clk                           ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[0]|clk                ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[10]|clk               ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[11]|clk               ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[12]|clk               ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[13]|clk               ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[14]|clk               ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[15]|clk               ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[16]|clk               ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[17]|clk               ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[18]|clk               ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[19]|clk               ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[1]|clk                ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[20]|clk               ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[21]|clk               ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[22]|clk               ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[23]|clk               ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[24]|clk               ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[25]|clk               ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[2]|clk                ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[3]|clk                ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[4]|clk                ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[5]|clk                ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[6]|clk                ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[7]|clk                ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[8]|clk                ;
; 18.518 ; 18.518       ; 0.000          ; High Pulse Width ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[9]|clk                ;
; 18.519 ; 18.519       ; 0.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; CLOCK_27|combout                                      ;
; 18.519 ; 18.519       ; 0.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; CLOCK_27~clkctrl|inclk[0]                             ;
; 18.519 ; 18.519       ; 0.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; CLOCK_27~clkctrl|outclk                               ;
; 18.519 ; 18.519       ; 0.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator_1|pll_2|altpll_component|pll|clk[1]   ;
; 18.519 ; 18.519       ; 0.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator_1|pll_2|altpll_component|pll|inclk[0] ;
; 18.519 ; 18.519       ; 0.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator_1|reset|clk                           ;
; 18.519 ; 18.519       ; 0.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[0]|clk                ;
; 18.519 ; 18.519       ; 0.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[10]|clk               ;
; 18.519 ; 18.519       ; 0.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[11]|clk               ;
; 18.519 ; 18.519       ; 0.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[12]|clk               ;
; 18.519 ; 18.519       ; 0.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[13]|clk               ;
; 18.519 ; 18.519       ; 0.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[14]|clk               ;
; 18.519 ; 18.519       ; 0.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[15]|clk               ;
; 18.519 ; 18.519       ; 0.000          ; Low Pulse Width  ; CLOCK_27 ; Rise       ; clock_generator_1|start_counter[16]|clk               ;
+--------+--------------+----------------+------------------+----------+------------+-------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'clock_generator_1|pll_2|altpll_component|pll|clk[1]'                                                                                                                    ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                               ; Clock Edge ; Target                                                                    ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------+
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[0]             ;
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[1]             ;
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[2]             ;
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[3]             ;
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[0]                   ;
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[1]                   ;
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[2]                   ;
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[3]                   ;
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SCLK                      ;
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~en                   ;
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ;
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[0]                ;
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[1]                ;
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack            ;
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten     ;
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten2    ;
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.anfangszustand ;
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n          ;
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ende           ;
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.error          ;
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.startbedingung ;
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stop_warten    ;
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stopbedingung  ;
; 40.666 ; 41.666       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.taktende       ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[0]             ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[1]             ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[2]             ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Befehls_NR[3]             ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[0]                   ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[1]                   ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[2]                   ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[3]                   ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SCLK                      ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~en                   ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~reg0                 ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[0]                ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|Sektion[1]                ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack            ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten     ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ack_warten2    ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.anfangszustand ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.bit_n          ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.ende           ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.error          ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.startbedingung ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stop_warten    ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.stopbedingung  ;
; 40.667 ; 41.667       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate.taktende       ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|Befehls_NR[0]|clk                               ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|Befehls_NR[1]|clk                               ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|Befehls_NR[2]|clk                               ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|Befehls_NR[3]|clk                               ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|Byte[0]|clk                                     ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|Byte[1]|clk                                     ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|Byte[2]|clk                                     ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|Byte[3]|clk                                     ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|SCLK|clk                                        ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|SDIN~en|clk                                     ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|SDIN~reg0|clk                                   ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|Sektion[0]|clk                                  ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|Sektion[1]|clk                                  ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|reg_fstate.ack_warten2|clk                      ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|reg_fstate.ack_warten|clk                       ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|reg_fstate.ack|clk                              ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|reg_fstate.anfangszustand|clk                   ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|reg_fstate.bit_n|clk                            ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|reg_fstate.ende|clk                             ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|reg_fstate.error|clk                            ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|reg_fstate.startbedingung|clk                   ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|reg_fstate.stop_warten|clk                      ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|reg_fstate.stopbedingung|clk                    ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|reg_fstate.taktende|clk                         ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|pll_2|altpll_component|_clk1~clkctrl|inclk[0]           ;
; 41.666 ; 41.666       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|pll_2|altpll_component|_clk1~clkctrl|outclk             ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|Befehls_NR[0]|clk                               ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|Befehls_NR[1]|clk                               ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|Befehls_NR[2]|clk                               ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|Befehls_NR[3]|clk                               ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|Byte[0]|clk                                     ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|Byte[1]|clk                                     ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|Byte[2]|clk                                     ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|Byte[3]|clk                                     ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|SCLK|clk                                        ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|SDIN~en|clk                                     ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|SDIN~reg0|clk                                   ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|Sektion[0]|clk                                  ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|Sektion[1]|clk                                  ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|reg_fstate.ack_warten2|clk                      ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|reg_fstate.ack_warten|clk                       ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|reg_fstate.ack|clk                              ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|reg_fstate.anfangszustand|clk                   ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|reg_fstate.bit_n|clk                            ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|reg_fstate.ende|clk                             ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|reg_fstate.error|clk                            ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|reg_fstate.startbedingung|clk                   ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|reg_fstate.stop_warten|clk                      ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|reg_fstate.stopbedingung|clk                    ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; audio_unit_1|i2c_master_1|reg_fstate.taktende|clk                         ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|pll_2|altpll_component|_clk1~clkctrl|inclk[0]           ;
; 41.667 ; 41.667       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|pll_2|altpll_component|_clk1~clkctrl|outclk             ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+---------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Model Minimum Pulse Width: 'clock_generator_1|pll_1|altpll_component|pll|clk[1]'                                                                                                                     ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+----------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                               ; Clock Edge ; Target                                                                     ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+----------------------------------------------------------------------------+
; 49.000 ; 50.000       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ;
; 49.000 ; 50.000       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[0]    ;
; 49.000 ; 50.000       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ;
; 49.000 ; 50.000       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[1]    ;
; 49.000 ; 50.000       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ;
; 49.000 ; 50.000       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[2]    ;
; 49.000 ; 50.000       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ;
; 49.000 ; 50.000       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[3]    ;
; 49.000 ; 50.000       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ;
; 49.000 ; 50.000       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[4]    ;
; 49.000 ; 50.000       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ;
; 49.000 ; 50.000       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[5]    ;
; 49.000 ; 50.000       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ;
; 49.000 ; 50.000       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[6]    ;
; 49.000 ; 50.000       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ;
; 49.000 ; 50.000       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[7]    ;
; 49.000 ; 50.000       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ;
; 49.000 ; 50.000       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|c400[8]    ;
; 49.000 ; 50.000       ; 1.000          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ;
; 49.000 ; 50.000       ; 1.000          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator:clock_generator_1|clock_divider:clock_divider_1|clk_400kHz ;
; 50.000 ; 50.000       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|clock_divider_1|c400[0]|clk                              ;
; 50.000 ; 50.000       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|clock_divider_1|c400[0]|clk                              ;
; 50.000 ; 50.000       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|clock_divider_1|c400[1]|clk                              ;
; 50.000 ; 50.000       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|clock_divider_1|c400[1]|clk                              ;
; 50.000 ; 50.000       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|clock_divider_1|c400[2]|clk                              ;
; 50.000 ; 50.000       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|clock_divider_1|c400[2]|clk                              ;
; 50.000 ; 50.000       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|clock_divider_1|c400[3]|clk                              ;
; 50.000 ; 50.000       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|clock_divider_1|c400[3]|clk                              ;
; 50.000 ; 50.000       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|clock_divider_1|c400[4]|clk                              ;
; 50.000 ; 50.000       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|clock_divider_1|c400[4]|clk                              ;
; 50.000 ; 50.000       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|clock_divider_1|c400[5]|clk                              ;
; 50.000 ; 50.000       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|clock_divider_1|c400[5]|clk                              ;
; 50.000 ; 50.000       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|clock_divider_1|c400[6]|clk                              ;
; 50.000 ; 50.000       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|clock_divider_1|c400[6]|clk                              ;
; 50.000 ; 50.000       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|clock_divider_1|c400[7]|clk                              ;
; 50.000 ; 50.000       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|clock_divider_1|c400[7]|clk                              ;
; 50.000 ; 50.000       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|clock_divider_1|c400[8]|clk                              ;
; 50.000 ; 50.000       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|clock_divider_1|c400[8]|clk                              ;
; 50.000 ; 50.000       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|clock_divider_1|clk_400kHz|clk                           ;
; 50.000 ; 50.000       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|clock_divider_1|clk_400kHz|clk                           ;
; 50.000 ; 50.000       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|pll_1|altpll_component|_clk1~clkctrl|inclk[0]            ;
; 50.000 ; 50.000       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|pll_1|altpll_component|_clk1~clkctrl|inclk[0]            ;
; 50.000 ; 50.000       ; 0.000          ; High Pulse Width ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|pll_1|altpll_component|_clk1~clkctrl|outclk              ;
; 50.000 ; 50.000       ; 0.000          ; Low Pulse Width  ; clock_generator_1|pll_1|altpll_component|pll|clk[1] ; Rise       ; clock_generator_1|pll_1|altpll_component|_clk1~clkctrl|outclk              ;
+--------+--------------+----------------+------------------+-----------------------------------------------------+------------+----------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                 ;
+-------------+------------+-------+-------+------------+-----------------------------------------------------+
; Data Port   ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
+-------------+------------+-------+-------+------------+-----------------------------------------------------+
; AUD_ADCDAT  ; AUD_BCLK   ; 2.400 ; 2.400 ; Rise       ; AUD_BCLK                                            ;
; AUD_ADCLRCK ; AUD_BCLK   ; 2.946 ; 2.946 ; Rise       ; AUD_BCLK                                            ;
; AUD_DACLRCK ; AUD_BCLK   ; 2.899 ; 2.899 ; Fall       ; AUD_BCLK                                            ;
; SW[*]       ; CLOCK_27   ; 2.224 ; 2.224 ; Rise       ; CLOCK_27                                            ;
;  SW[17]     ; CLOCK_27   ; 2.224 ; 2.224 ; Rise       ; CLOCK_27                                            ;
; KEY[*]      ; CLOCK_50   ; 5.802 ; 5.802 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  KEY[0]     ; CLOCK_50   ; 5.802 ; 5.802 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  KEY[1]     ; CLOCK_50   ; 5.641 ; 5.641 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  KEY[2]     ; CLOCK_50   ; 4.538 ; 4.538 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  KEY[3]     ; CLOCK_50   ; 4.682 ; 4.682 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; SW[*]       ; CLOCK_50   ; 3.100 ; 3.100 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  SW[2]      ; CLOCK_50   ; 2.016 ; 2.016 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  SW[3]      ; CLOCK_50   ; 3.100 ; 3.100 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; SW[*]       ; CLOCK_50   ; 1.905 ; 1.905 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  SW[1]      ; CLOCK_50   ; 1.905 ; 1.905 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; I2C_SDAT    ; CLOCK_27   ; 4.570 ; 4.570 ; Rise       ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ;
+-------------+------------+-------+-------+------------+-----------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                    ;
+-------------+------------+--------+--------+------------+-----------------------------------------------------+
; Data Port   ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
+-------------+------------+--------+--------+------------+-----------------------------------------------------+
; AUD_ADCDAT  ; AUD_BCLK   ; -1.782 ; -1.782 ; Rise       ; AUD_BCLK                                            ;
; AUD_ADCLRCK ; AUD_BCLK   ; -2.108 ; -2.108 ; Rise       ; AUD_BCLK                                            ;
; AUD_DACLRCK ; AUD_BCLK   ; -1.852 ; -1.852 ; Fall       ; AUD_BCLK                                            ;
; SW[*]       ; CLOCK_27   ; -1.973 ; -1.973 ; Rise       ; CLOCK_27                                            ;
;  SW[17]     ; CLOCK_27   ; -1.973 ; -1.973 ; Rise       ; CLOCK_27                                            ;
; KEY[*]      ; CLOCK_50   ; -3.336 ; -3.336 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  KEY[0]     ; CLOCK_50   ; -3.961 ; -3.961 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  KEY[1]     ; CLOCK_50   ; -3.623 ; -3.623 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  KEY[2]     ; CLOCK_50   ; -3.336 ; -3.336 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  KEY[3]     ; CLOCK_50   ; -3.746 ; -3.746 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; SW[*]       ; CLOCK_50   ; -1.636 ; -1.636 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  SW[2]      ; CLOCK_50   ; -1.725 ; -1.725 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  SW[3]      ; CLOCK_50   ; -1.636 ; -1.636 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; SW[*]       ; CLOCK_50   ; -0.979 ; -0.979 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  SW[1]      ; CLOCK_50   ; -0.979 ; -0.979 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; I2C_SDAT    ; CLOCK_27   ; -4.065 ; -4.065 ; Rise       ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ;
+-------------+------------+--------+--------+------------+-----------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                        ;
+--------------+------------+-------+-------+------------+-----------------------------------------------------+
; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
+--------------+------------+-------+-------+------------+-----------------------------------------------------+
; AUD_DACDAT   ; AUD_BCLK   ; 4.139 ; 4.139 ; Fall       ; AUD_BCLK                                            ;
; LCD_DATA[*]  ; CLOCK_50   ; 3.860 ; 3.860 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[0] ; CLOCK_50   ; 3.456 ; 3.456 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[1] ; CLOCK_50   ; 3.824 ; 3.824 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[2] ; CLOCK_50   ; 2.877 ; 2.877 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[3] ; CLOCK_50   ; 3.751 ; 3.751 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[4] ; CLOCK_50   ; 2.924 ; 2.924 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[5] ; CLOCK_50   ; 3.860 ; 3.860 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[6] ; CLOCK_50   ; 2.860 ; 2.860 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[7] ; CLOCK_50   ; 3.008 ; 3.008 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; LCD_EN       ; CLOCK_50   ; 3.195 ; 3.195 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; LCD_RS       ; CLOCK_50   ; 2.842 ; 2.842 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; HEX0[*]      ; CLOCK_50   ; 2.193 ; 2.193 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX0[2]     ; CLOCK_50   ; 2.193 ; 2.193 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX0[3]     ; CLOCK_50   ; 2.093 ; 2.093 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX0[4]     ; CLOCK_50   ; 2.106 ; 2.106 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX0[5]     ; CLOCK_50   ; 2.083 ; 2.083 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX0[6]     ; CLOCK_50   ; 2.086 ; 2.086 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; HEX1[*]      ; CLOCK_50   ; 2.044 ; 2.044 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX1[1]     ; CLOCK_50   ; 2.044 ; 2.044 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX1[2]     ; CLOCK_50   ; 1.841 ; 1.841 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX1[3]     ; CLOCK_50   ; 1.864 ; 1.864 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX1[4]     ; CLOCK_50   ; 1.861 ; 1.861 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX1[6]     ; CLOCK_50   ; 1.997 ; 1.997 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; HEX2[*]      ; CLOCK_50   ; 2.489 ; 2.489 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX2[0]     ; CLOCK_50   ; 2.489 ; 2.489 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX2[1]     ; CLOCK_50   ; 2.440 ; 2.440 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX2[2]     ; CLOCK_50   ; 2.383 ; 2.383 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX2[3]     ; CLOCK_50   ; 2.460 ; 2.460 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX2[4]     ; CLOCK_50   ; 2.357 ; 2.357 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX2[5]     ; CLOCK_50   ; 2.366 ; 2.366 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX2[6]     ; CLOCK_50   ; 2.309 ; 2.309 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; HEX3[*]      ; CLOCK_50   ; 2.594 ; 2.594 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX3[0]     ; CLOCK_50   ; 2.448 ; 2.448 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX3[1]     ; CLOCK_50   ; 2.386 ; 2.386 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX3[2]     ; CLOCK_50   ; 2.371 ; 2.371 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX3[3]     ; CLOCK_50   ; 2.594 ; 2.594 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX3[4]     ; CLOCK_50   ; 2.366 ; 2.366 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX3[5]     ; CLOCK_50   ; 2.291 ; 2.291 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX3[6]     ; CLOCK_50   ; 2.331 ; 2.331 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; HEX4[*]      ; CLOCK_50   ; 2.668 ; 2.668 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX4[6]     ; CLOCK_50   ; 2.668 ; 2.668 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; HEX6[*]      ; CLOCK_50   ; 4.200 ; 4.200 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX6[0]     ; CLOCK_50   ; 3.016 ; 3.016 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX6[1]     ; CLOCK_50   ; 3.175 ; 3.175 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX6[2]     ; CLOCK_50   ; 3.250 ; 3.250 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX6[3]     ; CLOCK_50   ; 3.856 ; 3.856 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX6[4]     ; CLOCK_50   ; 3.200 ; 3.200 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX6[5]     ; CLOCK_50   ; 4.200 ; 4.200 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX6[6]     ; CLOCK_50   ; 3.036 ; 3.036 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; HEX7[*]      ; CLOCK_50   ; 3.856 ; 3.856 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX7[0]     ; CLOCK_50   ; 3.856 ; 3.856 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX7[1]     ; CLOCK_50   ; 3.217 ; 3.217 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX7[2]     ; CLOCK_50   ; 3.187 ; 3.187 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX7[3]     ; CLOCK_50   ; 3.826 ; 3.826 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX7[4]     ; CLOCK_50   ; 3.826 ; 3.826 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX7[5]     ; CLOCK_50   ; 3.847 ; 3.847 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; AUD_XCK      ; CLOCK_27   ; 1.463 ;       ; Rise       ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ;
; I2C_SCLK     ; CLOCK_27   ; 3.089 ; 3.089 ; Rise       ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ;
; I2C_SDAT     ; CLOCK_27   ; 3.146 ; 3.146 ; Rise       ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ;
; AUD_XCK      ; CLOCK_27   ;       ; 1.463 ; Fall       ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ;
+--------------+------------+-------+-------+------------+-----------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                ;
+--------------+------------+-------+-------+------------+-----------------------------------------------------+
; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
+--------------+------------+-------+-------+------------+-----------------------------------------------------+
; AUD_DACDAT   ; AUD_BCLK   ; 4.139 ; 4.139 ; Fall       ; AUD_BCLK                                            ;
; LCD_DATA[*]  ; CLOCK_50   ; 2.860 ; 2.860 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[0] ; CLOCK_50   ; 3.456 ; 3.456 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[1] ; CLOCK_50   ; 3.824 ; 3.824 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[2] ; CLOCK_50   ; 2.877 ; 2.877 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[3] ; CLOCK_50   ; 3.751 ; 3.751 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[4] ; CLOCK_50   ; 2.924 ; 2.924 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[5] ; CLOCK_50   ; 3.860 ; 3.860 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[6] ; CLOCK_50   ; 2.860 ; 2.860 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[7] ; CLOCK_50   ; 3.008 ; 3.008 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; LCD_EN       ; CLOCK_50   ; 3.195 ; 3.195 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; LCD_RS       ; CLOCK_50   ; 2.842 ; 2.842 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; HEX0[*]      ; CLOCK_50   ; 2.083 ; 2.083 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX0[2]     ; CLOCK_50   ; 2.193 ; 2.193 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX0[3]     ; CLOCK_50   ; 2.093 ; 2.093 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX0[4]     ; CLOCK_50   ; 2.106 ; 2.106 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX0[5]     ; CLOCK_50   ; 2.083 ; 2.083 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX0[6]     ; CLOCK_50   ; 2.086 ; 2.086 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; HEX1[*]      ; CLOCK_50   ; 1.841 ; 1.841 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX1[1]     ; CLOCK_50   ; 2.044 ; 2.044 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX1[2]     ; CLOCK_50   ; 1.841 ; 1.841 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX1[3]     ; CLOCK_50   ; 1.864 ; 1.864 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX1[4]     ; CLOCK_50   ; 1.861 ; 1.861 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX1[6]     ; CLOCK_50   ; 1.997 ; 1.997 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; HEX2[*]      ; CLOCK_50   ; 2.309 ; 2.309 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX2[0]     ; CLOCK_50   ; 2.489 ; 2.489 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX2[1]     ; CLOCK_50   ; 2.440 ; 2.440 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX2[2]     ; CLOCK_50   ; 2.383 ; 2.383 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX2[3]     ; CLOCK_50   ; 2.460 ; 2.460 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX2[4]     ; CLOCK_50   ; 2.357 ; 2.357 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX2[5]     ; CLOCK_50   ; 2.366 ; 2.366 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX2[6]     ; CLOCK_50   ; 2.309 ; 2.309 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; HEX3[*]      ; CLOCK_50   ; 2.291 ; 2.291 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX3[0]     ; CLOCK_50   ; 2.448 ; 2.448 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX3[1]     ; CLOCK_50   ; 2.386 ; 2.386 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX3[2]     ; CLOCK_50   ; 2.371 ; 2.371 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX3[3]     ; CLOCK_50   ; 2.594 ; 2.594 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX3[4]     ; CLOCK_50   ; 2.366 ; 2.366 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX3[5]     ; CLOCK_50   ; 2.291 ; 2.291 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX3[6]     ; CLOCK_50   ; 2.331 ; 2.331 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; HEX4[*]      ; CLOCK_50   ; 2.668 ; 2.668 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX4[6]     ; CLOCK_50   ; 2.668 ; 2.668 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; HEX6[*]      ; CLOCK_50   ; 3.016 ; 3.016 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX6[0]     ; CLOCK_50   ; 3.016 ; 3.016 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX6[1]     ; CLOCK_50   ; 3.175 ; 3.175 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX6[2]     ; CLOCK_50   ; 3.250 ; 3.250 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX6[3]     ; CLOCK_50   ; 3.856 ; 3.856 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX6[4]     ; CLOCK_50   ; 3.200 ; 3.200 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX6[5]     ; CLOCK_50   ; 4.200 ; 4.200 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX6[6]     ; CLOCK_50   ; 3.036 ; 3.036 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; HEX7[*]      ; CLOCK_50   ; 3.187 ; 3.187 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX7[0]     ; CLOCK_50   ; 3.856 ; 3.856 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX7[1]     ; CLOCK_50   ; 3.217 ; 3.217 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX7[2]     ; CLOCK_50   ; 3.187 ; 3.187 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX7[3]     ; CLOCK_50   ; 3.826 ; 3.826 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX7[4]     ; CLOCK_50   ; 3.826 ; 3.826 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX7[5]     ; CLOCK_50   ; 3.847 ; 3.847 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; AUD_XCK      ; CLOCK_27   ; 1.463 ;       ; Rise       ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ;
; I2C_SCLK     ; CLOCK_27   ; 3.089 ; 3.089 ; Rise       ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ;
; I2C_SDAT     ; CLOCK_27   ; 3.146 ; 3.146 ; Rise       ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ;
; AUD_XCK      ; CLOCK_27   ;       ; 1.463 ; Fall       ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ;
+--------------+------------+-------+-------+------------+-----------------------------------------------------+


+----------------------------------------------------+
; Propagation Delay                                  ;
+------------+-------------+----+-------+-------+----+
; Input Port ; Output Port ; RR ; RF    ; FR    ; FF ;
+------------+-------------+----+-------+-------+----+
; SW[0]      ; AUD_DACDAT  ;    ; 3.957 ; 3.957 ;    ;
+------------+-------------+----+-------+-------+----+


+----------------------------------------------------+
; Minimum Propagation Delay                          ;
+------------+-------------+----+-------+-------+----+
; Input Port ; Output Port ; RR ; RF    ; FR    ; FF ;
+------------+-------------+----+-------+-------+----+
; SW[0]      ; AUD_DACDAT  ;    ; 3.957 ; 3.957 ;    ;
+------------+-------------+----+-------+-------+----+


+----------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                      ;
+-----------+------------+-------+------+------------+-----------------------------------------------------+
; Data Port ; Clock Port ; Rise  ; Fall ; Clock Edge ; Clock Reference                                     ;
+-----------+------------+-------+------+------------+-----------------------------------------------------+
; I2C_SDAT  ; CLOCK_27   ; 3.076 ;      ; Rise       ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ;
+-----------+------------+-------+------+------------+-----------------------------------------------------+


+----------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                              ;
+-----------+------------+-------+------+------------+-----------------------------------------------------+
; Data Port ; Clock Port ; Rise  ; Fall ; Clock Edge ; Clock Reference                                     ;
+-----------+------------+-------+------+------------+-----------------------------------------------------+
; I2C_SDAT  ; CLOCK_27   ; 3.076 ;      ; Rise       ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ;
+-----------+------------+-------+------+------------+-----------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                              ;
+-----------+------------+-----------+-----------+------------+-----------------------------------------------------+
; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                     ;
+-----------+------------+-----------+-----------+------------+-----------------------------------------------------+
; I2C_SDAT  ; CLOCK_27   ; 3.076     ;           ; Rise       ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ;
+-----------+------------+-----------+-----------+------------+-----------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                      ;
+-----------+------------+-----------+-----------+------------+-----------------------------------------------------+
; Data Port ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                     ;
+-----------+------------+-----------+-----------+------------+-----------------------------------------------------+
; I2C_SDAT  ; CLOCK_27   ; 3.076     ;           ; Rise       ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ;
+-----------+------------+-----------+-----------+------------+-----------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                                                                      ;
+---------------------------------------------------------+-----------+---------+----------+---------+---------------------+
; Clock                                                   ; Setup     ; Hold    ; Recovery ; Removal ; Minimum Pulse Width ;
+---------------------------------------------------------+-----------+---------+----------+---------+---------------------+
; Worst-case Slack                                        ; -5.130    ; -1.407  ; 2.904    ; 3.531   ; -1.222              ;
;  AUD_BCLK                                               ; -1.962    ; 0.085   ; N/A      ; N/A     ; -1.222              ;
;  CLOCK_27                                               ; 30.205    ; 0.215   ; N/A      ; N/A     ; 17.518              ;
;  CLOCK_50                                               ; N/A       ; N/A     ; N/A      ; N/A     ; 10.000              ;
;  audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 1.567     ; -1.388  ; N/A      ; N/A     ; -0.500              ;
;  audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 1.558     ; -1.407  ; N/A      ; N/A     ; -0.500              ;
;  clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; -5.130    ; -0.166  ; N/A      ; N/A     ; 7.981               ;
;  clock_generator_1|pll_1|altpll_component|pll|clk[1]    ; 96.859    ; 0.215   ; N/A      ; N/A     ; 49.000              ;
;  clock_generator_1|pll_2|altpll_component|pll|clk[1]    ; -1.791    ; 0.215   ; 2.904    ; 3.531   ; 40.666              ;
; Design-wide TNS                                         ; -1355.793 ; -50.638 ; 0.0      ; 0.0     ; -190.222            ;
;  AUD_BCLK                                               ; -215.939  ; 0.000   ; N/A      ; N/A     ; -142.222            ;
;  CLOCK_27                                               ; 0.000     ; 0.000   ; N/A      ; N/A     ; 0.000               ;
;  CLOCK_50                                               ; N/A       ; N/A     ; N/A      ; N/A     ; 0.000               ;
;  audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 0.000     ; -26.503 ; N/A      ; N/A     ; -24.000             ;
;  audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 0.000     ; -23.818 ; N/A      ; N/A     ; -24.000             ;
;  clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; -1103.783 ; -0.317  ; N/A      ; N/A     ; 0.000               ;
;  clock_generator_1|pll_1|altpll_component|pll|clk[1]    ; 0.000     ; 0.000   ; N/A      ; N/A     ; 0.000               ;
;  clock_generator_1|pll_2|altpll_component|pll|clk[1]    ; -36.071   ; 0.000   ; 0.000    ; 0.000   ; 0.000               ;
+---------------------------------------------------------+-----------+---------+----------+---------+---------------------+


+---------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                   ;
+-------------+------------+--------+--------+------------+-----------------------------------------------------+
; Data Port   ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
+-------------+------------+--------+--------+------------+-----------------------------------------------------+
; AUD_ADCDAT  ; AUD_BCLK   ; 4.249  ; 4.249  ; Rise       ; AUD_BCLK                                            ;
; AUD_ADCLRCK ; AUD_BCLK   ; 5.330  ; 5.330  ; Rise       ; AUD_BCLK                                            ;
; AUD_DACLRCK ; AUD_BCLK   ; 5.137  ; 5.137  ; Fall       ; AUD_BCLK                                            ;
; SW[*]       ; CLOCK_27   ; 4.062  ; 4.062  ; Rise       ; CLOCK_27                                            ;
;  SW[17]     ; CLOCK_27   ; 4.062  ; 4.062  ; Rise       ; CLOCK_27                                            ;
; KEY[*]      ; CLOCK_50   ; 10.815 ; 10.815 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  KEY[0]     ; CLOCK_50   ; 10.815 ; 10.815 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  KEY[1]     ; CLOCK_50   ; 10.486 ; 10.486 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  KEY[2]     ; CLOCK_50   ; 8.165  ; 8.165  ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  KEY[3]     ; CLOCK_50   ; 8.449  ; 8.449  ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; SW[*]       ; CLOCK_50   ; 6.119  ; 6.119  ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  SW[2]      ; CLOCK_50   ; 3.688  ; 3.688  ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  SW[3]      ; CLOCK_50   ; 6.119  ; 6.119  ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; SW[*]       ; CLOCK_50   ; 3.638  ; 3.638  ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  SW[1]      ; CLOCK_50   ; 3.638  ; 3.638  ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; I2C_SDAT    ; CLOCK_27   ; 8.026  ; 8.026  ; Rise       ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ;
+-------------+------------+--------+--------+------------+-----------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                    ;
+-------------+------------+--------+--------+------------+-----------------------------------------------------+
; Data Port   ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                     ;
+-------------+------------+--------+--------+------------+-----------------------------------------------------+
; AUD_ADCDAT  ; AUD_BCLK   ; -1.782 ; -1.782 ; Rise       ; AUD_BCLK                                            ;
; AUD_ADCLRCK ; AUD_BCLK   ; -2.108 ; -2.108 ; Rise       ; AUD_BCLK                                            ;
; AUD_DACLRCK ; AUD_BCLK   ; -1.852 ; -1.852 ; Fall       ; AUD_BCLK                                            ;
; SW[*]       ; CLOCK_27   ; -1.973 ; -1.973 ; Rise       ; CLOCK_27                                            ;
;  SW[17]     ; CLOCK_27   ; -1.973 ; -1.973 ; Rise       ; CLOCK_27                                            ;
; KEY[*]      ; CLOCK_50   ; -3.336 ; -3.336 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  KEY[0]     ; CLOCK_50   ; -3.961 ; -3.961 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  KEY[1]     ; CLOCK_50   ; -3.623 ; -3.623 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  KEY[2]     ; CLOCK_50   ; -3.336 ; -3.336 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  KEY[3]     ; CLOCK_50   ; -3.746 ; -3.746 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; SW[*]       ; CLOCK_50   ; -1.636 ; -1.636 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  SW[2]      ; CLOCK_50   ; -1.725 ; -1.725 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  SW[3]      ; CLOCK_50   ; -1.636 ; -1.636 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; SW[*]       ; CLOCK_50   ; -0.979 ; -0.979 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  SW[1]      ; CLOCK_50   ; -0.979 ; -0.979 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; I2C_SDAT    ; CLOCK_27   ; -4.065 ; -4.065 ; Rise       ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ;
+-------------+------------+--------+--------+------------+-----------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                        ;
+--------------+------------+-------+-------+------------+-----------------------------------------------------+
; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
+--------------+------------+-------+-------+------------+-----------------------------------------------------+
; AUD_DACDAT   ; AUD_BCLK   ; 7.930 ; 7.930 ; Fall       ; AUD_BCLK                                            ;
; LCD_DATA[*]  ; CLOCK_50   ; 7.681 ; 7.681 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[0] ; CLOCK_50   ; 6.767 ; 6.767 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[1] ; CLOCK_50   ; 7.457 ; 7.457 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[2] ; CLOCK_50   ; 5.693 ; 5.693 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[3] ; CLOCK_50   ; 7.335 ; 7.335 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[4] ; CLOCK_50   ; 5.843 ; 5.843 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[5] ; CLOCK_50   ; 7.681 ; 7.681 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[6] ; CLOCK_50   ; 5.666 ; 5.666 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[7] ; CLOCK_50   ; 5.981 ; 5.981 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; LCD_EN       ; CLOCK_50   ; 6.409 ; 6.409 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; LCD_RS       ; CLOCK_50   ; 5.639 ; 5.639 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; HEX0[*]      ; CLOCK_50   ; 4.281 ; 4.281 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX0[2]     ; CLOCK_50   ; 4.281 ; 4.281 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX0[3]     ; CLOCK_50   ; 4.047 ; 4.047 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX0[4]     ; CLOCK_50   ; 4.072 ; 4.072 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX0[5]     ; CLOCK_50   ; 4.035 ; 4.035 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX0[6]     ; CLOCK_50   ; 4.045 ; 4.045 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; HEX1[*]      ; CLOCK_50   ; 3.993 ; 3.993 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX1[1]     ; CLOCK_50   ; 3.993 ; 3.993 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX1[2]     ; CLOCK_50   ; 3.650 ; 3.650 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX1[3]     ; CLOCK_50   ; 3.690 ; 3.690 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX1[4]     ; CLOCK_50   ; 3.670 ; 3.670 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX1[6]     ; CLOCK_50   ; 3.961 ; 3.961 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; HEX2[*]      ; CLOCK_50   ; 5.008 ; 5.008 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX2[0]     ; CLOCK_50   ; 5.008 ; 5.008 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX2[1]     ; CLOCK_50   ; 4.948 ; 4.948 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX2[2]     ; CLOCK_50   ; 4.759 ; 4.759 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX2[3]     ; CLOCK_50   ; 4.958 ; 4.958 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX2[4]     ; CLOCK_50   ; 4.724 ; 4.724 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX2[5]     ; CLOCK_50   ; 4.740 ; 4.740 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX2[6]     ; CLOCK_50   ; 4.578 ; 4.578 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; HEX3[*]      ; CLOCK_50   ; 5.261 ; 5.261 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX3[0]     ; CLOCK_50   ; 4.957 ; 4.957 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX3[1]     ; CLOCK_50   ; 4.772 ; 4.772 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX3[2]     ; CLOCK_50   ; 4.745 ; 4.745 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX3[3]     ; CLOCK_50   ; 5.261 ; 5.261 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX3[4]     ; CLOCK_50   ; 4.740 ; 4.740 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX3[5]     ; CLOCK_50   ; 4.638 ; 4.638 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX3[6]     ; CLOCK_50   ; 4.699 ; 4.699 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; HEX4[*]      ; CLOCK_50   ; 5.238 ; 5.238 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX4[6]     ; CLOCK_50   ; 5.238 ; 5.238 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; HEX6[*]      ; CLOCK_50   ; 8.301 ; 8.301 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX6[0]     ; CLOCK_50   ; 6.113 ; 6.113 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX6[1]     ; CLOCK_50   ; 6.187 ; 6.187 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX6[2]     ; CLOCK_50   ; 6.634 ; 6.634 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX6[3]     ; CLOCK_50   ; 7.719 ; 7.719 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX6[4]     ; CLOCK_50   ; 6.507 ; 6.507 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX6[5]     ; CLOCK_50   ; 8.301 ; 8.301 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX6[6]     ; CLOCK_50   ; 6.169 ; 6.169 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; HEX7[*]      ; CLOCK_50   ; 7.768 ; 7.768 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX7[0]     ; CLOCK_50   ; 7.768 ; 7.768 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX7[1]     ; CLOCK_50   ; 6.385 ; 6.385 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX7[2]     ; CLOCK_50   ; 6.355 ; 6.355 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX7[3]     ; CLOCK_50   ; 7.738 ; 7.738 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX7[4]     ; CLOCK_50   ; 7.738 ; 7.738 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX7[5]     ; CLOCK_50   ; 7.758 ; 7.758 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; AUD_XCK      ; CLOCK_27   ; 2.917 ;       ; Rise       ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ;
; I2C_SCLK     ; CLOCK_27   ; 6.103 ; 6.103 ; Rise       ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ;
; I2C_SDAT     ; CLOCK_27   ; 6.296 ; 6.296 ; Rise       ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ;
; AUD_XCK      ; CLOCK_27   ;       ; 2.917 ; Fall       ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ;
+--------------+------------+-------+-------+------------+-----------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                ;
+--------------+------------+-------+-------+------------+-----------------------------------------------------+
; Data Port    ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                     ;
+--------------+------------+-------+-------+------------+-----------------------------------------------------+
; AUD_DACDAT   ; AUD_BCLK   ; 4.139 ; 4.139 ; Fall       ; AUD_BCLK                                            ;
; LCD_DATA[*]  ; CLOCK_50   ; 2.860 ; 2.860 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[0] ; CLOCK_50   ; 3.456 ; 3.456 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[1] ; CLOCK_50   ; 3.824 ; 3.824 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[2] ; CLOCK_50   ; 2.877 ; 2.877 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[3] ; CLOCK_50   ; 3.751 ; 3.751 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[4] ; CLOCK_50   ; 2.924 ; 2.924 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[5] ; CLOCK_50   ; 3.860 ; 3.860 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[6] ; CLOCK_50   ; 2.860 ; 2.860 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  LCD_DATA[7] ; CLOCK_50   ; 3.008 ; 3.008 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; LCD_EN       ; CLOCK_50   ; 3.195 ; 3.195 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; LCD_RS       ; CLOCK_50   ; 2.842 ; 2.842 ; Rise       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; HEX0[*]      ; CLOCK_50   ; 2.083 ; 2.083 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX0[2]     ; CLOCK_50   ; 2.193 ; 2.193 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX0[3]     ; CLOCK_50   ; 2.093 ; 2.093 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX0[4]     ; CLOCK_50   ; 2.106 ; 2.106 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX0[5]     ; CLOCK_50   ; 2.083 ; 2.083 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX0[6]     ; CLOCK_50   ; 2.086 ; 2.086 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; HEX1[*]      ; CLOCK_50   ; 1.841 ; 1.841 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX1[1]     ; CLOCK_50   ; 2.044 ; 2.044 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX1[2]     ; CLOCK_50   ; 1.841 ; 1.841 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX1[3]     ; CLOCK_50   ; 1.864 ; 1.864 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX1[4]     ; CLOCK_50   ; 1.861 ; 1.861 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX1[6]     ; CLOCK_50   ; 1.997 ; 1.997 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; HEX2[*]      ; CLOCK_50   ; 2.309 ; 2.309 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX2[0]     ; CLOCK_50   ; 2.489 ; 2.489 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX2[1]     ; CLOCK_50   ; 2.440 ; 2.440 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX2[2]     ; CLOCK_50   ; 2.383 ; 2.383 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX2[3]     ; CLOCK_50   ; 2.460 ; 2.460 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX2[4]     ; CLOCK_50   ; 2.357 ; 2.357 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX2[5]     ; CLOCK_50   ; 2.366 ; 2.366 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX2[6]     ; CLOCK_50   ; 2.309 ; 2.309 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; HEX3[*]      ; CLOCK_50   ; 2.291 ; 2.291 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX3[0]     ; CLOCK_50   ; 2.448 ; 2.448 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX3[1]     ; CLOCK_50   ; 2.386 ; 2.386 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX3[2]     ; CLOCK_50   ; 2.371 ; 2.371 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX3[3]     ; CLOCK_50   ; 2.594 ; 2.594 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX3[4]     ; CLOCK_50   ; 2.366 ; 2.366 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX3[5]     ; CLOCK_50   ; 2.291 ; 2.291 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX3[6]     ; CLOCK_50   ; 2.331 ; 2.331 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; HEX4[*]      ; CLOCK_50   ; 2.668 ; 2.668 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX4[6]     ; CLOCK_50   ; 2.668 ; 2.668 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; HEX6[*]      ; CLOCK_50   ; 3.016 ; 3.016 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX6[0]     ; CLOCK_50   ; 3.016 ; 3.016 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX6[1]     ; CLOCK_50   ; 3.175 ; 3.175 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX6[2]     ; CLOCK_50   ; 3.250 ; 3.250 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX6[3]     ; CLOCK_50   ; 3.856 ; 3.856 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX6[4]     ; CLOCK_50   ; 3.200 ; 3.200 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX6[5]     ; CLOCK_50   ; 4.200 ; 4.200 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX6[6]     ; CLOCK_50   ; 3.036 ; 3.036 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; HEX7[*]      ; CLOCK_50   ; 3.187 ; 3.187 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX7[0]     ; CLOCK_50   ; 3.856 ; 3.856 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX7[1]     ; CLOCK_50   ; 3.217 ; 3.217 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX7[2]     ; CLOCK_50   ; 3.187 ; 3.187 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX7[3]     ; CLOCK_50   ; 3.826 ; 3.826 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX7[4]     ; CLOCK_50   ; 3.826 ; 3.826 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
;  HEX7[5]     ; CLOCK_50   ; 3.847 ; 3.847 ; Fall       ; clock_generator_1|pll_1|altpll_component|pll|clk[0] ;
; AUD_XCK      ; CLOCK_27   ; 1.463 ;       ; Rise       ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ;
; I2C_SCLK     ; CLOCK_27   ; 3.089 ; 3.089 ; Rise       ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ;
; I2C_SDAT     ; CLOCK_27   ; 3.146 ; 3.146 ; Rise       ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ;
; AUD_XCK      ; CLOCK_27   ;       ; 1.463 ; Fall       ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ;
+--------------+------------+-------+-------+------------+-----------------------------------------------------+


+----------------------------------------------------+
; Progagation Delay                                  ;
+------------+-------------+----+-------+-------+----+
; Input Port ; Output Port ; RR ; RF    ; FR    ; FF ;
+------------+-------------+----+-------+-------+----+
; SW[0]      ; AUD_DACDAT  ;    ; 7.501 ; 7.501 ;    ;
+------------+-------------+----+-------+-------+----+


+----------------------------------------------------+
; Minimum Progagation Delay                          ;
+------------+-------------+----+-------+-------+----+
; Input Port ; Output Port ; RR ; RF    ; FR    ; FF ;
+------------+-------------+----+-------+-------+----+
; SW[0]      ; AUD_DACDAT  ;    ; 3.957 ; 3.957 ;    ;
+------------+-------------+----+-------+-------+----+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Transfers                                                                                                                                                 ;
+--------------------------------------------------------+--------------------------------------------------------+--------------+----------+----------+----------+
; From Clock                                             ; To Clock                                               ; RR Paths     ; FR Paths ; RF Paths ; FF Paths ;
+--------------------------------------------------------+--------------------------------------------------------+--------------+----------+----------+----------+
; AUD_BCLK                                               ; AUD_BCLK                                               ; 1101         ; 0        ; 0        ; 516      ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; AUD_BCLK                                               ; 0            ; 0        ; 24       ; 0        ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; AUD_BCLK                                               ; 0            ; 0        ; 24       ; 0        ;
; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 24           ; 0        ; 0        ; 0        ;
; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 24           ; 0        ; 0        ; 0        ;
; CLOCK_27                                               ; CLOCK_27                                               ; 1053         ; 0        ; 0        ; 0        ;
; AUD_BCLK                                               ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; 72           ; 0        ; 0        ; 0        ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; 2            ; 2        ; 0        ; 0        ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; 1            ; 1        ; 0        ; 0        ;
; CLOCK_27                                               ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; 340          ; 0        ; 0        ; 0        ;
; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; > 2147483647 ; 26       ; 22749    ; 890      ;
; clock_generator_1|pll_1|altpll_component|pll|clk[1]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1]    ; 73           ; 0        ; 0        ; 0        ;
; CLOCK_27                                               ; clock_generator_1|pll_2|altpll_component|pll|clk[1]    ; 6            ; 0        ; 0        ; 0        ;
; clock_generator_1|pll_1|altpll_component|pll|clk[1]    ; clock_generator_1|pll_2|altpll_component|pll|clk[1]    ; 24           ; 0        ; 0        ; 0        ;
; clock_generator_1|pll_2|altpll_component|pll|clk[1]    ; clock_generator_1|pll_2|altpll_component|pll|clk[1]    ; 235          ; 0        ; 0        ; 0        ;
+--------------------------------------------------------+--------------------------------------------------------+--------------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Transfers                                                                                                                                                  ;
+--------------------------------------------------------+--------------------------------------------------------+--------------+----------+----------+----------+
; From Clock                                             ; To Clock                                               ; RR Paths     ; FR Paths ; RF Paths ; FF Paths ;
+--------------------------------------------------------+--------------------------------------------------------+--------------+----------+----------+----------+
; AUD_BCLK                                               ; AUD_BCLK                                               ; 1101         ; 0        ; 0        ; 516      ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; AUD_BCLK                                               ; 0            ; 0        ; 24       ; 0        ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; AUD_BCLK                                               ; 0            ; 0        ; 24       ; 0        ;
; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; 24           ; 0        ; 0        ; 0        ;
; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; 24           ; 0        ; 0        ; 0        ;
; CLOCK_27                                               ; CLOCK_27                                               ; 1053         ; 0        ; 0        ; 0        ;
; AUD_BCLK                                               ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; 72           ; 0        ; 0        ; 0        ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; 2            ; 2        ; 0        ; 0        ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; 1            ; 1        ; 0        ; 0        ;
; CLOCK_27                                               ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; 340          ; 0        ; 0        ; 0        ;
; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; clock_generator_1|pll_1|altpll_component|pll|clk[0]    ; > 2147483647 ; 26       ; 22749    ; 890      ;
; clock_generator_1|pll_1|altpll_component|pll|clk[1]    ; clock_generator_1|pll_1|altpll_component|pll|clk[1]    ; 73           ; 0        ; 0        ; 0        ;
; CLOCK_27                                               ; clock_generator_1|pll_2|altpll_component|pll|clk[1]    ; 6            ; 0        ; 0        ; 0        ;
; clock_generator_1|pll_1|altpll_component|pll|clk[1]    ; clock_generator_1|pll_2|altpll_component|pll|clk[1]    ; 24           ; 0        ; 0        ; 0        ;
; clock_generator_1|pll_2|altpll_component|pll|clk[1]    ; clock_generator_1|pll_2|altpll_component|pll|clk[1]    ; 235          ; 0        ; 0        ; 0        ;
+--------------------------------------------------------+--------------------------------------------------------+--------------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+--------------------------------------------------------------------------------------------------------------+
; Recovery Transfers                                                                                           ;
+------------+-----------------------------------------------------+----------+----------+----------+----------+
; From Clock ; To Clock                                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+-----------------------------------------------------+----------+----------+----------+----------+
; CLOCK_27   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 18       ; 0        ; 0        ; 0        ;
+------------+-----------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+--------------------------------------------------------------------------------------------------------------+
; Removal Transfers                                                                                            ;
+------------+-----------------------------------------------------+----------+----------+----------+----------+
; From Clock ; To Clock                                            ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+------------+-----------------------------------------------------+----------+----------+----------+----------+
; CLOCK_27   ; clock_generator_1|pll_2|altpll_component|pll|clk[1] ; 18       ; 0        ; 0        ; 0        ;
+------------+-----------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No dedicated SERDES Receiver circuitry present in device or used in design


+------------------------------------------------+
; Unconstrained Paths                            ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 0     ; 0    ;
; Unconstrained Input Ports       ; 13    ; 13   ;
; Unconstrained Input Port Paths  ; 607   ; 607  ;
; Unconstrained Output Ports      ; 52    ; 52   ;
; Unconstrained Output Port Paths ; 54    ; 54   ;
+---------------------------------+-------+------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
    Info: Version 13.0.0 Build 156 04/24/2013 SJ Web Edition
    Info: Processing started: Fri May 22 21:51:02 2015
Info: Command: quartus_sta Equalizer -c Equalizer
Info: qsta_default_script.tcl version: #1
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Critical Warning (332012): Synopsys Design Constraints File file not found: 'Equalizer.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
Info (332142): No user constrained generated clocks found in the design. Calling "derive_pll_clocks -create_base_clocks"
Info (332110): Deriving PLL clocks
    Info (332110): create_clock -period 37.037 -waveform {0.000 18.518} -name CLOCK_27 CLOCK_27
    Info (332110): create_clock -period 20.000 -waveform {0.000 10.000} -name CLOCK_50 CLOCK_50
    Info (332110): create_generated_clock -source {clock_generator_1|pll_1|altpll_component|pll|inclk[0]} -duty_cycle 50.00 -name {clock_generator_1|pll_1|altpll_component|pll|clk[0]} {clock_generator_1|pll_1|altpll_component|pll|clk[0]}
    Info (332110): create_generated_clock -source {clock_generator_1|pll_1|altpll_component|pll|inclk[0]} -divide_by 5 -duty_cycle 50.00 -name {clock_generator_1|pll_1|altpll_component|pll|clk[1]} {clock_generator_1|pll_1|altpll_component|pll|clk[1]}
    Info (332110): create_generated_clock -source {clock_generator_1|pll_2|altpll_component|pll|inclk[0]} -divide_by 9 -multiply_by 4 -duty_cycle 50.00 -name {clock_generator_1|pll_2|altpll_component|pll|clk[1]} {clock_generator_1|pll_2|altpll_component|pll|clk[1]}
Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info (332105): Deriving Clocks
    Info (332105): create_clock -period 1.000 -name AUD_BCLK AUD_BCLK
    Info (332105): create_clock -period 1.000 -name audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr
    Info (332105): create_clock -period 1.000 -name audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow Model
Warning (332009): The launch and latch times for the relationship between source clock: clock_generator_1|pll_1|altpll_component|pll|clk[1] and destination clock: clock_generator_1|pll_2|altpll_component|pll|clk[1] are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
Critical Warning (332148): Timing requirements not met
Info (332146): Worst-case setup slack is -5.130
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -5.130     -1103.783 clock_generator_1|pll_1|altpll_component|pll|clk[0] 
    Info (332119):    -1.962      -215.939 AUD_BCLK 
    Info (332119):    -1.791       -36.071 clock_generator_1|pll_2|altpll_component|pll|clk[1] 
    Info (332119):     1.558         0.000 audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr 
    Info (332119):     1.567         0.000 audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql 
    Info (332119):    30.205         0.000 CLOCK_27 
    Info (332119):    96.859         0.000 clock_generator_1|pll_1|altpll_component|pll|clk[1] 
Info (332146): Worst-case hold slack is -1.407
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.407       -23.818 audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr 
    Info (332119):    -1.388       -26.503 audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql 
    Info (332119):    -0.166        -0.317 clock_generator_1|pll_1|altpll_component|pll|clk[0] 
    Info (332119):     0.154         0.000 AUD_BCLK 
    Info (332119):     0.391         0.000 CLOCK_27 
    Info (332119):     0.391         0.000 clock_generator_1|pll_1|altpll_component|pll|clk[1] 
    Info (332119):     0.391         0.000 clock_generator_1|pll_2|altpll_component|pll|clk[1] 
Info (332146): Worst-case recovery slack is 2.904
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     2.904         0.000 clock_generator_1|pll_2|altpll_component|pll|clk[1] 
Info (332146): Worst-case removal slack is 6.117
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     6.117         0.000 clock_generator_1|pll_2|altpll_component|pll|clk[1] 
Info (332146): Worst-case minimum pulse width slack is -1.222
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.222      -142.222 AUD_BCLK 
    Info (332119):    -0.500       -24.000 audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql 
    Info (332119):    -0.500       -24.000 audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr 
    Info (332119):     8.077         0.000 clock_generator_1|pll_1|altpll_component|pll|clk[0] 
    Info (332119):    10.000         0.000 CLOCK_50 
    Info (332119):    17.518         0.000 CLOCK_27 
    Info (332119):    40.666         0.000 clock_generator_1|pll_2|altpll_component|pll|clk[1] 
    Info (332119):    49.000         0.000 clock_generator_1|pll_1|altpll_component|pll|clk[1] 
Info (332001): The selected device family is not supported by the report_metastability command.
Info: Analyzing Fast Model
Warning (332009): The launch and latch times for the relationship between source clock: clock_generator_1|pll_1|altpll_component|pll|clk[1] and destination clock: clock_generator_1|pll_2|altpll_component|pll|clk[1] are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
Critical Warning (332148): Timing requirements not met
Info (332146): Worst-case setup slack is -2.966
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -2.966      -606.223 clock_generator_1|pll_1|altpll_component|pll|clk[0] 
    Info (332119):    -0.934       -18.945 clock_generator_1|pll_2|altpll_component|pll|clk[1] 
    Info (332119):    -0.428       -31.065 AUD_BCLK 
    Info (332119):     1.665         0.000 audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr 
    Info (332119):     1.674         0.000 audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql 
    Info (332119):    33.762         0.000 CLOCK_27 
    Info (332119):    98.561         0.000 clock_generator_1|pll_1|altpll_component|pll|clk[1] 
Info (332146): Worst-case hold slack is -1.082
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.082       -22.735 audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql 
    Info (332119):    -1.080       -21.545 audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr 
    Info (332119):     0.013         0.000 clock_generator_1|pll_1|altpll_component|pll|clk[0] 
    Info (332119):     0.085         0.000 AUD_BCLK 
    Info (332119):     0.215         0.000 CLOCK_27 
    Info (332119):     0.215         0.000 clock_generator_1|pll_1|altpll_component|pll|clk[1] 
    Info (332119):     0.215         0.000 clock_generator_1|pll_2|altpll_component|pll|clk[1] 
Info (332146): Worst-case recovery slack is 5.604
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.604         0.000 clock_generator_1|pll_2|altpll_component|pll|clk[1] 
Info (332146): Worst-case removal slack is 3.531
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     3.531         0.000 clock_generator_1|pll_2|altpll_component|pll|clk[1] 
Info (332146): Worst-case minimum pulse width slack is -1.222
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    -1.222      -142.222 AUD_BCLK 
    Info (332119):    -0.500       -24.000 audio_unit:audio_unit_1|filter_unit:filter_unit_1|enql 
    Info (332119):    -0.500       -24.000 audio_unit:audio_unit_1|filter_unit:filter_unit_1|enqr 
    Info (332119):     7.981         0.000 clock_generator_1|pll_1|altpll_component|pll|clk[0] 
    Info (332119):    10.000         0.000 CLOCK_50 
    Info (332119):    17.518         0.000 CLOCK_27 
    Info (332119):    40.666         0.000 clock_generator_1|pll_2|altpll_component|pll|clk[1] 
    Info (332119):    49.000         0.000 clock_generator_1|pll_1|altpll_component|pll|clk[1] 
Info (332001): The selected device family is not supported by the report_metastability command.
Warning (332009): The launch and latch times for the relationship between source clock: clock_generator_1|pll_1|altpll_component|pll|clk[1] and destination clock: clock_generator_1|pll_2|altpll_component|pll|clk[1] are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 6 warnings
    Info: Peak virtual memory: 471 megabytes
    Info: Processing ended: Fri May 22 21:51:09 2015
    Info: Elapsed time: 00:00:07
    Info: Total CPU time (on all processors): 00:00:07


