Analysis & Synthesis report for Equalizer
Fri May 22 21:46:42 2015
Quartus II 32-bit Version 13.0.0 Build 156 04/24/2013 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Parallel Compilation
  5. Analysis & Synthesis Source Files Read
  6. Analysis & Synthesis Resource Usage Summary
  7. Analysis & Synthesis Resource Utilization by Entity
  8. Analysis & Synthesis DSP Block Usage Summary
  9. Analysis & Synthesis IP Cores Summary
 10. State Machine - |Equalizer|audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate
 11. Registers Removed During Synthesis
 12. Removed Registers Triggering Further Register Optimizations
 13. General Register Statistics
 14. Inverted Register Statistics
 15. Multiplexer Restructuring Statistics (Restructuring Performed)
 16. Parameter Settings for User Entity Instance: clock_generator:clock_generator_1|EQ_PLL_50:pll_1|altpll:altpll_component
 17. Parameter Settings for User Entity Instance: clock_generator:clock_generator_1|EQ_PLL_27:pll_2|altpll:altpll_component
 18. Parameter Settings for User Entity Instance: audio_unit:audio_unit_1|filter_unit:filter_unit_1|lpm_mult_volume:volume_muliplier|lpm_mult:lpm_mult_component
 19. Parameter Settings for User Entity Instance: audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|coeff_mul:coeff_mul_1|lpm_mult:lpm_mult_component
 20. Parameter Settings for User Entity Instance: audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|lpm_mult0:lpm_mult0_1|lpm_mult:lpm_mult_component
 21. Parameter Settings for User Entity Instance: audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|lpm_mult0:lpm_mult0_2|lpm_mult:lpm_mult_component
 22. altpll Parameter Settings by Entity Instance
 23. lpm_mult Parameter Settings by Entity Instance
 24. Port Connectivity Checks: "audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|coeff_mul:coeff_mul_1"
 25. Port Connectivity Checks: "audio_unit:audio_unit_1|filter_unit:filter_unit_1|lpm_mult_volume:volume_muliplier"
 26. Port Connectivity Checks: "audio_unit:audio_unit_1|i2c_master:i2c_master_1"
 27. Port Connectivity Checks: "clock_generator:clock_generator_1"
 28. Elapsed Time Per Partition
 29. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+---------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                    ;
+------------------------------------+--------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Fri May 22 21:46:41 2015      ;
; Quartus II 32-bit Version          ; 13.0.0 Build 156 04/24/2013 SJ Web Edition ;
; Revision Name                      ; Equalizer                                  ;
; Top-level Entity Name              ; Equalizer                                  ;
; Family                             ; Cyclone II                                 ;
; Total logic elements               ; 10,840                                     ;
;     Total combinational functions  ; 10,588                                     ;
;     Dedicated logic registers      ; 4,698                                      ;
; Total registers                    ; 4698                                       ;
; Total pins                         ; 101                                        ;
; Total virtual pins                 ; 0                                          ;
; Total memory bits                  ; 0                                          ;
; Embedded Multiplier 9-bit elements ; 67                                         ;
; Total PLLs                         ; 2                                          ;
+------------------------------------+--------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                        ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Option                                                                     ; Setting            ; Default Value      ;
+----------------------------------------------------------------------------+--------------------+--------------------+
; Device                                                                     ; EP2C35F672C6       ;                    ;
; Top-level entity name                                                      ; Equalizer          ; Equalizer          ;
; Family name                                                                ; Cyclone II         ; Cyclone IV GX      ;
; VHDL Show LMF Mapping Messages                                             ; Off                ;                    ;
; VHDL Version                                                               ; VHDL_2008          ; VHDL_1993          ;
; Optimization Technique                                                     ; Speed              ; Balanced           ;
; Timing-Driven Synthesis                                                    ; On                 ; Off                ;
; Use smart compilation                                                      ; Off                ; Off                ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
; Enable compact report table                                                ; Off                ; Off                ;
; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
; Preserve fewer node names                                                  ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
; State Machine Processing                                                   ; Auto               ; Auto               ;
; Safe State Machine                                                         ; Off                ; Off                ;
; Extract Verilog State Machines                                             ; On                 ; On                 ;
; Extract VHDL State Machines                                                ; On                 ; On                 ;
; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
; Parallel Synthesis                                                         ; Off                ; Off                ;
; DSP Block Balancing                                                        ; Auto               ; Auto               ;
; NOT Gate Push-Back                                                         ; On                 ; On                 ;
; Power-Up Don't Care                                                        ; On                 ; On                 ;
; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
; Remove Duplicate Registers                                                 ; On                 ; On                 ;
; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
; Carry Chain Length                                                         ; 70                 ; 70                 ;
; Auto Carry Chains                                                          ; On                 ; On                 ;
; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
; Auto ROM Replacement                                                       ; On                 ; On                 ;
; Auto RAM Replacement                                                       ; On                 ; On                 ;
; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
; Strict RAM Replacement                                                     ; Off                ; Off                ;
; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
; Auto Resource Sharing                                                      ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
; Report Parameter Settings                                                  ; On                 ; On                 ;
; Report Source Assignments                                                  ; On                 ; On                 ;
; Report Connectivity Checks                                                 ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
; HDL message level                                                          ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
; Clock MUX Protection                                                       ; On                 ; On                 ;
; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
; Block Design Naming                                                        ; Auto               ; Auto               ;
; SDC constraint protection                                                  ; Off                ; Off                ;
; Synthesis Effort                                                           ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
; Pre-Mapping Resynthesis Optimization                                       ; Off                ; Off                ;
; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
; Synthesis Seed                                                             ; 1                  ; 1                  ;
+----------------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 2           ;
; Maximum allowed            ; 2           ;
;                            ;             ;
; Average used               ; 1.01        ;
; Maximum used               ; 2           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processor 2            ;   1.4%      ;
+----------------------------+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                               ;
+----------------------------------+-----------------+-----------------------------------+-----------------------------------------------------------------------------------+---------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                         ; File Name with Absolute Path                                                      ; Library ;
+----------------------------------+-----------------+-----------------------------------+-----------------------------------------------------------------------------------+---------+
; lpm_mult0.vhd                    ; yes             ; User Wizard-Generated File        ; C:/work/Projekte/zu sortieren/EQ/CD/Quellcode/Equalizer/lpm_mult0.vhd             ;         ;
; EQ_PLL_27.vhd                    ; yes             ; User Wizard-Generated File        ; C:/work/Projekte/zu sortieren/EQ/CD/Quellcode/Equalizer/EQ_PLL_27.vhd             ;         ;
; EQ_PLL_50.vhd                    ; yes             ; User Wizard-Generated File        ; C:/work/Projekte/zu sortieren/EQ/CD/Quellcode/Equalizer/EQ_PLL_50.vhd             ;         ;
; iir.vhd                          ; yes             ; User VHDL File                    ; C:/work/Projekte/zu sortieren/EQ/CD/Quellcode/Equalizer/iir.vhd                   ;         ;
; lcd_controller.vhd               ; yes             ; User VHDL File                    ; C:/work/Projekte/zu sortieren/EQ/CD/Quellcode/Equalizer/lcd_controller.vhd        ;         ;
; mmi_controller.vhd               ; yes             ; User VHDL File                    ; C:/work/Projekte/zu sortieren/EQ/CD/Quellcode/Equalizer/mmi_controller.vhd        ;         ;
; clock_generator.vhd              ; yes             ; User VHDL File                    ; C:/work/Projekte/zu sortieren/EQ/CD/Quellcode/Equalizer/clock_generator.vhd       ;         ;
; Equalizer.vhd                    ; yes             ; User VHDL File                    ; C:/work/Projekte/zu sortieren/EQ/CD/Quellcode/Equalizer/Equalizer.vhd             ;         ;
; clock_divider.vhd                ; yes             ; User VHDL File                    ; C:/work/Projekte/zu sortieren/EQ/CD/Quellcode/Equalizer/clock_divider.vhd         ;         ;
; coefficients_register.vhd        ; yes             ; User VHDL File                    ; C:/work/Projekte/zu sortieren/EQ/CD/Quellcode/Equalizer/coefficients_register.vhd ;         ;
; coeff_mul.vhd                    ; yes             ; User Wizard-Generated File        ; C:/work/Projekte/zu sortieren/EQ/CD/Quellcode/Equalizer/coeff_mul.vhd             ;         ;
; altpll.tdf                       ; yes             ; Megafunction                      ; c:/altera/13.0/quartus/libraries/megafunctions/altpll.tdf                         ;         ;
; aglobal130.inc                   ; yes             ; Megafunction                      ; c:/altera/13.0/quartus/libraries/megafunctions/aglobal130.inc                     ;         ;
; stratix_pll.inc                  ; yes             ; Megafunction                      ; c:/altera/13.0/quartus/libraries/megafunctions/stratix_pll.inc                    ;         ;
; stratixii_pll.inc                ; yes             ; Megafunction                      ; c:/altera/13.0/quartus/libraries/megafunctions/stratixii_pll.inc                  ;         ;
; cycloneii_pll.inc                ; yes             ; Megafunction                      ; c:/altera/13.0/quartus/libraries/megafunctions/cycloneii_pll.inc                  ;         ;
; mmi.vhd                          ; yes             ; Auto-Found VHDL File              ; C:/work/Projekte/zu sortieren/EQ/CD/Quellcode/Equalizer/mmi.vhd                   ;         ;
; audio_unit.vhd                   ; yes             ; Auto-Found VHDL File              ; C:/work/Projekte/zu sortieren/EQ/CD/Quellcode/Equalizer/audio_unit.vhd            ;         ;
; i2c_master.vhd                   ; yes             ; Auto-Found VHDL File              ; C:/work/Projekte/zu sortieren/EQ/CD/Quellcode/Equalizer/i2c_master.vhd            ;         ;
; audio_input_register.vhd         ; yes             ; Auto-Found VHDL File              ; C:/work/Projekte/zu sortieren/EQ/CD/Quellcode/Equalizer/audio_input_register.vhd  ;         ;
; filter_unit.vhd                  ; yes             ; Auto-Found VHDL File              ; C:/work/Projekte/zu sortieren/EQ/CD/Quellcode/Equalizer/filter_unit.vhd           ;         ;
; db2linear.vhd                    ; yes             ; Auto-Found VHDL File              ; C:/work/Projekte/zu sortieren/EQ/CD/Quellcode/Equalizer/db2linear.vhd             ;         ;
; lpm_mult_volume.vhd              ; yes             ; Auto-Found Wizard-Generated File  ; C:/work/Projekte/zu sortieren/EQ/CD/Quellcode/Equalizer/lpm_mult_volume.vhd       ;         ;
; lpm_mult.tdf                     ; yes             ; Megafunction                      ; c:/altera/13.0/quartus/libraries/megafunctions/lpm_mult.tdf                       ;         ;
; lpm_add_sub.inc                  ; yes             ; Megafunction                      ; c:/altera/13.0/quartus/libraries/megafunctions/lpm_add_sub.inc                    ;         ;
; multcore.inc                     ; yes             ; Megafunction                      ; c:/altera/13.0/quartus/libraries/megafunctions/multcore.inc                       ;         ;
; bypassff.inc                     ; yes             ; Megafunction                      ; c:/altera/13.0/quartus/libraries/megafunctions/bypassff.inc                       ;         ;
; altshift.inc                     ; yes             ; Megafunction                      ; c:/altera/13.0/quartus/libraries/megafunctions/altshift.inc                       ;         ;
; db/mult_knq.tdf                  ; yes             ; Auto-Generated Megafunction       ; C:/work/Projekte/zu sortieren/EQ/CD/Quellcode/Equalizer/db/mult_knq.tdf           ;         ;
; db/mult_3pq.tdf                  ; yes             ; Auto-Generated Megafunction       ; C:/work/Projekte/zu sortieren/EQ/CD/Quellcode/Equalizer/db/mult_3pq.tdf           ;         ;
; db/mult_0oq.tdf                  ; yes             ; Auto-Generated Megafunction       ; C:/work/Projekte/zu sortieren/EQ/CD/Quellcode/Equalizer/db/mult_0oq.tdf           ;         ;
; audio_output_register.vhd        ; yes             ; Auto-Found VHDL File              ; C:/work/Projekte/zu sortieren/EQ/CD/Quellcode/Equalizer/audio_output_register.vhd ;         ;
+----------------------------------+-----------------+-----------------------------------+-----------------------------------------------------------------------------------+---------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                                                                                   ;
+---------------------------------------------+---------------------------------------------------------------------------------+
; Resource                                    ; Usage                                                                           ;
+---------------------------------------------+---------------------------------------------------------------------------------+
; Estimated Total logic elements              ; 10,840                                                                          ;
;                                             ;                                                                                 ;
; Total combinational functions               ; 10588                                                                           ;
; Logic element usage by number of LUT inputs ;                                                                                 ;
;     -- 4 input functions                    ; 3541                                                                            ;
;     -- 3 input functions                    ; 3346                                                                            ;
;     -- <=2 input functions                  ; 3701                                                                            ;
;                                             ;                                                                                 ;
; Logic elements by mode                      ;                                                                                 ;
;     -- normal mode                          ; 6365                                                                            ;
;     -- arithmetic mode                      ; 4223                                                                            ;
;                                             ;                                                                                 ;
; Total registers                             ; 4698                                                                            ;
;     -- Dedicated logic registers            ; 4698                                                                            ;
;     -- I/O registers                        ; 0                                                                               ;
;                                             ;                                                                                 ;
; I/O pins                                    ; 101                                                                             ;
; Embedded Multiplier 9-bit elements          ; 67                                                                              ;
; Total PLLs                                  ; 2                                                                               ;
;     -- PLLs                                 ; 2                                                                               ;
;                                             ;                                                                                 ;
; Maximum fan-out node                        ; clock_generator:clock_generator_1|EQ_PLL_50:pll_1|altpll:altpll_component|_clk0 ;
; Maximum fan-out                             ; 4458                                                                            ;
; Total fan-out                               ; 45552                                                                           ;
; Average fan-out                             ; 2.95                                                                            ;
+---------------------------------------------+---------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                        ;
+----------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node                               ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                                                                  ; Library Name ;
+----------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; |Equalizer                                               ; 10588 (1)         ; 4698 (0)     ; 0           ; 67           ; 1       ; 33        ; 101  ; 0            ; |Equalizer                                                                                                                                                                           ;              ;
;    |MMI:MMI_1|                                           ; 1175 (0)          ; 259 (0)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Equalizer|MMI:MMI_1                                                                                                                                                                 ;              ;
;       |lcd_controller:lcd_controller_1|                  ; 134 (134)         ; 39 (39)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Equalizer|MMI:MMI_1|lcd_controller:lcd_controller_1                                                                                                                                 ;              ;
;       |mmi_controller:mmi_controller_1|                  ; 1041 (1041)       ; 220 (220)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Equalizer|MMI:MMI_1|mmi_controller:mmi_controller_1                                                                                                                                 ;              ;
;    |audio_unit:audio_unit_1|                             ; 9337 (1)          ; 4402 (0)     ; 0           ; 67           ; 1       ; 33        ; 0    ; 0            ; |Equalizer|audio_unit:audio_unit_1                                                                                                                                                   ;              ;
;       |audio_input_register:audio_input_register_1|      ; 96 (96)           ; 84 (84)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Equalizer|audio_unit:audio_unit_1|audio_input_register:audio_input_register_1                                                                                                       ;              ;
;       |audio_output_register:audio_output_register_1|    ; 74 (74)           ; 105 (105)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Equalizer|audio_unit:audio_unit_1|audio_output_register:audio_output_register_1                                                                                                     ;              ;
;       |filter_unit:filter_unit_1|                        ; 9094 (182)        ; 4189 (234)   ; 0           ; 67           ; 1       ; 33        ; 0    ; 0            ; |Equalizer|audio_unit:audio_unit_1|filter_unit:filter_unit_1                                                                                                                         ;              ;
;          |coefficients_register:coefficients_register_1| ; 3646 (2998)       ; 1890 (1890)  ; 0           ; 24           ; 0       ; 12        ; 0    ; 0            ; |Equalizer|audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1                                                                           ;              ;
;             |coeff_mul:coeff_mul_1|                      ; 330 (0)           ; 0 (0)        ; 0           ; 24           ; 0       ; 12        ; 0    ; 0            ; |Equalizer|audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|coeff_mul:coeff_mul_1                                                     ;              ;
;                |lpm_mult:lpm_mult_component|             ; 330 (0)           ; 0 (0)        ; 0           ; 24           ; 0       ; 12        ; 0    ; 0            ; |Equalizer|audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|coeff_mul:coeff_mul_1|lpm_mult:lpm_mult_component                         ;              ;
;                   |mult_3pq:auto_generated|              ; 330 (330)         ; 0 (0)        ; 0           ; 24           ; 0       ; 12        ; 0    ; 0            ; |Equalizer|audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|coeff_mul:coeff_mul_1|lpm_mult:lpm_mult_component|mult_3pq:auto_generated ;              ;
;             |db2linear:db2linear_1|                      ; 318 (318)         ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Equalizer|audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|db2linear:db2linear_1                                                     ;              ;
;          |db2linear:volume_db2linear|                    ; 311 (311)         ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Equalizer|audio_unit:audio_unit_1|filter_unit:filter_unit_1|db2linear:volume_db2linear                                                                                              ;              ;
;          |iir:filter|                                    ; 4874 (4448)       ; 2065 (2065)  ; 0           ; 32           ; 0       ; 16        ; 0    ; 0            ; |Equalizer|audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter                                                                                                              ;              ;
;             |lpm_mult0:lpm_mult0_1|                      ; 213 (0)           ; 0 (0)        ; 0           ; 16           ; 0       ; 8         ; 0    ; 0            ; |Equalizer|audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|lpm_mult0:lpm_mult0_1                                                                                        ;              ;
;                |lpm_mult:lpm_mult_component|             ; 213 (0)           ; 0 (0)        ; 0           ; 16           ; 0       ; 8         ; 0    ; 0            ; |Equalizer|audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|lpm_mult0:lpm_mult0_1|lpm_mult:lpm_mult_component                                                            ;              ;
;                   |mult_0oq:auto_generated|              ; 213 (213)         ; 0 (0)        ; 0           ; 16           ; 0       ; 8         ; 0    ; 0            ; |Equalizer|audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|lpm_mult0:lpm_mult0_1|lpm_mult:lpm_mult_component|mult_0oq:auto_generated                                    ;              ;
;             |lpm_mult0:lpm_mult0_2|                      ; 213 (0)           ; 0 (0)        ; 0           ; 16           ; 0       ; 8         ; 0    ; 0            ; |Equalizer|audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|lpm_mult0:lpm_mult0_2                                                                                        ;              ;
;                |lpm_mult:lpm_mult_component|             ; 213 (0)           ; 0 (0)        ; 0           ; 16           ; 0       ; 8         ; 0    ; 0            ; |Equalizer|audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|lpm_mult0:lpm_mult0_2|lpm_mult:lpm_mult_component                                                            ;              ;
;                   |mult_0oq:auto_generated|              ; 213 (213)         ; 0 (0)        ; 0           ; 16           ; 0       ; 8         ; 0    ; 0            ; |Equalizer|audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|lpm_mult0:lpm_mult0_2|lpm_mult:lpm_mult_component|mult_0oq:auto_generated                                    ;              ;
;          |lpm_mult_volume:volume_muliplier|              ; 81 (0)            ; 0 (0)        ; 0           ; 11           ; 1       ; 5         ; 0    ; 0            ; |Equalizer|audio_unit:audio_unit_1|filter_unit:filter_unit_1|lpm_mult_volume:volume_muliplier                                                                                        ;              ;
;             |lpm_mult:lpm_mult_component|                ; 81 (0)            ; 0 (0)        ; 0           ; 11           ; 1       ; 5         ; 0    ; 0            ; |Equalizer|audio_unit:audio_unit_1|filter_unit:filter_unit_1|lpm_mult_volume:volume_muliplier|lpm_mult:lpm_mult_component                                                            ;              ;
;                |mult_knq:auto_generated|                 ; 81 (81)           ; 0 (0)        ; 0           ; 11           ; 1       ; 5         ; 0    ; 0            ; |Equalizer|audio_unit:audio_unit_1|filter_unit:filter_unit_1|lpm_mult_volume:volume_muliplier|lpm_mult:lpm_mult_component|mult_knq:auto_generated                                    ;              ;
;       |i2c_master:i2c_master_1|                          ; 72 (72)           ; 24 (24)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Equalizer|audio_unit:audio_unit_1|i2c_master:i2c_master_1                                                                                                                           ;              ;
;    |clock_generator:clock_generator_1|                   ; 75 (61)           ; 37 (27)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Equalizer|clock_generator:clock_generator_1                                                                                                                                         ;              ;
;       |EQ_PLL_27:pll_2|                                  ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Equalizer|clock_generator:clock_generator_1|EQ_PLL_27:pll_2                                                                                                                         ;              ;
;          |altpll:altpll_component|                       ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Equalizer|clock_generator:clock_generator_1|EQ_PLL_27:pll_2|altpll:altpll_component                                                                                                 ;              ;
;       |EQ_PLL_50:pll_1|                                  ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Equalizer|clock_generator:clock_generator_1|EQ_PLL_50:pll_1                                                                                                                         ;              ;
;          |altpll:altpll_component|                       ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Equalizer|clock_generator:clock_generator_1|EQ_PLL_50:pll_1|altpll:altpll_component                                                                                                 ;              ;
;       |clock_divider:clock_divider_1|                    ; 14 (14)           ; 10 (10)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Equalizer|clock_generator:clock_generator_1|clock_divider:clock_divider_1                                                                                                           ;              ;
+----------------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+-----------------------------------------------------+
; Analysis & Synthesis DSP Block Usage Summary        ;
+---------------------------------------+-------------+
; Statistic                             ; Number Used ;
+---------------------------------------+-------------+
; Simple Multipliers (9-bit)            ; 1           ;
; Simple Multipliers (18-bit)           ; 33          ;
; Embedded Multiplier Blocks            ; --          ;
; Embedded Multiplier 9-bit elements    ; 67          ;
; Signed Embedded Multipliers           ; 4           ;
; Unsigned Embedded Multipliers         ; 14          ;
; Mixed Sign Embedded Multipliers       ; 16          ;
; Variable Sign Embedded Multipliers    ; 0           ;
; Dedicated Input Shift Register Chains ; 0           ;
+---------------------------------------+-------------+
Note: number of Embedded Multiplier Blocks used is only available after a successful fit.


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary                                                                                                                                                                                                                                          ;
+--------+--------------+---------+--------------+--------------+----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance                                                                                                                  ; IP Include File                                                             ;
+--------+--------------+---------+--------------+--------------+----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+
; Altera ; LPM_MULT     ; 11.1    ; N/A          ; N/A          ; |Equalizer|audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|coeff_mul:coeff_mul_1 ; C:/work/Projekte/zu sortieren/EQ/CD/Quellcode/Equalizer/coeff_mul.vhd       ;
; Altera ; LPM_MULT     ; N/A     ; N/A          ; N/A          ; |Equalizer|audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|lpm_mult0:lpm_mult0_1                                    ; C:/work/Projekte/zu sortieren/EQ/CD/Quellcode/Equalizer/lpm_mult0.vhd       ;
; Altera ; LPM_MULT     ; N/A     ; N/A          ; N/A          ; |Equalizer|audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|lpm_mult0:lpm_mult0_2                                    ; C:/work/Projekte/zu sortieren/EQ/CD/Quellcode/Equalizer/lpm_mult0.vhd       ;
; Altera ; LPM_MULT     ; N/A     ; N/A          ; N/A          ; |Equalizer|audio_unit:audio_unit_1|filter_unit:filter_unit_1|lpm_mult_volume:volume_muliplier                                    ; C:/work/Projekte/zu sortieren/EQ/CD/Quellcode/Equalizer/lpm_mult_volume.vhd ;
; Altera ; ALTPLL       ; N/A     ; N/A          ; N/A          ; |Equalizer|clock_generator:clock_generator_1|EQ_PLL_50:pll_1                                                                     ; C:/work/Projekte/zu sortieren/EQ/CD/Quellcode/Equalizer/EQ_PLL_50.vhd       ;
; Altera ; ALTPLL       ; N/A     ; N/A          ; N/A          ; |Equalizer|clock_generator:clock_generator_1|EQ_PLL_27:pll_2                                                                     ; C:/work/Projekte/zu sortieren/EQ/CD/Quellcode/Equalizer/EQ_PLL_27.vhd       ;
+--------+--------------+---------+--------------+--------------+----------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------+


Encoding Type:  One-Hot
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |Equalizer|audio_unit:audio_unit_1|i2c_master:i2c_master_1|reg_fstate                                                                                                                                                                                                 ;
+---------------------------+-----------------+--------------------------+------------------------+------------------+----------------+------------------------+-----------------------+---------------------+------------------+---------------------------+---------------------------+
; Name                      ; reg_fstate.ende ; reg_fstate.stopbedingung ; reg_fstate.stop_warten ; reg_fstate.error ; reg_fstate.ack ; reg_fstate.ack_warten2 ; reg_fstate.ack_warten ; reg_fstate.taktende ; reg_fstate.bit_n ; reg_fstate.startbedingung ; reg_fstate.anfangszustand ;
+---------------------------+-----------------+--------------------------+------------------------+------------------+----------------+------------------------+-----------------------+---------------------+------------------+---------------------------+---------------------------+
; reg_fstate.anfangszustand ; 0               ; 0                        ; 0                      ; 0                ; 0              ; 0                      ; 0                     ; 0                   ; 0                ; 0                         ; 0                         ;
; reg_fstate.startbedingung ; 0               ; 0                        ; 0                      ; 0                ; 0              ; 0                      ; 0                     ; 0                   ; 0                ; 1                         ; 1                         ;
; reg_fstate.bit_n          ; 0               ; 0                        ; 0                      ; 0                ; 0              ; 0                      ; 0                     ; 0                   ; 1                ; 0                         ; 1                         ;
; reg_fstate.taktende       ; 0               ; 0                        ; 0                      ; 0                ; 0              ; 0                      ; 0                     ; 1                   ; 0                ; 0                         ; 1                         ;
; reg_fstate.ack_warten     ; 0               ; 0                        ; 0                      ; 0                ; 0              ; 0                      ; 1                     ; 0                   ; 0                ; 0                         ; 1                         ;
; reg_fstate.ack_warten2    ; 0               ; 0                        ; 0                      ; 0                ; 0              ; 1                      ; 0                     ; 0                   ; 0                ; 0                         ; 1                         ;
; reg_fstate.ack            ; 0               ; 0                        ; 0                      ; 0                ; 1              ; 0                      ; 0                     ; 0                   ; 0                ; 0                         ; 1                         ;
; reg_fstate.error          ; 0               ; 0                        ; 0                      ; 1                ; 0              ; 0                      ; 0                     ; 0                   ; 0                ; 0                         ; 1                         ;
; reg_fstate.stop_warten    ; 0               ; 0                        ; 1                      ; 0                ; 0              ; 0                      ; 0                     ; 0                   ; 0                ; 0                         ; 1                         ;
; reg_fstate.stopbedingung  ; 0               ; 1                        ; 0                      ; 0                ; 0              ; 0                      ; 0                     ; 0                   ; 0                ; 0                         ; 1                         ;
; reg_fstate.ende           ; 1               ; 0                        ; 0                      ; 0                ; 0              ; 0                      ; 0                     ; 0                   ; 0                ; 0                         ; 1                         ;
+---------------------------+-----------------+--------------------------+------------------------+------------------+----------------+------------------------+-----------------------+---------------------+------------------+---------------------------+---------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------+
; Register name                                                                                                 ; Reason for Removal                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------+
; MMI:MMI_1|mmi_controller:mmi_controller_1|db_letter_2[0]                                                      ; Stuck at VCC due to stuck port data_in                                                                                ;
; MMI:MMI_1|mmi_controller:mmi_controller_1|lcd_1[0,3,7]                                                        ; Stuck at GND due to stuck port data_in                                                                                ;
; MMI:MMI_1|mmi_controller:mmi_controller_1|lcd_1[8]                                                            ; Stuck at VCC due to stuck port data_in                                                                                ;
; MMI:MMI_1|mmi_controller:mmi_controller_1|db_letter_2[1]                                                      ; Stuck at VCC due to stuck port data_in                                                                                ;
; MMI:MMI_1|mmi_controller:mmi_controller_1|db_letter_1[0,5]                                                    ; Stuck at VCC due to stuck port data_in                                                                                ;
; MMI:MMI_1|mmi_controller:mmi_controller_1|db_sign[0..5]                                                       ; Stuck at VCC due to stuck port data_in                                                                                ;
; MMI:MMI_1|lcd_controller:lcd_controller_1|stop                                                                ; Stuck at GND due to stuck port data_in                                                                                ;
; MMI:MMI_1|mmi_controller:mmi_controller_1|lcd_1[6]                                                            ; Merged with MMI:MMI_1|mmi_controller:mmi_controller_1|lcd_1[2]                                                        ;
; MMI:MMI_1|mmi_controller:mmi_controller_1|lcd_1[2]                                                            ; Merged with MMI:MMI_1|mmi_controller:mmi_controller_1|lcd_1[1]                                                        ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|mul_b_2[2,4..6]                                  ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|mul_b_2[1]                                   ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|mul_b_2[61..63]                                  ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|mul_b_2[60]                                  ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a2[0..5,58]                                      ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[0]                                        ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[0]                                            ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[0]                                        ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[2,4..6]                                       ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[1]                                        ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[1,2,4..6]                                     ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[1]                                        ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a2[59..63]                                       ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[3]                                        ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[3]                                            ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[3]                                        ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[7]                                            ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[7]                                        ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[8]                                            ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[8]                                        ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[9]                                            ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[9]                                        ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[12]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[12]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[14]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[14]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[16]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[16]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[17]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[17]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[35]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[35]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[37]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[37]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[48]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[48]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[61..63]                                       ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[60]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[60..63]                                       ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[60]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_a[58..63] ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_a[57] ;
; MMI:MMI_1|mmi_controller:mmi_controller_1|lcd_4[2,3]                                                          ; Merged with MMI:MMI_1|mmi_controller:mmi_controller_1|lcd_4[0]                                                        ;
; MMI:MMI_1|mmi_controller:mmi_controller_1|lcd_4[4,6,7]                                                        ; Merged with MMI:MMI_1|mmi_controller:mmi_controller_1|lcd_4[1]                                                        ;
; MMI:MMI_1|mmi_controller:mmi_controller_1|lcd_5[3,6,7]                                                        ; Merged with MMI:MMI_1|mmi_controller:mmi_controller_1|lcd_4[1]                                                        ;
; MMI:MMI_1|mmi_controller:mmi_controller_1|lcd_6[6,7]                                                          ; Merged with MMI:MMI_1|mmi_controller:mmi_controller_1|lcd_4[1]                                                        ;
; MMI:MMI_1|mmi_controller:mmi_controller_1|lcd_4[8]                                                            ; Merged with MMI:MMI_1|mmi_controller:mmi_controller_1|lcd_4[5]                                                        ;
; MMI:MMI_1|mmi_controller:mmi_controller_1|lcd_5[5,8]                                                          ; Merged with MMI:MMI_1|mmi_controller:mmi_controller_1|lcd_4[5]                                                        ;
; MMI:MMI_1|mmi_controller:mmi_controller_1|lcd_6[5,8]                                                          ; Merged with MMI:MMI_1|mmi_controller:mmi_controller_1|lcd_4[5]                                                        ;
; MMI:MMI_1|mmi_controller:mmi_controller_1|lcd_3[4]                                                            ; Merged with MMI:MMI_1|mmi_controller:mmi_controller_1|lcd_2[4]                                                        ;
; MMI:MMI_1|mmi_controller:mmi_controller_1|lcd_2[8]                                                            ; Merged with MMI:MMI_1|mmi_controller:mmi_controller_1|lcd_2[5]                                                        ;
; MMI:MMI_1|mmi_controller:mmi_controller_1|lcd_3[5,8]                                                          ; Merged with MMI:MMI_1|mmi_controller:mmi_controller_1|lcd_2[5]                                                        ;
; MMI:MMI_1|mmi_controller:mmi_controller_1|lcd_2[2,3,6]                                                        ; Merged with MMI:MMI_1|mmi_controller:mmi_controller_1|lcd_2[1]                                                        ;
; MMI:MMI_1|mmi_controller:mmi_controller_1|lcd_3[6]                                                            ; Merged with MMI:MMI_1|mmi_controller:mmi_controller_1|lcd_2[1]                                                        ;
; MMI:MMI_1|mmi_controller:mmi_controller_1|lcd_3[7]                                                            ; Merged with MMI:MMI_1|mmi_controller:mmi_controller_1|lcd_2[7]                                                        ;
; MMI:MMI_1|mmi_controller:mmi_controller_1|db_ten[3]                                                           ; Merged with MMI:MMI_1|mmi_controller:mmi_controller_1|db_ten[0]                                                       ;
; MMI:MMI_1|mmi_controller:mmi_controller_1|filter_ten[2]                                                       ; Merged with MMI:MMI_1|mmi_controller:mmi_controller_1|filter_ten[1]                                                   ;
; MMI:MMI_1|lcd_controller:lcd_controller_1|counter[6,7]                                                        ; Merged with MMI:MMI_1|lcd_controller:lcd_controller_1|counter[5]                                                      ;
; MMI:MMI_1|mmi_controller:mmi_controller_1|lcd_6[4]                                                            ; Merged with MMI:MMI_1|mmi_controller:mmi_controller_1|lcd_5[4]                                                        ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[10]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[10]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[11]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[11]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[13]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[13]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[15]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[15]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[18]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[18]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[19]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[19]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[20]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[20]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[21]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[21]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[22]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[22]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[23]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[23]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[24]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[24]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[25]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[25]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[26]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[26]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[27]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[27]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a2[22]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[28]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[28]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[28]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[29]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[29]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[30]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[30]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[31]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[31]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[32]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[32]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[33]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[33]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[34]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[34]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[36]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[36]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[38]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[38]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[39]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[39]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[40]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[40]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[41]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[41]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[42]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[42]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[43]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[43]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[44]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[44]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[45]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[45]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[46]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[46]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[47]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[47]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[49]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[49]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[50]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[50]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[51]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[51]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[52]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[52]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[53]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[53]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[54]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[54]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[55]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[55]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[56]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[56]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[57]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[57]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[58]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[58]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a2[25]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[59]                                       ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b1[59]                                           ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[59]                                       ;
; MMI:MMI_1|mmi_controller:mmi_controller_1|filter_ten[3..5]                                                    ; Merged with MMI:MMI_1|mmi_controller:mmi_controller_1|filter_ten[0]                                                   ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|vmb[39]                                                     ; Stuck at GND due to stuck port data_in                                                                                ;
; MMI:MMI_1|lcd_controller:lcd_controller_1|counter[5]                                                          ; Stuck at GND due to stuck port data_in                                                                                ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[3]                                            ; Stuck at GND due to stuck port data_in                                                                                ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|mul_b_2[3]                                       ; Stuck at GND due to stuck port data_in                                                                                ;
; MMI:MMI_1|mmi_controller:mmi_controller_1|filter_ten[6]                                                       ; Stuck at VCC due to stuck port data_in                                                                                ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[39]     ; Stuck at GND due to stuck port data_in                                                                                ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_a[57]     ; Stuck at GND due to stuck port data_in                                                                                ;
; MMI:MMI_1|mmi_controller:mmi_controller_1|lcd_2[7]                                                            ; Stuck at GND due to stuck port data_in                                                                                ;
; MMI:MMI_1|mmi_controller:mmi_controller_1|lcd_4[1]                                                            ; Stuck at GND due to stuck port data_in                                                                                ;
; MMI:MMI_1|mmi_controller:mmi_controller_1|lcd_2[5]                                                            ; Stuck at VCC due to stuck port data_in                                                                                ;
; MMI:MMI_1|mmi_controller:mmi_controller_1|lcd_4[5]                                                            ; Stuck at VCC due to stuck port data_in                                                                                ;
; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[0]                        ; Stuck at GND due to stuck port data_in                                                                                ;
; audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[0]                        ; Stuck at GND due to stuck port data_in                                                                                ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[0]                                            ; Stuck at VCC due to stuck port data_in                                                                                ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|mul_b_2[0]                                       ; Stuck at VCC due to stuck port data_in                                                                                ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y[23]                                            ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y1_14[23]                                    ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y[22]                                            ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y1_14[22]                                    ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y[21]                                            ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y1_14[21]                                    ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y[20]                                            ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y1_14[20]                                    ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y[19]                                            ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y1_14[19]                                    ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y[18]                                            ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y1_14[18]                                    ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y[17]                                            ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y1_14[17]                                    ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y[16]                                            ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y1_14[16]                                    ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y[0]                                             ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y1_14[0]                                     ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y[1]                                             ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y1_14[1]                                     ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y[2]                                             ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y1_14[2]                                     ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y[3]                                             ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y1_14[3]                                     ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y[4]                                             ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y1_14[4]                                     ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y[5]                                             ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y1_14[5]                                     ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y[6]                                             ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y1_14[6]                                     ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y[7]                                             ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y1_14[7]                                     ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y[8]                                             ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y1_14[8]                                     ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y[9]                                             ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y1_14[9]                                     ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y[10]                                            ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y1_14[10]                                    ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y[11]                                            ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y1_14[11]                                    ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y[12]                                            ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y1_14[12]                                    ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y[13]                                            ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y1_14[13]                                    ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y[14]                                            ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y1_14[14]                                    ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y[15]                                            ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|y1_14[15]                                    ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|b2_1[0]       ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|b0_1[0]   ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|b2_2[0]       ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|b0_2[0]   ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|b2_3[0]       ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|b0_3[0]   ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|b2_4[0]       ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|b0_4[0]   ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|b2_5[0]       ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|b0_5[0]   ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|b2_6[0]       ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|b0_6[0]   ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|b2_7[0]       ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|b0_7[0]   ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|b2_8[0]       ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|b0_8[0]   ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|b2_9[0]       ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|b0_9[0]   ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|b2_10[0]      ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|b0_10[0]  ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|b2_11[0]      ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|b0_11[0]  ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|b2_12[0]      ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|b0_12[0]  ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|b2_13[0]      ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|b0_13[0]  ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|b2_14[0]      ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|b0_14[0]  ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b2[0]                                            ; Merged with audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|b0[0]                                        ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|tmp1[83..87]                                     ; Lost fanout                                                                                                           ;
; Total Number of Removed Registers = 206                                                                       ;                                                                                                                       ;
+---------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations                                                                                                              ;
+--------------------------------------------------------------------+---------------------------+-------------------------------------------------------------------------+
; Register name                                                      ; Reason for Removal        ; Registers Removed due to This Register                                  ;
+--------------------------------------------------------------------+---------------------------+-------------------------------------------------------------------------+
; MMI:MMI_1|lcd_controller:lcd_controller_1|stop                     ; Stuck at GND              ; MMI:MMI_1|lcd_controller:lcd_controller_1|counter[5]                    ;
;                                                                    ; due to stuck port data_in ;                                                                         ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[3] ; Stuck at GND              ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|mul_b_2[3] ;
;                                                                    ; due to stuck port data_in ;                                                                         ;
; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|a1[0] ; Stuck at VCC              ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|mul_b_2[0] ;
;                                                                    ; due to stuck port data_in ;                                                                         ;
+--------------------------------------------------------------------+---------------------------+-------------------------------------------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 4698  ;
; Number of registers using Synchronous Clear  ; 229   ;
; Number of registers using Synchronous Load   ; 141   ;
; Number of registers using Asynchronous Clear ; 18    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 3155  ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------------------------------------------+
; Inverted Register Statistics                                      ;
+---------------------------------------------------------+---------+
; Inverted Register                                       ; Fan out ;
+---------------------------------------------------------+---------+
; clock_generator:clock_generator_1|reset                 ; 199     ;
; MMI:MMI_1|lcd_controller:lcd_controller_1|start         ; 4       ;
; clock_generator:clock_generator_1|start_counter[0]      ; 2       ;
; clock_generator:clock_generator_1|start_counter[1]      ; 2       ;
; clock_generator:clock_generator_1|start_counter[2]      ; 2       ;
; clock_generator:clock_generator_1|start_counter[3]      ; 2       ;
; clock_generator:clock_generator_1|start_counter[4]      ; 2       ;
; clock_generator:clock_generator_1|start_counter[5]      ; 2       ;
; clock_generator:clock_generator_1|start_counter[6]      ; 2       ;
; clock_generator:clock_generator_1|start_counter[7]      ; 2       ;
; clock_generator:clock_generator_1|start_counter[8]      ; 2       ;
; clock_generator:clock_generator_1|start_counter[9]      ; 2       ;
; clock_generator:clock_generator_1|start_counter[10]     ; 2       ;
; clock_generator:clock_generator_1|start_counter[11]     ; 2       ;
; clock_generator:clock_generator_1|start_counter[12]     ; 2       ;
; clock_generator:clock_generator_1|start_counter[13]     ; 2       ;
; clock_generator:clock_generator_1|start_counter[14]     ; 2       ;
; clock_generator:clock_generator_1|start_counter[15]     ; 2       ;
; clock_generator:clock_generator_1|start_counter[16]     ; 2       ;
; clock_generator:clock_generator_1|start_counter[17]     ; 2       ;
; clock_generator:clock_generator_1|start_counter[18]     ; 2       ;
; clock_generator:clock_generator_1|start_counter[19]     ; 2       ;
; clock_generator:clock_generator_1|start_counter[20]     ; 2       ;
; clock_generator:clock_generator_1|start_counter[21]     ; 2       ;
; clock_generator:clock_generator_1|start_counter[22]     ; 2       ;
; clock_generator:clock_generator_1|start_counter[23]     ; 2       ;
; clock_generator:clock_generator_1|start_counter[24]     ; 2       ;
; clock_generator:clock_generator_1|start_counter[25]     ; 2       ;
; audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~en ; 1       ;
; MMI:MMI_1|mmi_controller:mmi_controller_1|lcd_1[5]      ; 1       ;
; Total number of inverted registers = 30                 ;         ;
+---------------------------------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                                                                     ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------------------------------------------------------+
; 3:1                ; 39 bits   ; 78 LEs        ; 0 LEs                ; 78 LEs                 ; Yes        ; |Equalizer|audio_unit:audio_unit_1|filter_unit:filter_unit_1|vmb[10]                                                 ;
; 3:1                ; 24 bits   ; 48 LEs        ; 24 LEs               ; 24 LEs                 ; Yes        ; |Equalizer|audio_unit:audio_unit_1|filter_unit:filter_unit_1|vma[2]                                                  ;
; 3:1                ; 24 bits   ; 48 LEs        ; 0 LEs                ; 48 LEs                 ; Yes        ; |Equalizer|audio_unit:audio_unit_1|filter_unit:filter_unit_1|idn[2]                                                  ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |Equalizer|MMI:MMI_1|mmi_controller:mmi_controller_1|filter_ten[1]                                                   ;
; 3:1                ; 28 bits   ; 56 LEs        ; 28 LEs               ; 28 LEs                 ; Yes        ; |Equalizer|MMI:MMI_1|mmi_controller:mmi_controller_1|clk_counter[23]                                                 ;
; 3:1                ; 5 bits    ; 10 LEs        ; 5 LEs                ; 5 LEs                  ; Yes        ; |Equalizer|audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_left[1]                       ;
; 3:1                ; 5 bits    ; 10 LEs        ; 5 LEs                ; 5 LEs                  ; Yes        ; |Equalizer|audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|counter_right[0]                      ;
; 3:1                ; 12 bits   ; 24 LEs        ; 12 LEs               ; 12 LEs                 ; Yes        ; |Equalizer|audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_left[0]                                         ;
; 3:1                ; 12 bits   ; 24 LEs        ; 12 LEs               ; 12 LEs                 ; Yes        ; |Equalizer|audio_unit:audio_unit_1|filter_unit:filter_unit_1|counter_right[11]                                       ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |Equalizer|audio_unit:audio_unit_1|i2c_master:i2c_master_1|Byte[1]                                                   ;
; 4:1                ; 5 bits    ; 10 LEs        ; 5 LEs                ; 5 LEs                  ; Yes        ; |Equalizer|MMI:MMI_1|lcd_controller:lcd_controller_1|counter[4]                                                      ;
; 4:1                ; 24 bits   ; 48 LEs        ; 48 LEs               ; 0 LEs                  ; Yes        ; |Equalizer|audio_unit:audio_unit_1|audio_input_register:audio_input_register_1|data[13]                              ;
; 3:1                ; 24 bits   ; 48 LEs        ; 24 LEs               ; 24 LEs                 ; Yes        ; |Equalizer|audio_unit:audio_unit_1|filter_unit:filter_unit_1|idm[3]                                                  ;
; 4:1                ; 5 bits    ; 10 LEs        ; 5 LEs                ; 5 LEs                  ; Yes        ; |Equalizer|audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_left[0]           ;
; 4:1                ; 5 bits    ; 10 LEs        ; 5 LEs                ; 5 LEs                  ; Yes        ; |Equalizer|audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:counter_right[4]          ;
; 4:1                ; 23 bits   ; 46 LEs        ; 23 LEs               ; 23 LEs                 ; Yes        ; |Equalizer|audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdr[18]                   ;
; 4:1                ; 23 bits   ; 46 LEs        ; 23 LEs               ; 23 LEs                 ; Yes        ; |Equalizer|audio_unit:audio_unit_1|audio_output_register:audio_output_register_1|\transmit:sdl[1]                    ;
; 17:1               ; 8 bits    ; 88 LEs        ; 80 LEs               ; 8 LEs                  ; Yes        ; |Equalizer|MMI:MMI_1|mmi_controller:mmi_controller_1|lcd_3[2]                                                        ;
; 17:1               ; 8 bits    ; 88 LEs        ; 80 LEs               ; 8 LEs                  ; Yes        ; |Equalizer|MMI:MMI_1|mmi_controller:mmi_controller_1|filter_ones[3]                                                  ;
; 7:1                ; 3 bits    ; 12 LEs        ; 9 LEs                ; 3 LEs                  ; Yes        ; |Equalizer|MMI:MMI_1|mmi_controller:mmi_controller_1|filter[3]                                                       ;
; 12:1               ; 3 bits    ; 24 LEs        ; 18 LEs               ; 6 LEs                  ; Yes        ; |Equalizer|MMI:MMI_1|lcd_controller:lcd_controller_1|index[2]                                                        ;
; 12:1               ; 20 bits   ; 160 LEs       ; 20 LEs               ; 140 LEs                ; Yes        ; |Equalizer|MMI:MMI_1|lcd_controller:lcd_controller_1|delay[12]                                                       ;
; 256:1              ; 10 bits   ; 1700 LEs      ; 400 LEs              ; 1300 LEs               ; Yes        ; |Equalizer|MMI:MMI_1|mmi_controller:mmi_controller_1|lcd_4[1]                                                        ;
; 256:1              ; 5 bits    ; 850 LEs       ; 10 LEs               ; 840 LEs                ; Yes        ; |Equalizer|audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|mul_b_1[59]                                  ;
; 256:1              ; 24 bits   ; 4080 LEs      ; 24 LEs               ; 4056 LEs               ; Yes        ; |Equalizer|audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|mul_a_2[14]                                  ;
; 256:1              ; 76 bits   ; 12920 LEs     ; 152 LEs              ; 12768 LEs              ; Yes        ; |Equalizer|audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|mul_b_1[31]                                  ;
; 256:1              ; 59 bits   ; 10030 LEs     ; 531 LEs              ; 9499 LEs               ; Yes        ; |Equalizer|audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_a[16] ;
; 256:1              ; 39 bits   ; 6630 LEs      ; 0 LEs                ; 6630 LEs               ; Yes        ; |Equalizer|audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|mul_b[28] ;
; 256:1              ; 8 bits    ; 1360 LEs      ; 72 LEs               ; 1288 LEs               ; Yes        ; |Equalizer|audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|g[2]      ;
; 7:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |Equalizer|MMI:MMI_1|mmi_controller:mmi_controller_1|vol_db[1]                                                       ;
; 7:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |Equalizer|MMI:MMI_1|mmi_controller:mmi_controller_1|f1_db[6]                                                        ;
; 7:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |Equalizer|MMI:MMI_1|mmi_controller:mmi_controller_1|f2_db[5]                                                        ;
; 7:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |Equalizer|MMI:MMI_1|mmi_controller:mmi_controller_1|f3_db[1]                                                        ;
; 7:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |Equalizer|MMI:MMI_1|mmi_controller:mmi_controller_1|f4_db[1]                                                        ;
; 7:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |Equalizer|MMI:MMI_1|mmi_controller:mmi_controller_1|f5_db[4]                                                        ;
; 7:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |Equalizer|MMI:MMI_1|mmi_controller:mmi_controller_1|f6_db[0]                                                        ;
; 7:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |Equalizer|MMI:MMI_1|mmi_controller:mmi_controller_1|f7_db[2]                                                        ;
; 7:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |Equalizer|MMI:MMI_1|mmi_controller:mmi_controller_1|f8_db[1]                                                        ;
; 7:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |Equalizer|MMI:MMI_1|mmi_controller:mmi_controller_1|f9_db[1]                                                        ;
; 7:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |Equalizer|MMI:MMI_1|mmi_controller:mmi_controller_1|f10_db[5]                                                       ;
; 7:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |Equalizer|MMI:MMI_1|mmi_controller:mmi_controller_1|f11_db[2]                                                       ;
; 7:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |Equalizer|MMI:MMI_1|mmi_controller:mmi_controller_1|f12_db[4]                                                       ;
; 7:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |Equalizer|MMI:MMI_1|mmi_controller:mmi_controller_1|f13_db[3]                                                       ;
; 7:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |Equalizer|MMI:MMI_1|mmi_controller:mmi_controller_1|f14_db[6]                                                       ;
; 130:1              ; 7 bits    ; 602 LEs       ; 14 LEs               ; 588 LEs                ; Yes        ; |Equalizer|audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|mul_b_1[0]                                   ;
; 257:1              ; 13 bits   ; 2223 LEs      ; 520 LEs              ; 1703 LEs               ; Yes        ; |Equalizer|MMI:MMI_1|mmi_controller:mmi_controller_1|db_ten[2]                                                       ;
; 3:1                ; 26 bits   ; 52 LEs        ; 26 LEs               ; 26 LEs                 ; Yes        ; |Equalizer|clock_generator:clock_generator_1|start_counter[25]                                                       ;
; 4:1                ; 16 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; No         ; |Equalizer|MMI:MMI_1|mmi_controller:mmi_controller_1|Mux241                                                          ;
; 8:1                ; 8 bits    ; 40 LEs        ; 40 LEs               ; 0 LEs                  ; No         ; |Equalizer|MMI:MMI_1|mmi_controller:mmi_controller_1|Mux247                                                          ;
; 9:1                ; 8 bits    ; 48 LEs        ; 40 LEs               ; 8 LEs                  ; No         ; |Equalizer|MMI:MMI_1|mmi_controller:mmi_controller_1|tmp                                                             ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: clock_generator:clock_generator_1|EQ_PLL_50:pll_1|altpll:altpll_component ;
+-------------------------------+-----------------------------+----------------------------------------------------------+
; Parameter Name                ; Value                       ; Type                                                     ;
+-------------------------------+-----------------------------+----------------------------------------------------------+
; OPERATION_MODE                ; NORMAL                      ; Untyped                                                  ;
; PLL_TYPE                      ; AUTO                        ; Untyped                                                  ;
; LPM_HINT                      ; CBX_MODULE_PREFIX=EQ_PLL_50 ; Untyped                                                  ;
; QUALIFY_CONF_DONE             ; OFF                         ; Untyped                                                  ;
; COMPENSATE_CLOCK              ; CLK0                        ; Untyped                                                  ;
; SCAN_CHAIN                    ; LONG                        ; Untyped                                                  ;
; PRIMARY_CLOCK                 ; INCLK0                      ; Untyped                                                  ;
; INCLK0_INPUT_FREQUENCY        ; 20000                       ; Signed Integer                                           ;
; INCLK1_INPUT_FREQUENCY        ; 0                           ; Untyped                                                  ;
; GATE_LOCK_SIGNAL              ; NO                          ; Untyped                                                  ;
; GATE_LOCK_COUNTER             ; 0                           ; Untyped                                                  ;
; LOCK_HIGH                     ; 1                           ; Untyped                                                  ;
; LOCK_LOW                      ; 1                           ; Untyped                                                  ;
; VALID_LOCK_MULTIPLIER         ; 1                           ; Untyped                                                  ;
; INVALID_LOCK_MULTIPLIER       ; 5                           ; Untyped                                                  ;
; SWITCH_OVER_ON_LOSSCLK        ; OFF                         ; Untyped                                                  ;
; SWITCH_OVER_ON_GATED_LOCK     ; OFF                         ; Untyped                                                  ;
; ENABLE_SWITCH_OVER_COUNTER    ; OFF                         ; Untyped                                                  ;
; SKIP_VCO                      ; OFF                         ; Untyped                                                  ;
; SWITCH_OVER_COUNTER           ; 0                           ; Untyped                                                  ;
; SWITCH_OVER_TYPE              ; AUTO                        ; Untyped                                                  ;
; FEEDBACK_SOURCE               ; EXTCLK0                     ; Untyped                                                  ;
; BANDWIDTH                     ; 0                           ; Untyped                                                  ;
; BANDWIDTH_TYPE                ; AUTO                        ; Untyped                                                  ;
; SPREAD_FREQUENCY              ; 0                           ; Untyped                                                  ;
; DOWN_SPREAD                   ; 0                           ; Untyped                                                  ;
; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF                         ; Untyped                                                  ;
; SELF_RESET_ON_LOSS_LOCK       ; OFF                         ; Untyped                                                  ;
; CLK9_MULTIPLY_BY              ; 0                           ; Untyped                                                  ;
; CLK8_MULTIPLY_BY              ; 0                           ; Untyped                                                  ;
; CLK7_MULTIPLY_BY              ; 0                           ; Untyped                                                  ;
; CLK6_MULTIPLY_BY              ; 0                           ; Untyped                                                  ;
; CLK5_MULTIPLY_BY              ; 1                           ; Untyped                                                  ;
; CLK4_MULTIPLY_BY              ; 1                           ; Untyped                                                  ;
; CLK3_MULTIPLY_BY              ; 1                           ; Untyped                                                  ;
; CLK2_MULTIPLY_BY              ; 1                           ; Untyped                                                  ;
; CLK1_MULTIPLY_BY              ; 1                           ; Signed Integer                                           ;
; CLK0_MULTIPLY_BY              ; 1                           ; Signed Integer                                           ;
; CLK9_DIVIDE_BY                ; 0                           ; Untyped                                                  ;
; CLK8_DIVIDE_BY                ; 0                           ; Untyped                                                  ;
; CLK7_DIVIDE_BY                ; 0                           ; Untyped                                                  ;
; CLK6_DIVIDE_BY                ; 0                           ; Untyped                                                  ;
; CLK5_DIVIDE_BY                ; 1                           ; Untyped                                                  ;
; CLK4_DIVIDE_BY                ; 1                           ; Untyped                                                  ;
; CLK3_DIVIDE_BY                ; 1                           ; Untyped                                                  ;
; CLK2_DIVIDE_BY                ; 1                           ; Untyped                                                  ;
; CLK1_DIVIDE_BY                ; 5                           ; Signed Integer                                           ;
; CLK0_DIVIDE_BY                ; 1                           ; Signed Integer                                           ;
; CLK9_PHASE_SHIFT              ; 0                           ; Untyped                                                  ;
; CLK8_PHASE_SHIFT              ; 0                           ; Untyped                                                  ;
; CLK7_PHASE_SHIFT              ; 0                           ; Untyped                                                  ;
; CLK6_PHASE_SHIFT              ; 0                           ; Untyped                                                  ;
; CLK5_PHASE_SHIFT              ; 0                           ; Untyped                                                  ;
; CLK4_PHASE_SHIFT              ; 0                           ; Untyped                                                  ;
; CLK3_PHASE_SHIFT              ; 0                           ; Untyped                                                  ;
; CLK2_PHASE_SHIFT              ; 0                           ; Untyped                                                  ;
; CLK1_PHASE_SHIFT              ; 0                           ; Untyped                                                  ;
; CLK0_PHASE_SHIFT              ; 0                           ; Untyped                                                  ;
; CLK5_TIME_DELAY               ; 0                           ; Untyped                                                  ;
; CLK4_TIME_DELAY               ; 0                           ; Untyped                                                  ;
; CLK3_TIME_DELAY               ; 0                           ; Untyped                                                  ;
; CLK2_TIME_DELAY               ; 0                           ; Untyped                                                  ;
; CLK1_TIME_DELAY               ; 0                           ; Untyped                                                  ;
; CLK0_TIME_DELAY               ; 0                           ; Untyped                                                  ;
; CLK9_DUTY_CYCLE               ; 50                          ; Untyped                                                  ;
; CLK8_DUTY_CYCLE               ; 50                          ; Untyped                                                  ;
; CLK7_DUTY_CYCLE               ; 50                          ; Untyped                                                  ;
; CLK6_DUTY_CYCLE               ; 50                          ; Untyped                                                  ;
; CLK5_DUTY_CYCLE               ; 50                          ; Untyped                                                  ;
; CLK4_DUTY_CYCLE               ; 50                          ; Untyped                                                  ;
; CLK3_DUTY_CYCLE               ; 50                          ; Untyped                                                  ;
; CLK2_DUTY_CYCLE               ; 50                          ; Untyped                                                  ;
; CLK1_DUTY_CYCLE               ; 50                          ; Signed Integer                                           ;
; CLK0_DUTY_CYCLE               ; 50                          ; Signed Integer                                           ;
; CLK9_USE_EVEN_COUNTER_MODE    ; OFF                         ; Untyped                                                  ;
; CLK8_USE_EVEN_COUNTER_MODE    ; OFF                         ; Untyped                                                  ;
; CLK7_USE_EVEN_COUNTER_MODE    ; OFF                         ; Untyped                                                  ;
; CLK6_USE_EVEN_COUNTER_MODE    ; OFF                         ; Untyped                                                  ;
; CLK5_USE_EVEN_COUNTER_MODE    ; OFF                         ; Untyped                                                  ;
; CLK4_USE_EVEN_COUNTER_MODE    ; OFF                         ; Untyped                                                  ;
; CLK3_USE_EVEN_COUNTER_MODE    ; OFF                         ; Untyped                                                  ;
; CLK2_USE_EVEN_COUNTER_MODE    ; OFF                         ; Untyped                                                  ;
; CLK1_USE_EVEN_COUNTER_MODE    ; OFF                         ; Untyped                                                  ;
; CLK0_USE_EVEN_COUNTER_MODE    ; OFF                         ; Untyped                                                  ;
; CLK9_USE_EVEN_COUNTER_VALUE   ; OFF                         ; Untyped                                                  ;
; CLK8_USE_EVEN_COUNTER_VALUE   ; OFF                         ; Untyped                                                  ;
; CLK7_USE_EVEN_COUNTER_VALUE   ; OFF                         ; Untyped                                                  ;
; CLK6_USE_EVEN_COUNTER_VALUE   ; OFF                         ; Untyped                                                  ;
; CLK5_USE_EVEN_COUNTER_VALUE   ; OFF                         ; Untyped                                                  ;
; CLK4_USE_EVEN_COUNTER_VALUE   ; OFF                         ; Untyped                                                  ;
; CLK3_USE_EVEN_COUNTER_VALUE   ; OFF                         ; Untyped                                                  ;
; CLK2_USE_EVEN_COUNTER_VALUE   ; OFF                         ; Untyped                                                  ;
; CLK1_USE_EVEN_COUNTER_VALUE   ; OFF                         ; Untyped                                                  ;
; CLK0_USE_EVEN_COUNTER_VALUE   ; OFF                         ; Untyped                                                  ;
; LOCK_WINDOW_UI                ;  0.05                       ; Untyped                                                  ;
; LOCK_WINDOW_UI_BITS           ; UNUSED                      ; Untyped                                                  ;
; VCO_RANGE_DETECTOR_LOW_BITS   ; UNUSED                      ; Untyped                                                  ;
; VCO_RANGE_DETECTOR_HIGH_BITS  ; UNUSED                      ; Untyped                                                  ;
; DPA_MULTIPLY_BY               ; 0                           ; Untyped                                                  ;
; DPA_DIVIDE_BY                 ; 1                           ; Untyped                                                  ;
; DPA_DIVIDER                   ; 0                           ; Untyped                                                  ;
; EXTCLK3_MULTIPLY_BY           ; 1                           ; Untyped                                                  ;
; EXTCLK2_MULTIPLY_BY           ; 1                           ; Untyped                                                  ;
; EXTCLK1_MULTIPLY_BY           ; 1                           ; Untyped                                                  ;
; EXTCLK0_MULTIPLY_BY           ; 1                           ; Untyped                                                  ;
; EXTCLK3_DIVIDE_BY             ; 1                           ; Untyped                                                  ;
; EXTCLK2_DIVIDE_BY             ; 1                           ; Untyped                                                  ;
; EXTCLK1_DIVIDE_BY             ; 1                           ; Untyped                                                  ;
; EXTCLK0_DIVIDE_BY             ; 1                           ; Untyped                                                  ;
; EXTCLK3_PHASE_SHIFT           ; 0                           ; Untyped                                                  ;
; EXTCLK2_PHASE_SHIFT           ; 0                           ; Untyped                                                  ;
; EXTCLK1_PHASE_SHIFT           ; 0                           ; Untyped                                                  ;
; EXTCLK0_PHASE_SHIFT           ; 0                           ; Untyped                                                  ;
; EXTCLK3_TIME_DELAY            ; 0                           ; Untyped                                                  ;
; EXTCLK2_TIME_DELAY            ; 0                           ; Untyped                                                  ;
; EXTCLK1_TIME_DELAY            ; 0                           ; Untyped                                                  ;
; EXTCLK0_TIME_DELAY            ; 0                           ; Untyped                                                  ;
; EXTCLK3_DUTY_CYCLE            ; 50                          ; Untyped                                                  ;
; EXTCLK2_DUTY_CYCLE            ; 50                          ; Untyped                                                  ;
; EXTCLK1_DUTY_CYCLE            ; 50                          ; Untyped                                                  ;
; EXTCLK0_DUTY_CYCLE            ; 50                          ; Untyped                                                  ;
; VCO_MULTIPLY_BY               ; 0                           ; Untyped                                                  ;
; VCO_DIVIDE_BY                 ; 0                           ; Untyped                                                  ;
; SCLKOUT0_PHASE_SHIFT          ; 0                           ; Untyped                                                  ;
; SCLKOUT1_PHASE_SHIFT          ; 0                           ; Untyped                                                  ;
; VCO_MIN                       ; 0                           ; Untyped                                                  ;
; VCO_MAX                       ; 0                           ; Untyped                                                  ;
; VCO_CENTER                    ; 0                           ; Untyped                                                  ;
; PFD_MIN                       ; 0                           ; Untyped                                                  ;
; PFD_MAX                       ; 0                           ; Untyped                                                  ;
; M_INITIAL                     ; 0                           ; Untyped                                                  ;
; M                             ; 0                           ; Untyped                                                  ;
; N                             ; 1                           ; Untyped                                                  ;
; M2                            ; 1                           ; Untyped                                                  ;
; N2                            ; 1                           ; Untyped                                                  ;
; SS                            ; 1                           ; Untyped                                                  ;
; C0_HIGH                       ; 0                           ; Untyped                                                  ;
; C1_HIGH                       ; 0                           ; Untyped                                                  ;
; C2_HIGH                       ; 0                           ; Untyped                                                  ;
; C3_HIGH                       ; 0                           ; Untyped                                                  ;
; C4_HIGH                       ; 0                           ; Untyped                                                  ;
; C5_HIGH                       ; 0                           ; Untyped                                                  ;
; C6_HIGH                       ; 0                           ; Untyped                                                  ;
; C7_HIGH                       ; 0                           ; Untyped                                                  ;
; C8_HIGH                       ; 0                           ; Untyped                                                  ;
; C9_HIGH                       ; 0                           ; Untyped                                                  ;
; C0_LOW                        ; 0                           ; Untyped                                                  ;
; C1_LOW                        ; 0                           ; Untyped                                                  ;
; C2_LOW                        ; 0                           ; Untyped                                                  ;
; C3_LOW                        ; 0                           ; Untyped                                                  ;
; C4_LOW                        ; 0                           ; Untyped                                                  ;
; C5_LOW                        ; 0                           ; Untyped                                                  ;
; C6_LOW                        ; 0                           ; Untyped                                                  ;
; C7_LOW                        ; 0                           ; Untyped                                                  ;
; C8_LOW                        ; 0                           ; Untyped                                                  ;
; C9_LOW                        ; 0                           ; Untyped                                                  ;
; C0_INITIAL                    ; 0                           ; Untyped                                                  ;
; C1_INITIAL                    ; 0                           ; Untyped                                                  ;
; C2_INITIAL                    ; 0                           ; Untyped                                                  ;
; C3_INITIAL                    ; 0                           ; Untyped                                                  ;
; C4_INITIAL                    ; 0                           ; Untyped                                                  ;
; C5_INITIAL                    ; 0                           ; Untyped                                                  ;
; C6_INITIAL                    ; 0                           ; Untyped                                                  ;
; C7_INITIAL                    ; 0                           ; Untyped                                                  ;
; C8_INITIAL                    ; 0                           ; Untyped                                                  ;
; C9_INITIAL                    ; 0                           ; Untyped                                                  ;
; C0_MODE                       ; BYPASS                      ; Untyped                                                  ;
; C1_MODE                       ; BYPASS                      ; Untyped                                                  ;
; C2_MODE                       ; BYPASS                      ; Untyped                                                  ;
; C3_MODE                       ; BYPASS                      ; Untyped                                                  ;
; C4_MODE                       ; BYPASS                      ; Untyped                                                  ;
; C5_MODE                       ; BYPASS                      ; Untyped                                                  ;
; C6_MODE                       ; BYPASS                      ; Untyped                                                  ;
; C7_MODE                       ; BYPASS                      ; Untyped                                                  ;
; C8_MODE                       ; BYPASS                      ; Untyped                                                  ;
; C9_MODE                       ; BYPASS                      ; Untyped                                                  ;
; C0_PH                         ; 0                           ; Untyped                                                  ;
; C1_PH                         ; 0                           ; Untyped                                                  ;
; C2_PH                         ; 0                           ; Untyped                                                  ;
; C3_PH                         ; 0                           ; Untyped                                                  ;
; C4_PH                         ; 0                           ; Untyped                                                  ;
; C5_PH                         ; 0                           ; Untyped                                                  ;
; C6_PH                         ; 0                           ; Untyped                                                  ;
; C7_PH                         ; 0                           ; Untyped                                                  ;
; C8_PH                         ; 0                           ; Untyped                                                  ;
; C9_PH                         ; 0                           ; Untyped                                                  ;
; L0_HIGH                       ; 1                           ; Untyped                                                  ;
; L1_HIGH                       ; 1                           ; Untyped                                                  ;
; G0_HIGH                       ; 1                           ; Untyped                                                  ;
; G1_HIGH                       ; 1                           ; Untyped                                                  ;
; G2_HIGH                       ; 1                           ; Untyped                                                  ;
; G3_HIGH                       ; 1                           ; Untyped                                                  ;
; E0_HIGH                       ; 1                           ; Untyped                                                  ;
; E1_HIGH                       ; 1                           ; Untyped                                                  ;
; E2_HIGH                       ; 1                           ; Untyped                                                  ;
; E3_HIGH                       ; 1                           ; Untyped                                                  ;
; L0_LOW                        ; 1                           ; Untyped                                                  ;
; L1_LOW                        ; 1                           ; Untyped                                                  ;
; G0_LOW                        ; 1                           ; Untyped                                                  ;
; G1_LOW                        ; 1                           ; Untyped                                                  ;
; G2_LOW                        ; 1                           ; Untyped                                                  ;
; G3_LOW                        ; 1                           ; Untyped                                                  ;
; E0_LOW                        ; 1                           ; Untyped                                                  ;
; E1_LOW                        ; 1                           ; Untyped                                                  ;
; E2_LOW                        ; 1                           ; Untyped                                                  ;
; E3_LOW                        ; 1                           ; Untyped                                                  ;
; L0_INITIAL                    ; 1                           ; Untyped                                                  ;
; L1_INITIAL                    ; 1                           ; Untyped                                                  ;
; G0_INITIAL                    ; 1                           ; Untyped                                                  ;
; G1_INITIAL                    ; 1                           ; Untyped                                                  ;
; G2_INITIAL                    ; 1                           ; Untyped                                                  ;
; G3_INITIAL                    ; 1                           ; Untyped                                                  ;
; E0_INITIAL                    ; 1                           ; Untyped                                                  ;
; E1_INITIAL                    ; 1                           ; Untyped                                                  ;
; E2_INITIAL                    ; 1                           ; Untyped                                                  ;
; E3_INITIAL                    ; 1                           ; Untyped                                                  ;
; L0_MODE                       ; BYPASS                      ; Untyped                                                  ;
; L1_MODE                       ; BYPASS                      ; Untyped                                                  ;
; G0_MODE                       ; BYPASS                      ; Untyped                                                  ;
; G1_MODE                       ; BYPASS                      ; Untyped                                                  ;
; G2_MODE                       ; BYPASS                      ; Untyped                                                  ;
; G3_MODE                       ; BYPASS                      ; Untyped                                                  ;
; E0_MODE                       ; BYPASS                      ; Untyped                                                  ;
; E1_MODE                       ; BYPASS                      ; Untyped                                                  ;
; E2_MODE                       ; BYPASS                      ; Untyped                                                  ;
; E3_MODE                       ; BYPASS                      ; Untyped                                                  ;
; L0_PH                         ; 0                           ; Untyped                                                  ;
; L1_PH                         ; 0                           ; Untyped                                                  ;
; G0_PH                         ; 0                           ; Untyped                                                  ;
; G1_PH                         ; 0                           ; Untyped                                                  ;
; G2_PH                         ; 0                           ; Untyped                                                  ;
; G3_PH                         ; 0                           ; Untyped                                                  ;
; E0_PH                         ; 0                           ; Untyped                                                  ;
; E1_PH                         ; 0                           ; Untyped                                                  ;
; E2_PH                         ; 0                           ; Untyped                                                  ;
; E3_PH                         ; 0                           ; Untyped                                                  ;
; M_PH                          ; 0                           ; Untyped                                                  ;
; C1_USE_CASC_IN                ; OFF                         ; Untyped                                                  ;
; C2_USE_CASC_IN                ; OFF                         ; Untyped                                                  ;
; C3_USE_CASC_IN                ; OFF                         ; Untyped                                                  ;
; C4_USE_CASC_IN                ; OFF                         ; Untyped                                                  ;
; C5_USE_CASC_IN                ; OFF                         ; Untyped                                                  ;
; C6_USE_CASC_IN                ; OFF                         ; Untyped                                                  ;
; C7_USE_CASC_IN                ; OFF                         ; Untyped                                                  ;
; C8_USE_CASC_IN                ; OFF                         ; Untyped                                                  ;
; C9_USE_CASC_IN                ; OFF                         ; Untyped                                                  ;
; CLK0_COUNTER                  ; G0                          ; Untyped                                                  ;
; CLK1_COUNTER                  ; G0                          ; Untyped                                                  ;
; CLK2_COUNTER                  ; G0                          ; Untyped                                                  ;
; CLK3_COUNTER                  ; G0                          ; Untyped                                                  ;
; CLK4_COUNTER                  ; G0                          ; Untyped                                                  ;
; CLK5_COUNTER                  ; G0                          ; Untyped                                                  ;
; CLK6_COUNTER                  ; E0                          ; Untyped                                                  ;
; CLK7_COUNTER                  ; E1                          ; Untyped                                                  ;
; CLK8_COUNTER                  ; E2                          ; Untyped                                                  ;
; CLK9_COUNTER                  ; E3                          ; Untyped                                                  ;
; L0_TIME_DELAY                 ; 0                           ; Untyped                                                  ;
; L1_TIME_DELAY                 ; 0                           ; Untyped                                                  ;
; G0_TIME_DELAY                 ; 0                           ; Untyped                                                  ;
; G1_TIME_DELAY                 ; 0                           ; Untyped                                                  ;
; G2_TIME_DELAY                 ; 0                           ; Untyped                                                  ;
; G3_TIME_DELAY                 ; 0                           ; Untyped                                                  ;
; E0_TIME_DELAY                 ; 0                           ; Untyped                                                  ;
; E1_TIME_DELAY                 ; 0                           ; Untyped                                                  ;
; E2_TIME_DELAY                 ; 0                           ; Untyped                                                  ;
; E3_TIME_DELAY                 ; 0                           ; Untyped                                                  ;
; M_TIME_DELAY                  ; 0                           ; Untyped                                                  ;
; N_TIME_DELAY                  ; 0                           ; Untyped                                                  ;
; EXTCLK3_COUNTER               ; E3                          ; Untyped                                                  ;
; EXTCLK2_COUNTER               ; E2                          ; Untyped                                                  ;
; EXTCLK1_COUNTER               ; E1                          ; Untyped                                                  ;
; EXTCLK0_COUNTER               ; E0                          ; Untyped                                                  ;
; ENABLE0_COUNTER               ; L0                          ; Untyped                                                  ;
; ENABLE1_COUNTER               ; L0                          ; Untyped                                                  ;
; CHARGE_PUMP_CURRENT           ; 2                           ; Untyped                                                  ;
; LOOP_FILTER_R                 ;  1.000000                   ; Untyped                                                  ;
; LOOP_FILTER_C                 ; 5                           ; Untyped                                                  ;
; CHARGE_PUMP_CURRENT_BITS      ; 9999                        ; Untyped                                                  ;
; LOOP_FILTER_R_BITS            ; 9999                        ; Untyped                                                  ;
; LOOP_FILTER_C_BITS            ; 9999                        ; Untyped                                                  ;
; VCO_POST_SCALE                ; 0                           ; Untyped                                                  ;
; CLK2_OUTPUT_FREQUENCY         ; 0                           ; Untyped                                                  ;
; CLK1_OUTPUT_FREQUENCY         ; 0                           ; Untyped                                                  ;
; CLK0_OUTPUT_FREQUENCY         ; 0                           ; Untyped                                                  ;
; INTENDED_DEVICE_FAMILY        ; Cyclone II                  ; Untyped                                                  ;
; PORT_CLKENA0                  ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_CLKENA1                  ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_CLKENA2                  ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_CLKENA3                  ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_CLKENA4                  ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_CLKENA5                  ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY           ; Untyped                                                  ;
; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY           ; Untyped                                                  ;
; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY           ; Untyped                                                  ;
; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY           ; Untyped                                                  ;
; PORT_EXTCLK0                  ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_EXTCLK1                  ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_EXTCLK2                  ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_EXTCLK3                  ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_CLKBAD0                  ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_CLKBAD1                  ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_CLK0                     ; PORT_USED                   ; Untyped                                                  ;
; PORT_CLK1                     ; PORT_USED                   ; Untyped                                                  ;
; PORT_CLK2                     ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_CLK3                     ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_CLK4                     ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_CLK5                     ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_CLK6                     ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_CLK7                     ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_CLK8                     ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_CLK9                     ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_SCANDATA                 ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_SCANDATAOUT              ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_SCANDONE                 ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY           ; Untyped                                                  ;
; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY           ; Untyped                                                  ;
; PORT_ACTIVECLOCK              ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_CLKLOSS                  ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_INCLK1                   ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_INCLK0                   ; PORT_USED                   ; Untyped                                                  ;
; PORT_FBIN                     ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_PLLENA                   ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_CLKSWITCH                ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_ARESET                   ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_PFDENA                   ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_SCANCLK                  ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_SCANACLR                 ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_SCANREAD                 ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_SCANWRITE                ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_ENABLE0                  ; PORT_CONNECTIVITY           ; Untyped                                                  ;
; PORT_ENABLE1                  ; PORT_CONNECTIVITY           ; Untyped                                                  ;
; PORT_LOCKED                   ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_CONFIGUPDATE             ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_FBOUT                    ; PORT_CONNECTIVITY           ; Untyped                                                  ;
; PORT_PHASEDONE                ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_PHASESTEP                ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_PHASEUPDOWN              ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_SCANCLKENA               ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_PHASECOUNTERSELECT       ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_VCOOVERRANGE             ; PORT_CONNECTIVITY           ; Untyped                                                  ;
; PORT_VCOUNDERRANGE            ; PORT_CONNECTIVITY           ; Untyped                                                  ;
; M_TEST_SOURCE                 ; 5                           ; Untyped                                                  ;
; C0_TEST_SOURCE                ; 5                           ; Untyped                                                  ;
; C1_TEST_SOURCE                ; 5                           ; Untyped                                                  ;
; C2_TEST_SOURCE                ; 5                           ; Untyped                                                  ;
; C3_TEST_SOURCE                ; 5                           ; Untyped                                                  ;
; C4_TEST_SOURCE                ; 5                           ; Untyped                                                  ;
; C5_TEST_SOURCE                ; 5                           ; Untyped                                                  ;
; C6_TEST_SOURCE                ; 5                           ; Untyped                                                  ;
; C7_TEST_SOURCE                ; 5                           ; Untyped                                                  ;
; C8_TEST_SOURCE                ; 5                           ; Untyped                                                  ;
; C9_TEST_SOURCE                ; 5                           ; Untyped                                                  ;
; CBXI_PARAMETER                ; NOTHING                     ; Untyped                                                  ;
; VCO_FREQUENCY_CONTROL         ; AUTO                        ; Untyped                                                  ;
; VCO_PHASE_SHIFT_STEP          ; 0                           ; Untyped                                                  ;
; WIDTH_CLOCK                   ; 6                           ; Untyped                                                  ;
; WIDTH_PHASECOUNTERSELECT      ; 4                           ; Untyped                                                  ;
; USING_FBMIMICBIDIR_PORT       ; OFF                         ; Untyped                                                  ;
; DEVICE_FAMILY                 ; Cyclone II                  ; Untyped                                                  ;
; SCAN_CHAIN_MIF_FILE           ; UNUSED                      ; Untyped                                                  ;
; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF                         ; Untyped                                                  ;
; AUTO_CARRY_CHAINS             ; ON                          ; AUTO_CARRY                                               ;
; IGNORE_CARRY_BUFFERS          ; OFF                         ; IGNORE_CARRY                                             ;
; AUTO_CASCADE_CHAINS           ; ON                          ; AUTO_CASCADE                                             ;
; IGNORE_CASCADE_BUFFERS        ; OFF                         ; IGNORE_CASCADE                                           ;
+-------------------------------+-----------------------------+----------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: clock_generator:clock_generator_1|EQ_PLL_27:pll_2|altpll:altpll_component ;
+-------------------------------+-----------------------------+----------------------------------------------------------+
; Parameter Name                ; Value                       ; Type                                                     ;
+-------------------------------+-----------------------------+----------------------------------------------------------+
; OPERATION_MODE                ; NORMAL                      ; Untyped                                                  ;
; PLL_TYPE                      ; AUTO                        ; Untyped                                                  ;
; LPM_HINT                      ; CBX_MODULE_PREFIX=EQ_PLL_27 ; Untyped                                                  ;
; QUALIFY_CONF_DONE             ; OFF                         ; Untyped                                                  ;
; COMPENSATE_CLOCK              ; CLK0                        ; Untyped                                                  ;
; SCAN_CHAIN                    ; LONG                        ; Untyped                                                  ;
; PRIMARY_CLOCK                 ; INCLK0                      ; Untyped                                                  ;
; INCLK0_INPUT_FREQUENCY        ; 37037                       ; Signed Integer                                           ;
; INCLK1_INPUT_FREQUENCY        ; 0                           ; Untyped                                                  ;
; GATE_LOCK_SIGNAL              ; NO                          ; Untyped                                                  ;
; GATE_LOCK_COUNTER             ; 0                           ; Untyped                                                  ;
; LOCK_HIGH                     ; 1                           ; Untyped                                                  ;
; LOCK_LOW                      ; 1                           ; Untyped                                                  ;
; VALID_LOCK_MULTIPLIER         ; 1                           ; Untyped                                                  ;
; INVALID_LOCK_MULTIPLIER       ; 5                           ; Untyped                                                  ;
; SWITCH_OVER_ON_LOSSCLK        ; OFF                         ; Untyped                                                  ;
; SWITCH_OVER_ON_GATED_LOCK     ; OFF                         ; Untyped                                                  ;
; ENABLE_SWITCH_OVER_COUNTER    ; OFF                         ; Untyped                                                  ;
; SKIP_VCO                      ; OFF                         ; Untyped                                                  ;
; SWITCH_OVER_COUNTER           ; 0                           ; Untyped                                                  ;
; SWITCH_OVER_TYPE              ; AUTO                        ; Untyped                                                  ;
; FEEDBACK_SOURCE               ; EXTCLK0                     ; Untyped                                                  ;
; BANDWIDTH                     ; 0                           ; Untyped                                                  ;
; BANDWIDTH_TYPE                ; AUTO                        ; Untyped                                                  ;
; SPREAD_FREQUENCY              ; 0                           ; Untyped                                                  ;
; DOWN_SPREAD                   ; 0                           ; Untyped                                                  ;
; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF                         ; Untyped                                                  ;
; SELF_RESET_ON_LOSS_LOCK       ; OFF                         ; Untyped                                                  ;
; CLK9_MULTIPLY_BY              ; 0                           ; Untyped                                                  ;
; CLK8_MULTIPLY_BY              ; 0                           ; Untyped                                                  ;
; CLK7_MULTIPLY_BY              ; 0                           ; Untyped                                                  ;
; CLK6_MULTIPLY_BY              ; 0                           ; Untyped                                                  ;
; CLK5_MULTIPLY_BY              ; 1                           ; Untyped                                                  ;
; CLK4_MULTIPLY_BY              ; 1                           ; Untyped                                                  ;
; CLK3_MULTIPLY_BY              ; 1                           ; Untyped                                                  ;
; CLK2_MULTIPLY_BY              ; 1                           ; Untyped                                                  ;
; CLK1_MULTIPLY_BY              ; 4                           ; Signed Integer                                           ;
; CLK0_MULTIPLY_BY              ; 1                           ; Signed Integer                                           ;
; CLK9_DIVIDE_BY                ; 0                           ; Untyped                                                  ;
; CLK8_DIVIDE_BY                ; 0                           ; Untyped                                                  ;
; CLK7_DIVIDE_BY                ; 0                           ; Untyped                                                  ;
; CLK6_DIVIDE_BY                ; 0                           ; Untyped                                                  ;
; CLK5_DIVIDE_BY                ; 1                           ; Untyped                                                  ;
; CLK4_DIVIDE_BY                ; 1                           ; Untyped                                                  ;
; CLK3_DIVIDE_BY                ; 1                           ; Untyped                                                  ;
; CLK2_DIVIDE_BY                ; 1                           ; Untyped                                                  ;
; CLK1_DIVIDE_BY                ; 9                           ; Signed Integer                                           ;
; CLK0_DIVIDE_BY                ; 1                           ; Signed Integer                                           ;
; CLK9_PHASE_SHIFT              ; 0                           ; Untyped                                                  ;
; CLK8_PHASE_SHIFT              ; 0                           ; Untyped                                                  ;
; CLK7_PHASE_SHIFT              ; 0                           ; Untyped                                                  ;
; CLK6_PHASE_SHIFT              ; 0                           ; Untyped                                                  ;
; CLK5_PHASE_SHIFT              ; 0                           ; Untyped                                                  ;
; CLK4_PHASE_SHIFT              ; 0                           ; Untyped                                                  ;
; CLK3_PHASE_SHIFT              ; 0                           ; Untyped                                                  ;
; CLK2_PHASE_SHIFT              ; 0                           ; Untyped                                                  ;
; CLK1_PHASE_SHIFT              ; 0                           ; Untyped                                                  ;
; CLK0_PHASE_SHIFT              ; 0                           ; Untyped                                                  ;
; CLK5_TIME_DELAY               ; 0                           ; Untyped                                                  ;
; CLK4_TIME_DELAY               ; 0                           ; Untyped                                                  ;
; CLK3_TIME_DELAY               ; 0                           ; Untyped                                                  ;
; CLK2_TIME_DELAY               ; 0                           ; Untyped                                                  ;
; CLK1_TIME_DELAY               ; 0                           ; Untyped                                                  ;
; CLK0_TIME_DELAY               ; 0                           ; Untyped                                                  ;
; CLK9_DUTY_CYCLE               ; 50                          ; Untyped                                                  ;
; CLK8_DUTY_CYCLE               ; 50                          ; Untyped                                                  ;
; CLK7_DUTY_CYCLE               ; 50                          ; Untyped                                                  ;
; CLK6_DUTY_CYCLE               ; 50                          ; Untyped                                                  ;
; CLK5_DUTY_CYCLE               ; 50                          ; Untyped                                                  ;
; CLK4_DUTY_CYCLE               ; 50                          ; Untyped                                                  ;
; CLK3_DUTY_CYCLE               ; 50                          ; Untyped                                                  ;
; CLK2_DUTY_CYCLE               ; 50                          ; Untyped                                                  ;
; CLK1_DUTY_CYCLE               ; 50                          ; Signed Integer                                           ;
; CLK0_DUTY_CYCLE               ; 50                          ; Signed Integer                                           ;
; CLK9_USE_EVEN_COUNTER_MODE    ; OFF                         ; Untyped                                                  ;
; CLK8_USE_EVEN_COUNTER_MODE    ; OFF                         ; Untyped                                                  ;
; CLK7_USE_EVEN_COUNTER_MODE    ; OFF                         ; Untyped                                                  ;
; CLK6_USE_EVEN_COUNTER_MODE    ; OFF                         ; Untyped                                                  ;
; CLK5_USE_EVEN_COUNTER_MODE    ; OFF                         ; Untyped                                                  ;
; CLK4_USE_EVEN_COUNTER_MODE    ; OFF                         ; Untyped                                                  ;
; CLK3_USE_EVEN_COUNTER_MODE    ; OFF                         ; Untyped                                                  ;
; CLK2_USE_EVEN_COUNTER_MODE    ; OFF                         ; Untyped                                                  ;
; CLK1_USE_EVEN_COUNTER_MODE    ; OFF                         ; Untyped                                                  ;
; CLK0_USE_EVEN_COUNTER_MODE    ; OFF                         ; Untyped                                                  ;
; CLK9_USE_EVEN_COUNTER_VALUE   ; OFF                         ; Untyped                                                  ;
; CLK8_USE_EVEN_COUNTER_VALUE   ; OFF                         ; Untyped                                                  ;
; CLK7_USE_EVEN_COUNTER_VALUE   ; OFF                         ; Untyped                                                  ;
; CLK6_USE_EVEN_COUNTER_VALUE   ; OFF                         ; Untyped                                                  ;
; CLK5_USE_EVEN_COUNTER_VALUE   ; OFF                         ; Untyped                                                  ;
; CLK4_USE_EVEN_COUNTER_VALUE   ; OFF                         ; Untyped                                                  ;
; CLK3_USE_EVEN_COUNTER_VALUE   ; OFF                         ; Untyped                                                  ;
; CLK2_USE_EVEN_COUNTER_VALUE   ; OFF                         ; Untyped                                                  ;
; CLK1_USE_EVEN_COUNTER_VALUE   ; OFF                         ; Untyped                                                  ;
; CLK0_USE_EVEN_COUNTER_VALUE   ; OFF                         ; Untyped                                                  ;
; LOCK_WINDOW_UI                ;  0.05                       ; Untyped                                                  ;
; LOCK_WINDOW_UI_BITS           ; UNUSED                      ; Untyped                                                  ;
; VCO_RANGE_DETECTOR_LOW_BITS   ; UNUSED                      ; Untyped                                                  ;
; VCO_RANGE_DETECTOR_HIGH_BITS  ; UNUSED                      ; Untyped                                                  ;
; DPA_MULTIPLY_BY               ; 0                           ; Untyped                                                  ;
; DPA_DIVIDE_BY                 ; 1                           ; Untyped                                                  ;
; DPA_DIVIDER                   ; 0                           ; Untyped                                                  ;
; EXTCLK3_MULTIPLY_BY           ; 1                           ; Untyped                                                  ;
; EXTCLK2_MULTIPLY_BY           ; 1                           ; Untyped                                                  ;
; EXTCLK1_MULTIPLY_BY           ; 1                           ; Untyped                                                  ;
; EXTCLK0_MULTIPLY_BY           ; 1                           ; Untyped                                                  ;
; EXTCLK3_DIVIDE_BY             ; 1                           ; Untyped                                                  ;
; EXTCLK2_DIVIDE_BY             ; 1                           ; Untyped                                                  ;
; EXTCLK1_DIVIDE_BY             ; 1                           ; Untyped                                                  ;
; EXTCLK0_DIVIDE_BY             ; 1                           ; Untyped                                                  ;
; EXTCLK3_PHASE_SHIFT           ; 0                           ; Untyped                                                  ;
; EXTCLK2_PHASE_SHIFT           ; 0                           ; Untyped                                                  ;
; EXTCLK1_PHASE_SHIFT           ; 0                           ; Untyped                                                  ;
; EXTCLK0_PHASE_SHIFT           ; 0                           ; Untyped                                                  ;
; EXTCLK3_TIME_DELAY            ; 0                           ; Untyped                                                  ;
; EXTCLK2_TIME_DELAY            ; 0                           ; Untyped                                                  ;
; EXTCLK1_TIME_DELAY            ; 0                           ; Untyped                                                  ;
; EXTCLK0_TIME_DELAY            ; 0                           ; Untyped                                                  ;
; EXTCLK3_DUTY_CYCLE            ; 50                          ; Untyped                                                  ;
; EXTCLK2_DUTY_CYCLE            ; 50                          ; Untyped                                                  ;
; EXTCLK1_DUTY_CYCLE            ; 50                          ; Untyped                                                  ;
; EXTCLK0_DUTY_CYCLE            ; 50                          ; Untyped                                                  ;
; VCO_MULTIPLY_BY               ; 0                           ; Untyped                                                  ;
; VCO_DIVIDE_BY                 ; 0                           ; Untyped                                                  ;
; SCLKOUT0_PHASE_SHIFT          ; 0                           ; Untyped                                                  ;
; SCLKOUT1_PHASE_SHIFT          ; 0                           ; Untyped                                                  ;
; VCO_MIN                       ; 0                           ; Untyped                                                  ;
; VCO_MAX                       ; 0                           ; Untyped                                                  ;
; VCO_CENTER                    ; 0                           ; Untyped                                                  ;
; PFD_MIN                       ; 0                           ; Untyped                                                  ;
; PFD_MAX                       ; 0                           ; Untyped                                                  ;
; M_INITIAL                     ; 0                           ; Untyped                                                  ;
; M                             ; 0                           ; Untyped                                                  ;
; N                             ; 1                           ; Untyped                                                  ;
; M2                            ; 1                           ; Untyped                                                  ;
; N2                            ; 1                           ; Untyped                                                  ;
; SS                            ; 1                           ; Untyped                                                  ;
; C0_HIGH                       ; 0                           ; Untyped                                                  ;
; C1_HIGH                       ; 0                           ; Untyped                                                  ;
; C2_HIGH                       ; 0                           ; Untyped                                                  ;
; C3_HIGH                       ; 0                           ; Untyped                                                  ;
; C4_HIGH                       ; 0                           ; Untyped                                                  ;
; C5_HIGH                       ; 0                           ; Untyped                                                  ;
; C6_HIGH                       ; 0                           ; Untyped                                                  ;
; C7_HIGH                       ; 0                           ; Untyped                                                  ;
; C8_HIGH                       ; 0                           ; Untyped                                                  ;
; C9_HIGH                       ; 0                           ; Untyped                                                  ;
; C0_LOW                        ; 0                           ; Untyped                                                  ;
; C1_LOW                        ; 0                           ; Untyped                                                  ;
; C2_LOW                        ; 0                           ; Untyped                                                  ;
; C3_LOW                        ; 0                           ; Untyped                                                  ;
; C4_LOW                        ; 0                           ; Untyped                                                  ;
; C5_LOW                        ; 0                           ; Untyped                                                  ;
; C6_LOW                        ; 0                           ; Untyped                                                  ;
; C7_LOW                        ; 0                           ; Untyped                                                  ;
; C8_LOW                        ; 0                           ; Untyped                                                  ;
; C9_LOW                        ; 0                           ; Untyped                                                  ;
; C0_INITIAL                    ; 0                           ; Untyped                                                  ;
; C1_INITIAL                    ; 0                           ; Untyped                                                  ;
; C2_INITIAL                    ; 0                           ; Untyped                                                  ;
; C3_INITIAL                    ; 0                           ; Untyped                                                  ;
; C4_INITIAL                    ; 0                           ; Untyped                                                  ;
; C5_INITIAL                    ; 0                           ; Untyped                                                  ;
; C6_INITIAL                    ; 0                           ; Untyped                                                  ;
; C7_INITIAL                    ; 0                           ; Untyped                                                  ;
; C8_INITIAL                    ; 0                           ; Untyped                                                  ;
; C9_INITIAL                    ; 0                           ; Untyped                                                  ;
; C0_MODE                       ; BYPASS                      ; Untyped                                                  ;
; C1_MODE                       ; BYPASS                      ; Untyped                                                  ;
; C2_MODE                       ; BYPASS                      ; Untyped                                                  ;
; C3_MODE                       ; BYPASS                      ; Untyped                                                  ;
; C4_MODE                       ; BYPASS                      ; Untyped                                                  ;
; C5_MODE                       ; BYPASS                      ; Untyped                                                  ;
; C6_MODE                       ; BYPASS                      ; Untyped                                                  ;
; C7_MODE                       ; BYPASS                      ; Untyped                                                  ;
; C8_MODE                       ; BYPASS                      ; Untyped                                                  ;
; C9_MODE                       ; BYPASS                      ; Untyped                                                  ;
; C0_PH                         ; 0                           ; Untyped                                                  ;
; C1_PH                         ; 0                           ; Untyped                                                  ;
; C2_PH                         ; 0                           ; Untyped                                                  ;
; C3_PH                         ; 0                           ; Untyped                                                  ;
; C4_PH                         ; 0                           ; Untyped                                                  ;
; C5_PH                         ; 0                           ; Untyped                                                  ;
; C6_PH                         ; 0                           ; Untyped                                                  ;
; C7_PH                         ; 0                           ; Untyped                                                  ;
; C8_PH                         ; 0                           ; Untyped                                                  ;
; C9_PH                         ; 0                           ; Untyped                                                  ;
; L0_HIGH                       ; 1                           ; Untyped                                                  ;
; L1_HIGH                       ; 1                           ; Untyped                                                  ;
; G0_HIGH                       ; 1                           ; Untyped                                                  ;
; G1_HIGH                       ; 1                           ; Untyped                                                  ;
; G2_HIGH                       ; 1                           ; Untyped                                                  ;
; G3_HIGH                       ; 1                           ; Untyped                                                  ;
; E0_HIGH                       ; 1                           ; Untyped                                                  ;
; E1_HIGH                       ; 1                           ; Untyped                                                  ;
; E2_HIGH                       ; 1                           ; Untyped                                                  ;
; E3_HIGH                       ; 1                           ; Untyped                                                  ;
; L0_LOW                        ; 1                           ; Untyped                                                  ;
; L1_LOW                        ; 1                           ; Untyped                                                  ;
; G0_LOW                        ; 1                           ; Untyped                                                  ;
; G1_LOW                        ; 1                           ; Untyped                                                  ;
; G2_LOW                        ; 1                           ; Untyped                                                  ;
; G3_LOW                        ; 1                           ; Untyped                                                  ;
; E0_LOW                        ; 1                           ; Untyped                                                  ;
; E1_LOW                        ; 1                           ; Untyped                                                  ;
; E2_LOW                        ; 1                           ; Untyped                                                  ;
; E3_LOW                        ; 1                           ; Untyped                                                  ;
; L0_INITIAL                    ; 1                           ; Untyped                                                  ;
; L1_INITIAL                    ; 1                           ; Untyped                                                  ;
; G0_INITIAL                    ; 1                           ; Untyped                                                  ;
; G1_INITIAL                    ; 1                           ; Untyped                                                  ;
; G2_INITIAL                    ; 1                           ; Untyped                                                  ;
; G3_INITIAL                    ; 1                           ; Untyped                                                  ;
; E0_INITIAL                    ; 1                           ; Untyped                                                  ;
; E1_INITIAL                    ; 1                           ; Untyped                                                  ;
; E2_INITIAL                    ; 1                           ; Untyped                                                  ;
; E3_INITIAL                    ; 1                           ; Untyped                                                  ;
; L0_MODE                       ; BYPASS                      ; Untyped                                                  ;
; L1_MODE                       ; BYPASS                      ; Untyped                                                  ;
; G0_MODE                       ; BYPASS                      ; Untyped                                                  ;
; G1_MODE                       ; BYPASS                      ; Untyped                                                  ;
; G2_MODE                       ; BYPASS                      ; Untyped                                                  ;
; G3_MODE                       ; BYPASS                      ; Untyped                                                  ;
; E0_MODE                       ; BYPASS                      ; Untyped                                                  ;
; E1_MODE                       ; BYPASS                      ; Untyped                                                  ;
; E2_MODE                       ; BYPASS                      ; Untyped                                                  ;
; E3_MODE                       ; BYPASS                      ; Untyped                                                  ;
; L0_PH                         ; 0                           ; Untyped                                                  ;
; L1_PH                         ; 0                           ; Untyped                                                  ;
; G0_PH                         ; 0                           ; Untyped                                                  ;
; G1_PH                         ; 0                           ; Untyped                                                  ;
; G2_PH                         ; 0                           ; Untyped                                                  ;
; G3_PH                         ; 0                           ; Untyped                                                  ;
; E0_PH                         ; 0                           ; Untyped                                                  ;
; E1_PH                         ; 0                           ; Untyped                                                  ;
; E2_PH                         ; 0                           ; Untyped                                                  ;
; E3_PH                         ; 0                           ; Untyped                                                  ;
; M_PH                          ; 0                           ; Untyped                                                  ;
; C1_USE_CASC_IN                ; OFF                         ; Untyped                                                  ;
; C2_USE_CASC_IN                ; OFF                         ; Untyped                                                  ;
; C3_USE_CASC_IN                ; OFF                         ; Untyped                                                  ;
; C4_USE_CASC_IN                ; OFF                         ; Untyped                                                  ;
; C5_USE_CASC_IN                ; OFF                         ; Untyped                                                  ;
; C6_USE_CASC_IN                ; OFF                         ; Untyped                                                  ;
; C7_USE_CASC_IN                ; OFF                         ; Untyped                                                  ;
; C8_USE_CASC_IN                ; OFF                         ; Untyped                                                  ;
; C9_USE_CASC_IN                ; OFF                         ; Untyped                                                  ;
; CLK0_COUNTER                  ; G0                          ; Untyped                                                  ;
; CLK1_COUNTER                  ; G0                          ; Untyped                                                  ;
; CLK2_COUNTER                  ; G0                          ; Untyped                                                  ;
; CLK3_COUNTER                  ; G0                          ; Untyped                                                  ;
; CLK4_COUNTER                  ; G0                          ; Untyped                                                  ;
; CLK5_COUNTER                  ; G0                          ; Untyped                                                  ;
; CLK6_COUNTER                  ; E0                          ; Untyped                                                  ;
; CLK7_COUNTER                  ; E1                          ; Untyped                                                  ;
; CLK8_COUNTER                  ; E2                          ; Untyped                                                  ;
; CLK9_COUNTER                  ; E3                          ; Untyped                                                  ;
; L0_TIME_DELAY                 ; 0                           ; Untyped                                                  ;
; L1_TIME_DELAY                 ; 0                           ; Untyped                                                  ;
; G0_TIME_DELAY                 ; 0                           ; Untyped                                                  ;
; G1_TIME_DELAY                 ; 0                           ; Untyped                                                  ;
; G2_TIME_DELAY                 ; 0                           ; Untyped                                                  ;
; G3_TIME_DELAY                 ; 0                           ; Untyped                                                  ;
; E0_TIME_DELAY                 ; 0                           ; Untyped                                                  ;
; E1_TIME_DELAY                 ; 0                           ; Untyped                                                  ;
; E2_TIME_DELAY                 ; 0                           ; Untyped                                                  ;
; E3_TIME_DELAY                 ; 0                           ; Untyped                                                  ;
; M_TIME_DELAY                  ; 0                           ; Untyped                                                  ;
; N_TIME_DELAY                  ; 0                           ; Untyped                                                  ;
; EXTCLK3_COUNTER               ; E3                          ; Untyped                                                  ;
; EXTCLK2_COUNTER               ; E2                          ; Untyped                                                  ;
; EXTCLK1_COUNTER               ; E1                          ; Untyped                                                  ;
; EXTCLK0_COUNTER               ; E0                          ; Untyped                                                  ;
; ENABLE0_COUNTER               ; L0                          ; Untyped                                                  ;
; ENABLE1_COUNTER               ; L0                          ; Untyped                                                  ;
; CHARGE_PUMP_CURRENT           ; 2                           ; Untyped                                                  ;
; LOOP_FILTER_R                 ;  1.000000                   ; Untyped                                                  ;
; LOOP_FILTER_C                 ; 5                           ; Untyped                                                  ;
; CHARGE_PUMP_CURRENT_BITS      ; 9999                        ; Untyped                                                  ;
; LOOP_FILTER_R_BITS            ; 9999                        ; Untyped                                                  ;
; LOOP_FILTER_C_BITS            ; 9999                        ; Untyped                                                  ;
; VCO_POST_SCALE                ; 0                           ; Untyped                                                  ;
; CLK2_OUTPUT_FREQUENCY         ; 0                           ; Untyped                                                  ;
; CLK1_OUTPUT_FREQUENCY         ; 0                           ; Untyped                                                  ;
; CLK0_OUTPUT_FREQUENCY         ; 0                           ; Untyped                                                  ;
; INTENDED_DEVICE_FAMILY        ; Cyclone II                  ; Untyped                                                  ;
; PORT_CLKENA0                  ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_CLKENA1                  ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_CLKENA2                  ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_CLKENA3                  ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_CLKENA4                  ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_CLKENA5                  ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY           ; Untyped                                                  ;
; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY           ; Untyped                                                  ;
; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY           ; Untyped                                                  ;
; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY           ; Untyped                                                  ;
; PORT_EXTCLK0                  ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_EXTCLK1                  ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_EXTCLK2                  ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_EXTCLK3                  ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_CLKBAD0                  ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_CLKBAD1                  ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_CLK0                     ; PORT_USED                   ; Untyped                                                  ;
; PORT_CLK1                     ; PORT_USED                   ; Untyped                                                  ;
; PORT_CLK2                     ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_CLK3                     ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_CLK4                     ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_CLK5                     ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_CLK6                     ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_CLK7                     ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_CLK8                     ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_CLK9                     ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_SCANDATA                 ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_SCANDATAOUT              ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_SCANDONE                 ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY           ; Untyped                                                  ;
; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY           ; Untyped                                                  ;
; PORT_ACTIVECLOCK              ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_CLKLOSS                  ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_INCLK1                   ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_INCLK0                   ; PORT_USED                   ; Untyped                                                  ;
; PORT_FBIN                     ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_PLLENA                   ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_CLKSWITCH                ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_ARESET                   ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_PFDENA                   ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_SCANCLK                  ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_SCANACLR                 ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_SCANREAD                 ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_SCANWRITE                ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_ENABLE0                  ; PORT_CONNECTIVITY           ; Untyped                                                  ;
; PORT_ENABLE1                  ; PORT_CONNECTIVITY           ; Untyped                                                  ;
; PORT_LOCKED                   ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_CONFIGUPDATE             ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_FBOUT                    ; PORT_CONNECTIVITY           ; Untyped                                                  ;
; PORT_PHASEDONE                ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_PHASESTEP                ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_PHASEUPDOWN              ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_SCANCLKENA               ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_PHASECOUNTERSELECT       ; PORT_UNUSED                 ; Untyped                                                  ;
; PORT_VCOOVERRANGE             ; PORT_CONNECTIVITY           ; Untyped                                                  ;
; PORT_VCOUNDERRANGE            ; PORT_CONNECTIVITY           ; Untyped                                                  ;
; M_TEST_SOURCE                 ; 5                           ; Untyped                                                  ;
; C0_TEST_SOURCE                ; 5                           ; Untyped                                                  ;
; C1_TEST_SOURCE                ; 5                           ; Untyped                                                  ;
; C2_TEST_SOURCE                ; 5                           ; Untyped                                                  ;
; C3_TEST_SOURCE                ; 5                           ; Untyped                                                  ;
; C4_TEST_SOURCE                ; 5                           ; Untyped                                                  ;
; C5_TEST_SOURCE                ; 5                           ; Untyped                                                  ;
; C6_TEST_SOURCE                ; 5                           ; Untyped                                                  ;
; C7_TEST_SOURCE                ; 5                           ; Untyped                                                  ;
; C8_TEST_SOURCE                ; 5                           ; Untyped                                                  ;
; C9_TEST_SOURCE                ; 5                           ; Untyped                                                  ;
; CBXI_PARAMETER                ; NOTHING                     ; Untyped                                                  ;
; VCO_FREQUENCY_CONTROL         ; AUTO                        ; Untyped                                                  ;
; VCO_PHASE_SHIFT_STEP          ; 0                           ; Untyped                                                  ;
; WIDTH_CLOCK                   ; 6                           ; Untyped                                                  ;
; WIDTH_PHASECOUNTERSELECT      ; 4                           ; Untyped                                                  ;
; USING_FBMIMICBIDIR_PORT       ; OFF                         ; Untyped                                                  ;
; DEVICE_FAMILY                 ; Cyclone II                  ; Untyped                                                  ;
; SCAN_CHAIN_MIF_FILE           ; UNUSED                      ; Untyped                                                  ;
; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF                         ; Untyped                                                  ;
; AUTO_CARRY_CHAINS             ; ON                          ; AUTO_CARRY                                               ;
; IGNORE_CARRY_BUFFERS          ; OFF                         ; IGNORE_CARRY                                             ;
; AUTO_CASCADE_CHAINS           ; ON                          ; AUTO_CASCADE                                             ;
; IGNORE_CASCADE_BUFFERS        ; OFF                         ; IGNORE_CASCADE                                           ;
+-------------------------------+-----------------------------+----------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: audio_unit:audio_unit_1|filter_unit:filter_unit_1|lpm_mult_volume:volume_muliplier|lpm_mult:lpm_mult_component ;
+------------------------------------------------+------------+-----------------------------------------------------------------------------------------------+
; Parameter Name                                 ; Value      ; Type                                                                                          ;
+------------------------------------------------+------------+-----------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS                              ; ON         ; AUTO_CARRY                                                                                    ;
; IGNORE_CARRY_BUFFERS                           ; OFF        ; IGNORE_CARRY                                                                                  ;
; AUTO_CASCADE_CHAINS                            ; ON         ; AUTO_CASCADE                                                                                  ;
; IGNORE_CASCADE_BUFFERS                         ; OFF        ; IGNORE_CASCADE                                                                                ;
; LPM_WIDTHA                                     ; 24         ; Signed Integer                                                                                ;
; LPM_WIDTHB                                     ; 40         ; Signed Integer                                                                                ;
; LPM_WIDTHP                                     ; 64         ; Signed Integer                                                                                ;
; LPM_WIDTHR                                     ; 0          ; Untyped                                                                                       ;
; LPM_WIDTHS                                     ; 1          ; Untyped                                                                                       ;
; LPM_REPRESENTATION                             ; SIGNED     ; Untyped                                                                                       ;
; LPM_PIPELINE                                   ; 0          ; Untyped                                                                                       ;
; LATENCY                                        ; 0          ; Untyped                                                                                       ;
; INPUT_A_IS_CONSTANT                            ; NO         ; Untyped                                                                                       ;
; INPUT_B_IS_CONSTANT                            ; NO         ; Untyped                                                                                       ;
; USE_EAB                                        ; OFF        ; Untyped                                                                                       ;
; MAXIMIZE_SPEED                                 ; 9          ; Untyped                                                                                       ;
; DEVICE_FAMILY                                  ; Cyclone II ; Untyped                                                                                       ;
; CARRY_CHAIN                                    ; MANUAL     ; Untyped                                                                                       ;
; APEX20K_TECHNOLOGY_MAPPER                      ; LUT        ; TECH_MAPPER_APEX20K                                                                           ;
; DEDICATED_MULTIPLIER_CIRCUITRY                 ; YES        ; Untyped                                                                                       ;
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0          ; Untyped                                                                                       ;
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0          ; Untyped                                                                                       ;
; CBXI_PARAMETER                                 ; mult_knq   ; Untyped                                                                                       ;
; INPUT_A_FIXED_VALUE                            ; Bx         ; Untyped                                                                                       ;
; INPUT_B_FIXED_VALUE                            ; Bx         ; Untyped                                                                                       ;
; USE_AHDL_IMPLEMENTATION                        ; OFF        ; Untyped                                                                                       ;
+------------------------------------------------+------------+-----------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|coeff_mul:coeff_mul_1|lpm_mult:lpm_mult_component ;
+------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                                 ; Value      ; Type                                                                                                                             ;
+------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS                              ; ON         ; AUTO_CARRY                                                                                                                       ;
; IGNORE_CARRY_BUFFERS                           ; OFF        ; IGNORE_CARRY                                                                                                                     ;
; AUTO_CASCADE_CHAINS                            ; ON         ; AUTO_CASCADE                                                                                                                     ;
; IGNORE_CASCADE_BUFFERS                         ; OFF        ; IGNORE_CASCADE                                                                                                                   ;
; LPM_WIDTHA                                     ; 64         ; Signed Integer                                                                                                                   ;
; LPM_WIDTHB                                     ; 40         ; Signed Integer                                                                                                                   ;
; LPM_WIDTHP                                     ; 104        ; Signed Integer                                                                                                                   ;
; LPM_WIDTHR                                     ; 0          ; Untyped                                                                                                                          ;
; LPM_WIDTHS                                     ; 1          ; Untyped                                                                                                                          ;
; LPM_REPRESENTATION                             ; SIGNED     ; Untyped                                                                                                                          ;
; LPM_PIPELINE                                   ; 0          ; Untyped                                                                                                                          ;
; LATENCY                                        ; 0          ; Untyped                                                                                                                          ;
; INPUT_A_IS_CONSTANT                            ; NO         ; Untyped                                                                                                                          ;
; INPUT_B_IS_CONSTANT                            ; NO         ; Untyped                                                                                                                          ;
; USE_EAB                                        ; OFF        ; Untyped                                                                                                                          ;
; MAXIMIZE_SPEED                                 ; 9          ; Untyped                                                                                                                          ;
; DEVICE_FAMILY                                  ; Cyclone II ; Untyped                                                                                                                          ;
; CARRY_CHAIN                                    ; MANUAL     ; Untyped                                                                                                                          ;
; APEX20K_TECHNOLOGY_MAPPER                      ; LUT        ; TECH_MAPPER_APEX20K                                                                                                              ;
; DEDICATED_MULTIPLIER_CIRCUITRY                 ; YES        ; Untyped                                                                                                                          ;
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0          ; Untyped                                                                                                                          ;
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0          ; Untyped                                                                                                                          ;
; CBXI_PARAMETER                                 ; mult_3pq   ; Untyped                                                                                                                          ;
; INPUT_A_FIXED_VALUE                            ; Bx         ; Untyped                                                                                                                          ;
; INPUT_B_FIXED_VALUE                            ; Bx         ; Untyped                                                                                                                          ;
; USE_AHDL_IMPLEMENTATION                        ; OFF        ; Untyped                                                                                                                          ;
+------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|lpm_mult0:lpm_mult0_1|lpm_mult:lpm_mult_component ;
+------------------------------------------------+------------+-----------------------------------------------------------------------------------------------+
; Parameter Name                                 ; Value      ; Type                                                                                          ;
+------------------------------------------------+------------+-----------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS                              ; ON         ; AUTO_CARRY                                                                                    ;
; IGNORE_CARRY_BUFFERS                           ; OFF        ; IGNORE_CARRY                                                                                  ;
; AUTO_CASCADE_CHAINS                            ; ON         ; AUTO_CASCADE                                                                                  ;
; IGNORE_CASCADE_BUFFERS                         ; OFF        ; IGNORE_CASCADE                                                                                ;
; LPM_WIDTHA                                     ; 24         ; Signed Integer                                                                                ;
; LPM_WIDTHB                                     ; 64         ; Signed Integer                                                                                ;
; LPM_WIDTHP                                     ; 88         ; Signed Integer                                                                                ;
; LPM_WIDTHR                                     ; 0          ; Untyped                                                                                       ;
; LPM_WIDTHS                                     ; 1          ; Untyped                                                                                       ;
; LPM_REPRESENTATION                             ; SIGNED     ; Untyped                                                                                       ;
; LPM_PIPELINE                                   ; 0          ; Untyped                                                                                       ;
; LATENCY                                        ; 0          ; Untyped                                                                                       ;
; INPUT_A_IS_CONSTANT                            ; NO         ; Untyped                                                                                       ;
; INPUT_B_IS_CONSTANT                            ; NO         ; Untyped                                                                                       ;
; USE_EAB                                        ; OFF        ; Untyped                                                                                       ;
; MAXIMIZE_SPEED                                 ; 9          ; Untyped                                                                                       ;
; DEVICE_FAMILY                                  ; Cyclone II ; Untyped                                                                                       ;
; CARRY_CHAIN                                    ; MANUAL     ; Untyped                                                                                       ;
; APEX20K_TECHNOLOGY_MAPPER                      ; LUT        ; TECH_MAPPER_APEX20K                                                                           ;
; DEDICATED_MULTIPLIER_CIRCUITRY                 ; YES        ; Untyped                                                                                       ;
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0          ; Untyped                                                                                       ;
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0          ; Untyped                                                                                       ;
; CBXI_PARAMETER                                 ; mult_0oq   ; Untyped                                                                                       ;
; INPUT_A_FIXED_VALUE                            ; Bx         ; Untyped                                                                                       ;
; INPUT_B_FIXED_VALUE                            ; Bx         ; Untyped                                                                                       ;
; USE_AHDL_IMPLEMENTATION                        ; OFF        ; Untyped                                                                                       ;
+------------------------------------------------+------------+-----------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|lpm_mult0:lpm_mult0_2|lpm_mult:lpm_mult_component ;
+------------------------------------------------+------------+-----------------------------------------------------------------------------------------------+
; Parameter Name                                 ; Value      ; Type                                                                                          ;
+------------------------------------------------+------------+-----------------------------------------------------------------------------------------------+
; AUTO_CARRY_CHAINS                              ; ON         ; AUTO_CARRY                                                                                    ;
; IGNORE_CARRY_BUFFERS                           ; OFF        ; IGNORE_CARRY                                                                                  ;
; AUTO_CASCADE_CHAINS                            ; ON         ; AUTO_CASCADE                                                                                  ;
; IGNORE_CASCADE_BUFFERS                         ; OFF        ; IGNORE_CASCADE                                                                                ;
; LPM_WIDTHA                                     ; 24         ; Signed Integer                                                                                ;
; LPM_WIDTHB                                     ; 64         ; Signed Integer                                                                                ;
; LPM_WIDTHP                                     ; 88         ; Signed Integer                                                                                ;
; LPM_WIDTHR                                     ; 0          ; Untyped                                                                                       ;
; LPM_WIDTHS                                     ; 1          ; Untyped                                                                                       ;
; LPM_REPRESENTATION                             ; SIGNED     ; Untyped                                                                                       ;
; LPM_PIPELINE                                   ; 0          ; Untyped                                                                                       ;
; LATENCY                                        ; 0          ; Untyped                                                                                       ;
; INPUT_A_IS_CONSTANT                            ; NO         ; Untyped                                                                                       ;
; INPUT_B_IS_CONSTANT                            ; NO         ; Untyped                                                                                       ;
; USE_EAB                                        ; OFF        ; Untyped                                                                                       ;
; MAXIMIZE_SPEED                                 ; 9          ; Untyped                                                                                       ;
; DEVICE_FAMILY                                  ; Cyclone II ; Untyped                                                                                       ;
; CARRY_CHAIN                                    ; MANUAL     ; Untyped                                                                                       ;
; APEX20K_TECHNOLOGY_MAPPER                      ; LUT        ; TECH_MAPPER_APEX20K                                                                           ;
; DEDICATED_MULTIPLIER_CIRCUITRY                 ; YES        ; Untyped                                                                                       ;
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0          ; Untyped                                                                                       ;
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0          ; Untyped                                                                                       ;
; CBXI_PARAMETER                                 ; mult_0oq   ; Untyped                                                                                       ;
; INPUT_A_FIXED_VALUE                            ; Bx         ; Untyped                                                                                       ;
; INPUT_B_FIXED_VALUE                            ; Bx         ; Untyped                                                                                       ;
; USE_AHDL_IMPLEMENTATION                        ; OFF        ; Untyped                                                                                       ;
+------------------------------------------------+------------+-----------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------+
; altpll Parameter Settings by Entity Instance                                                              ;
+-------------------------------+---------------------------------------------------------------------------+
; Name                          ; Value                                                                     ;
+-------------------------------+---------------------------------------------------------------------------+
; Number of entity instances    ; 2                                                                         ;
; Entity Instance               ; clock_generator:clock_generator_1|EQ_PLL_50:pll_1|altpll:altpll_component ;
;     -- OPERATION_MODE         ; NORMAL                                                                    ;
;     -- PLL_TYPE               ; AUTO                                                                      ;
;     -- PRIMARY_CLOCK          ; INCLK0                                                                    ;
;     -- INCLK0_INPUT_FREQUENCY ; 20000                                                                     ;
;     -- INCLK1_INPUT_FREQUENCY ; 0                                                                         ;
;     -- VCO_MULTIPLY_BY        ; 0                                                                         ;
;     -- VCO_DIVIDE_BY          ; 0                                                                         ;
; Entity Instance               ; clock_generator:clock_generator_1|EQ_PLL_27:pll_2|altpll:altpll_component ;
;     -- OPERATION_MODE         ; NORMAL                                                                    ;
;     -- PLL_TYPE               ; AUTO                                                                      ;
;     -- PRIMARY_CLOCK          ; INCLK0                                                                    ;
;     -- INCLK0_INPUT_FREQUENCY ; 37037                                                                     ;
;     -- INCLK1_INPUT_FREQUENCY ; 0                                                                         ;
;     -- VCO_MULTIPLY_BY        ; 0                                                                         ;
;     -- VCO_DIVIDE_BY          ; 0                                                                         ;
+-------------------------------+---------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; lpm_mult Parameter Settings by Entity Instance                                                                                                                                            ;
+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Name                                  ; Value                                                                                                                                             ;
+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Number of entity instances            ; 4                                                                                                                                                 ;
; Entity Instance                       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|lpm_mult_volume:volume_muliplier|lpm_mult:lpm_mult_component                                    ;
;     -- LPM_WIDTHA                     ; 24                                                                                                                                                ;
;     -- LPM_WIDTHB                     ; 40                                                                                                                                                ;
;     -- LPM_WIDTHP                     ; 64                                                                                                                                                ;
;     -- LPM_REPRESENTATION             ; SIGNED                                                                                                                                            ;
;     -- INPUT_A_IS_CONSTANT            ; NO                                                                                                                                                ;
;     -- INPUT_B_IS_CONSTANT            ; NO                                                                                                                                                ;
;     -- USE_EAB                        ; OFF                                                                                                                                               ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; YES                                                                                                                                               ;
;     -- INPUT_A_FIXED_VALUE            ; Bx                                                                                                                                                ;
;     -- INPUT_B_FIXED_VALUE            ; Bx                                                                                                                                                ;
; Entity Instance                       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|coeff_mul:coeff_mul_1|lpm_mult:lpm_mult_component ;
;     -- LPM_WIDTHA                     ; 64                                                                                                                                                ;
;     -- LPM_WIDTHB                     ; 40                                                                                                                                                ;
;     -- LPM_WIDTHP                     ; 104                                                                                                                                               ;
;     -- LPM_REPRESENTATION             ; SIGNED                                                                                                                                            ;
;     -- INPUT_A_IS_CONSTANT            ; NO                                                                                                                                                ;
;     -- INPUT_B_IS_CONSTANT            ; NO                                                                                                                                                ;
;     -- USE_EAB                        ; OFF                                                                                                                                               ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; YES                                                                                                                                               ;
;     -- INPUT_A_FIXED_VALUE            ; Bx                                                                                                                                                ;
;     -- INPUT_B_FIXED_VALUE            ; Bx                                                                                                                                                ;
; Entity Instance                       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|lpm_mult0:lpm_mult0_1|lpm_mult:lpm_mult_component                                    ;
;     -- LPM_WIDTHA                     ; 24                                                                                                                                                ;
;     -- LPM_WIDTHB                     ; 64                                                                                                                                                ;
;     -- LPM_WIDTHP                     ; 88                                                                                                                                                ;
;     -- LPM_REPRESENTATION             ; SIGNED                                                                                                                                            ;
;     -- INPUT_A_IS_CONSTANT            ; NO                                                                                                                                                ;
;     -- INPUT_B_IS_CONSTANT            ; NO                                                                                                                                                ;
;     -- USE_EAB                        ; OFF                                                                                                                                               ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; YES                                                                                                                                               ;
;     -- INPUT_A_FIXED_VALUE            ; Bx                                                                                                                                                ;
;     -- INPUT_B_FIXED_VALUE            ; Bx                                                                                                                                                ;
; Entity Instance                       ; audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|lpm_mult0:lpm_mult0_2|lpm_mult:lpm_mult_component                                    ;
;     -- LPM_WIDTHA                     ; 24                                                                                                                                                ;
;     -- LPM_WIDTHB                     ; 64                                                                                                                                                ;
;     -- LPM_WIDTHP                     ; 88                                                                                                                                                ;
;     -- LPM_REPRESENTATION             ; SIGNED                                                                                                                                            ;
;     -- INPUT_A_IS_CONSTANT            ; NO                                                                                                                                                ;
;     -- INPUT_B_IS_CONSTANT            ; NO                                                                                                                                                ;
;     -- USE_EAB                        ; OFF                                                                                                                                               ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; YES                                                                                                                                               ;
;     -- INPUT_A_FIXED_VALUE            ; Bx                                                                                                                                                ;
;     -- INPUT_B_FIXED_VALUE            ; Bx                                                                                                                                                ;
+---------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|coeff_mul:coeff_mul_1" ;
+-----------------+--------+----------+-------------------------------------------------------------------------------------------------------------+
; Port            ; Type   ; Severity ; Details                                                                                                     ;
+-----------------+--------+----------+-------------------------------------------------------------------------------------------------------------+
; result[103..99] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                         ;
; result[34..0]   ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed.                         ;
+-----------------+--------+----------+-------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "audio_unit:audio_unit_1|filter_unit:filter_unit_1|lpm_mult_volume:volume_muliplier"           ;
+----------------+--------+----------+-------------------------------------------------------------------------------------+
; Port           ; Type   ; Severity ; Details                                                                             ;
+----------------+--------+----------+-------------------------------------------------------------------------------------+
; result[63..59] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; result[34..0]  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+----------------+--------+----------+-------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "audio_unit:audio_unit_1|i2c_master:i2c_master_1"                                           ;
+-------------+--------+----------+-------------------------------------------------------------------------------------+
; Port        ; Type   ; Severity ; Details                                                                             ;
+-------------+--------+----------+-------------------------------------------------------------------------------------+
; done        ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; state_count ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+-------------+--------+----------+-------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "clock_generator:clock_generator_1"                                                       ;
+-----------+--------+----------+-------------------------------------------------------------------------------------+
; Port      ; Type   ; Severity ; Details                                                                             ;
+-----------+--------+----------+-------------------------------------------------------------------------------------+
; clk_27mhz ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; clk_100hz ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+-----------+--------+----------+-------------------------------------------------------------------------------------+


+-------------------------------+
; Elapsed Time Per Partition    ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top            ; 00:01:07     ;
+----------------+--------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit Analysis & Synthesis
    Info: Version 13.0.0 Build 156 04/24/2013 SJ Web Edition
    Info: Processing started: Fri May 22 21:45:23 2015
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Equalizer -c Equalizer
Info (20030): Parallel compilation is enabled and will use 2 of the 2 processors detected
Info (12021): Found 2 design units, including 1 entities, in source file lpm_mult0.vhd
    Info (12022): Found design unit 1: lpm_mult0-SYN
    Info (12023): Found entity 1: lpm_mult0
Info (12021): Found 2 design units, including 1 entities, in source file eq_pll_27.vhd
    Info (12022): Found design unit 1: eq_pll_27-SYN
    Info (12023): Found entity 1: EQ_PLL_27
Info (12021): Found 2 design units, including 1 entities, in source file eq_pll_50.vhd
    Info (12022): Found design unit 1: eq_pll_50-SYN
    Info (12023): Found entity 1: EQ_PLL_50
Info (12021): Found 2 design units, including 1 entities, in source file lpm_div0.vhd
    Info (12022): Found design unit 1: lpm_div0-SYN
    Info (12023): Found entity 1: lpm_div0
Info (12021): Found 2 design units, including 1 entities, in source file iir.vhd
    Info (12022): Found design unit 1: iir-behavior
    Info (12023): Found entity 1: iir
Info (12021): Found 2 design units, including 1 entities, in source file lcd_controller.vhd
    Info (12022): Found design unit 1: lcd_controller-a_lcd_controller
    Info (12023): Found entity 1: lcd_controller
Info (12021): Found 2 design units, including 1 entities, in source file mmi_controller.vhd
    Info (12022): Found design unit 1: mmi_controller-behavior
    Info (12023): Found entity 1: mmi_controller
Info (12021): Found 2 design units, including 1 entities, in source file clock_generator.vhd
    Info (12022): Found design unit 1: clock_generator-behavior
    Info (12023): Found entity 1: clock_generator
Info (12021): Found 2 design units, including 1 entities, in source file equalizer.vhd
    Info (12022): Found design unit 1: Equalizer-behavior
    Info (12023): Found entity 1: Equalizer
Info (12021): Found 2 design units, including 1 entities, in source file clock_divider.vhd
    Info (12022): Found design unit 1: clock_divider-behavior
    Info (12023): Found entity 1: clock_divider
Info (12021): Found 2 design units, including 1 entities, in source file coefficients_register.vhd
    Info (12022): Found design unit 1: coefficients_register-behavior
    Info (12023): Found entity 1: coefficients_register
Info (12021): Found 2 design units, including 1 entities, in source file coeff_mul.vhd
    Info (12022): Found design unit 1: coeff_mul-SYN
    Info (12023): Found entity 1: coeff_mul
Info (12021): Found 2 design units, including 1 entities, in source file coeff_add.vhd
    Info (12022): Found design unit 1: coeff_add-SYN
    Info (12023): Found entity 1: coeff_add
Info (12021): Found 2 design units, including 1 entities, in source file coeff_sub.vhd
    Info (12022): Found design unit 1: coeff_sub-SYN
    Info (12023): Found entity 1: coeff_sub
Info (12127): Elaborating entity "Equalizer" for the top level hierarchy
Warning (10540): VHDL Signal Declaration warning at Equalizer.vhd(49): used explicit default value for signal "HEX5" because signal was never assigned a value
Warning (10036): Verilog HDL or VHDL warning at Equalizer.vhd(87): object "clk_27MHz" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at Equalizer.vhd(90): object "clk_100Hz" assigned a value but never read
Info (12128): Elaborating entity "clock_generator" for hierarchy "clock_generator:clock_generator_1"
Info (12128): Elaborating entity "EQ_PLL_50" for hierarchy "clock_generator:clock_generator_1|EQ_PLL_50:pll_1"
Info (12128): Elaborating entity "altpll" for hierarchy "clock_generator:clock_generator_1|EQ_PLL_50:pll_1|altpll:altpll_component"
Info (12130): Elaborated megafunction instantiation "clock_generator:clock_generator_1|EQ_PLL_50:pll_1|altpll:altpll_component"
Info (12133): Instantiated megafunction "clock_generator:clock_generator_1|EQ_PLL_50:pll_1|altpll:altpll_component" with the following parameter:
    Info (12134): Parameter "clk0_divide_by" = "1"
    Info (12134): Parameter "clk0_duty_cycle" = "50"
    Info (12134): Parameter "clk0_multiply_by" = "1"
    Info (12134): Parameter "clk0_phase_shift" = "0"
    Info (12134): Parameter "clk1_divide_by" = "5"
    Info (12134): Parameter "clk1_duty_cycle" = "50"
    Info (12134): Parameter "clk1_multiply_by" = "1"
    Info (12134): Parameter "clk1_phase_shift" = "0"
    Info (12134): Parameter "compensate_clock" = "CLK0"
    Info (12134): Parameter "inclk0_input_frequency" = "20000"
    Info (12134): Parameter "intended_device_family" = "Cyclone II"
    Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=EQ_PLL_50"
    Info (12134): Parameter "lpm_type" = "altpll"
    Info (12134): Parameter "operation_mode" = "NORMAL"
    Info (12134): Parameter "port_activeclock" = "PORT_UNUSED"
    Info (12134): Parameter "port_areset" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkloss" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED"
    Info (12134): Parameter "port_configupdate" = "PORT_UNUSED"
    Info (12134): Parameter "port_fbin" = "PORT_UNUSED"
    Info (12134): Parameter "port_inclk0" = "PORT_USED"
    Info (12134): Parameter "port_inclk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_locked" = "PORT_UNUSED"
    Info (12134): Parameter "port_pfdena" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasedone" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasestep" = "PORT_UNUSED"
    Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED"
    Info (12134): Parameter "port_pllena" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanclk" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandata" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandataout" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandone" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanread" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk0" = "PORT_USED"
    Info (12134): Parameter "port_clk1" = "PORT_USED"
    Info (12134): Parameter "port_clk2" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk3" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk4" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk5" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena0" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena2" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena3" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena4" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena5" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk0" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk2" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk3" = "PORT_UNUSED"
Info (12128): Elaborating entity "EQ_PLL_27" for hierarchy "clock_generator:clock_generator_1|EQ_PLL_27:pll_2"
Info (12128): Elaborating entity "altpll" for hierarchy "clock_generator:clock_generator_1|EQ_PLL_27:pll_2|altpll:altpll_component"
Info (12130): Elaborated megafunction instantiation "clock_generator:clock_generator_1|EQ_PLL_27:pll_2|altpll:altpll_component"
Info (12133): Instantiated megafunction "clock_generator:clock_generator_1|EQ_PLL_27:pll_2|altpll:altpll_component" with the following parameter:
    Info (12134): Parameter "clk0_divide_by" = "1"
    Info (12134): Parameter "clk0_duty_cycle" = "50"
    Info (12134): Parameter "clk0_multiply_by" = "1"
    Info (12134): Parameter "clk0_phase_shift" = "0"
    Info (12134): Parameter "clk1_divide_by" = "9"
    Info (12134): Parameter "clk1_duty_cycle" = "50"
    Info (12134): Parameter "clk1_multiply_by" = "4"
    Info (12134): Parameter "clk1_phase_shift" = "0"
    Info (12134): Parameter "compensate_clock" = "CLK0"
    Info (12134): Parameter "inclk0_input_frequency" = "37037"
    Info (12134): Parameter "intended_device_family" = "Cyclone II"
    Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=EQ_PLL_27"
    Info (12134): Parameter "lpm_type" = "altpll"
    Info (12134): Parameter "operation_mode" = "NORMAL"
    Info (12134): Parameter "port_activeclock" = "PORT_UNUSED"
    Info (12134): Parameter "port_areset" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkloss" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED"
    Info (12134): Parameter "port_configupdate" = "PORT_UNUSED"
    Info (12134): Parameter "port_fbin" = "PORT_UNUSED"
    Info (12134): Parameter "port_inclk0" = "PORT_USED"
    Info (12134): Parameter "port_inclk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_locked" = "PORT_UNUSED"
    Info (12134): Parameter "port_pfdena" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasedone" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasestep" = "PORT_UNUSED"
    Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED"
    Info (12134): Parameter "port_pllena" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanclk" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandata" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandataout" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandone" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanread" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk0" = "PORT_USED"
    Info (12134): Parameter "port_clk1" = "PORT_USED"
    Info (12134): Parameter "port_clk2" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk3" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk4" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk5" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena0" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena2" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena3" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena4" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena5" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk0" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk2" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk3" = "PORT_UNUSED"
Info (12128): Elaborating entity "clock_divider" for hierarchy "clock_generator:clock_generator_1|clock_divider:clock_divider_1"
Warning (12125): Using design file mmi.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info (12022): Found design unit 1: MMI-behavior
    Info (12023): Found entity 1: MMI
Info (12128): Elaborating entity "MMI" for hierarchy "MMI:MMI_1"
Info (12128): Elaborating entity "lcd_controller" for hierarchy "MMI:MMI_1|lcd_controller:lcd_controller_1"
Info (12128): Elaborating entity "mmi_controller" for hierarchy "MMI:MMI_1|mmi_controller:mmi_controller_1"
Warning (12125): Using design file audio_unit.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info (12022): Found design unit 1: audio_unit-behavior
    Info (12023): Found entity 1: audio_unit
Info (12128): Elaborating entity "audio_unit" for hierarchy "audio_unit:audio_unit_1"
Warning (10036): Verilog HDL or VHDL warning at audio_unit.vhd(85): object "D" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at audio_unit.vhd(86): object "sc" assigned a value but never read
Warning (12125): Using design file i2c_master.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info (12022): Found design unit 1: i2c_master-BEHAVIOR
    Info (12023): Found entity 1: i2c_master
Info (12128): Elaborating entity "i2c_master" for hierarchy "audio_unit:audio_unit_1|i2c_master:i2c_master_1"
Warning (12125): Using design file audio_input_register.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info (12022): Found design unit 1: audio_input_register-behavior
    Info (12023): Found entity 1: audio_input_register
Info (12128): Elaborating entity "audio_input_register" for hierarchy "audio_unit:audio_unit_1|audio_input_register:audio_input_register_1"
Warning (12125): Using design file filter_unit.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info (12022): Found design unit 1: filter_unit-behavior
    Info (12023): Found entity 1: filter_unit
Info (12128): Elaborating entity "filter_unit" for hierarchy "audio_unit:audio_unit_1|filter_unit:filter_unit_1"
Warning (12125): Using design file db2linear.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info (12022): Found design unit 1: db2linear-behavior
    Info (12023): Found entity 1: db2linear
Info (12128): Elaborating entity "db2linear" for hierarchy "audio_unit:audio_unit_1|filter_unit:filter_unit_1|db2linear:volume_db2linear"
Warning (12125): Using design file lpm_mult_volume.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info (12022): Found design unit 1: lpm_mult_volume-SYN
    Info (12023): Found entity 1: lpm_mult_volume
Info (12128): Elaborating entity "lpm_mult_volume" for hierarchy "audio_unit:audio_unit_1|filter_unit:filter_unit_1|lpm_mult_volume:volume_muliplier"
Info (12128): Elaborating entity "lpm_mult" for hierarchy "audio_unit:audio_unit_1|filter_unit:filter_unit_1|lpm_mult_volume:volume_muliplier|lpm_mult:lpm_mult_component"
Info (12130): Elaborated megafunction instantiation "audio_unit:audio_unit_1|filter_unit:filter_unit_1|lpm_mult_volume:volume_muliplier|lpm_mult:lpm_mult_component"
Info (12133): Instantiated megafunction "audio_unit:audio_unit_1|filter_unit:filter_unit_1|lpm_mult_volume:volume_muliplier|lpm_mult:lpm_mult_component" with the following parameter:
    Info (12134): Parameter "lpm_hint" = "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9"
    Info (12134): Parameter "lpm_representation" = "SIGNED"
    Info (12134): Parameter "lpm_type" = "LPM_MULT"
    Info (12134): Parameter "lpm_widtha" = "24"
    Info (12134): Parameter "lpm_widthb" = "40"
    Info (12134): Parameter "lpm_widthp" = "64"
Info (12021): Found 1 design units, including 1 entities, in source file db/mult_knq.tdf
    Info (12023): Found entity 1: mult_knq
Info (12128): Elaborating entity "mult_knq" for hierarchy "audio_unit:audio_unit_1|filter_unit:filter_unit_1|lpm_mult_volume:volume_muliplier|lpm_mult:lpm_mult_component|mult_knq:auto_generated"
Info (12128): Elaborating entity "coefficients_register" for hierarchy "audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1"
Info (12128): Elaborating entity "coeff_mul" for hierarchy "audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|coeff_mul:coeff_mul_1"
Info (12128): Elaborating entity "lpm_mult" for hierarchy "audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|coeff_mul:coeff_mul_1|lpm_mult:lpm_mult_component"
Info (12130): Elaborated megafunction instantiation "audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|coeff_mul:coeff_mul_1|lpm_mult:lpm_mult_component"
Info (12133): Instantiated megafunction "audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|coeff_mul:coeff_mul_1|lpm_mult:lpm_mult_component" with the following parameter:
    Info (12134): Parameter "lpm_hint" = "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9"
    Info (12134): Parameter "lpm_representation" = "SIGNED"
    Info (12134): Parameter "lpm_type" = "LPM_MULT"
    Info (12134): Parameter "lpm_widtha" = "64"
    Info (12134): Parameter "lpm_widthb" = "40"
    Info (12134): Parameter "lpm_widthp" = "104"
Info (12021): Found 1 design units, including 1 entities, in source file db/mult_3pq.tdf
    Info (12023): Found entity 1: mult_3pq
Info (12128): Elaborating entity "mult_3pq" for hierarchy "audio_unit:audio_unit_1|filter_unit:filter_unit_1|coefficients_register:coefficients_register_1|coeff_mul:coeff_mul_1|lpm_mult:lpm_mult_component|mult_3pq:auto_generated"
Info (12128): Elaborating entity "iir" for hierarchy "audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter"
Info (12128): Elaborating entity "lpm_mult0" for hierarchy "audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|lpm_mult0:lpm_mult0_1"
Info (12128): Elaborating entity "lpm_mult" for hierarchy "audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|lpm_mult0:lpm_mult0_1|lpm_mult:lpm_mult_component"
Info (12130): Elaborated megafunction instantiation "audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|lpm_mult0:lpm_mult0_1|lpm_mult:lpm_mult_component"
Info (12133): Instantiated megafunction "audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|lpm_mult0:lpm_mult0_1|lpm_mult:lpm_mult_component" with the following parameter:
    Info (12134): Parameter "lpm_hint" = "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9"
    Info (12134): Parameter "lpm_representation" = "SIGNED"
    Info (12134): Parameter "lpm_type" = "LPM_MULT"
    Info (12134): Parameter "lpm_widtha" = "24"
    Info (12134): Parameter "lpm_widthb" = "64"
    Info (12134): Parameter "lpm_widthp" = "88"
Info (12021): Found 1 design units, including 1 entities, in source file db/mult_0oq.tdf
    Info (12023): Found entity 1: mult_0oq
Info (12128): Elaborating entity "mult_0oq" for hierarchy "audio_unit:audio_unit_1|filter_unit:filter_unit_1|iir:filter|lpm_mult0:lpm_mult0_1|lpm_mult:lpm_mult_component|mult_0oq:auto_generated"
Warning (12125): Using design file audio_output_register.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info (12022): Found design unit 1: audio_output_register-behavior
    Info (12023): Found entity 1: audio_output_register
Info (12128): Elaborating entity "audio_output_register" for hierarchy "audio_unit:audio_unit_1|audio_output_register:audio_output_register_1"
Info (13014): Ignored 2404 buffer(s)
    Info (13019): Ignored 2404 SOFT buffer(s)
Warning (332009): The launch and latch times for the relationship between source clock: clock_generator_1|pll_1|altpll_component|pll|clk[1] and destination clock: clock_generator_1|pll_2|altpll_component|pll|clk[1] are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
Info (286030): Timing-Driven Synthesis is running
Warning (13034): The following nodes have both tri-state and non-tri-state drivers
    Warning (13035): Inserted always-enabled tri-state buffer between "LCD_DATA[0]" and its non-tri-state driver.
    Warning (13035): Inserted always-enabled tri-state buffer between "LCD_DATA[1]" and its non-tri-state driver.
    Warning (13035): Inserted always-enabled tri-state buffer between "LCD_DATA[2]" and its non-tri-state driver.
    Warning (13035): Inserted always-enabled tri-state buffer between "LCD_DATA[3]" and its non-tri-state driver.
    Warning (13035): Inserted always-enabled tri-state buffer between "LCD_DATA[4]" and its non-tri-state driver.
    Warning (13035): Inserted always-enabled tri-state buffer between "LCD_DATA[5]" and its non-tri-state driver.
    Warning (13035): Inserted always-enabled tri-state buffer between "LCD_DATA[6]" and its non-tri-state driver.
    Warning (13035): Inserted always-enabled tri-state buffer between "LCD_DATA[7]" and its non-tri-state driver.
Info (13000): Registers with preset signals will power-up high
Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Warning (13009): TRI or OPNDRN buffers permanently enabled
    Warning (13010): Node "LCD_DATA[0]~synth"
    Warning (13010): Node "LCD_DATA[1]~synth"
    Warning (13010): Node "LCD_DATA[2]~synth"
    Warning (13010): Node "LCD_DATA[3]~synth"
    Warning (13010): Node "LCD_DATA[4]~synth"
    Warning (13010): Node "LCD_DATA[5]~synth"
    Warning (13010): Node "LCD_DATA[6]~synth"
    Warning (13010): Node "LCD_DATA[7]~synth"
Warning (13024): Output pins are stuck at VCC or GND
    Warning (13410): Pin "LCD_RW" is stuck at GND
    Warning (13410): Pin "LCD_ON" is stuck at VCC
    Warning (13410): Pin "LCD_BLON" is stuck at VCC
    Warning (13410): Pin "HEX0[0]" is stuck at VCC
    Warning (13410): Pin "HEX0[1]" is stuck at VCC
    Warning (13410): Pin "HEX1[0]" is stuck at VCC
    Warning (13410): Pin "HEX1[5]" is stuck at VCC
    Warning (13410): Pin "HEX4[0]" is stuck at VCC
    Warning (13410): Pin "HEX4[1]" is stuck at VCC
    Warning (13410): Pin "HEX4[2]" is stuck at VCC
    Warning (13410): Pin "HEX4[3]" is stuck at VCC
    Warning (13410): Pin "HEX4[4]" is stuck at VCC
    Warning (13410): Pin "HEX4[5]" is stuck at VCC
    Warning (13410): Pin "HEX5[0]" is stuck at VCC
    Warning (13410): Pin "HEX5[1]" is stuck at VCC
    Warning (13410): Pin "HEX5[2]" is stuck at VCC
    Warning (13410): Pin "HEX5[3]" is stuck at VCC
    Warning (13410): Pin "HEX5[4]" is stuck at VCC
    Warning (13410): Pin "HEX5[5]" is stuck at VCC
    Warning (13410): Pin "HEX5[6]" is stuck at VCC
    Warning (13410): Pin "HEX7[6]" is stuck at VCC
Critical Warning (18061): Ignored Power-Up Level option on the following registers
    Critical Warning (18010): Register audio_unit:audio_unit_1|i2c_master:i2c_master_1|SDIN~en will power up to High
Warning (332009): The launch and latch times for the relationship between source clock: clock_generator_1|pll_1|altpll_component|pll|clk[1] and destination clock: clock_generator_1|pll_2|altpll_component|pll|clk[1] are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
Warning (332009): The launch and latch times for the relationship between source clock: clock_generator_1|pll_1|altpll_component|pll|clk[1] and destination clock: clock_generator_1|pll_2|altpll_component|pll|clk[1] are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
Info (17049): 5 registers lost all their fanouts during netlist optimizations.
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
    Info (16011): Adding 2 node(s), including 0 DDIO, 2 PLL, 0 transceiver and 0 LCELL
Warning (21074): Design contains 13 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "SW[4]"
    Warning (15610): No output dependent on input pin "SW[5]"
    Warning (15610): No output dependent on input pin "SW[6]"
    Warning (15610): No output dependent on input pin "SW[7]"
    Warning (15610): No output dependent on input pin "SW[8]"
    Warning (15610): No output dependent on input pin "SW[9]"
    Warning (15610): No output dependent on input pin "SW[10]"
    Warning (15610): No output dependent on input pin "SW[11]"
    Warning (15610): No output dependent on input pin "SW[12]"
    Warning (15610): No output dependent on input pin "SW[13]"
    Warning (15610): No output dependent on input pin "SW[14]"
    Warning (15610): No output dependent on input pin "SW[15]"
    Warning (15610): No output dependent on input pin "SW[16]"
Info (21057): Implemented 11032 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 28 input pins
    Info (21059): Implemented 64 output pins
    Info (21060): Implemented 9 bidirectional pins
    Info (21061): Implemented 10862 logic cells
    Info (21065): Implemented 2 PLLs
    Info (21062): Implemented 67 DSP elements
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 72 warnings
    Info: Peak virtual memory: 811 megabytes
    Info: Processing ended: Fri May 22 21:46:42 2015
    Info: Elapsed time: 00:01:19
    Info: Total CPU time (on all processors): 00:01:17


